Organization of the Thesis

There are five parts in this thesis. Chapter 1 is the introduction. We describe the motivation and organization of this thesis. In Chapter 2, we describe the experimental setup and the method of normalizing the Vth variation (Takeuchi plot) used in experiments. In Chapter 3, the variability study based on the V_th variation and the

3

effects of temperature, drain bias, and substrate bias of strained n-MOSFETs will be examined. Moreover, the enhanced V_th variation caused by stress-induced interface traps was proposed. In Chapter 4, by applying similar analysis, we will discuss the variability for strained p-MOSFETs. Finally, the summary and conclusion will be included in Chapter 5.

4

Fig. 1.1 Example of random threshold voltage fluctuations. Closely located identically designed 4k transistors are measured [1.3].

5

Chapter 2

Experimental Setup and V

_th

Variation

2.1 Introduction

As devices are scaled to the nanoscale dimension, it is important to understand random fluctuations. Since there are many possible microscopic causes, it is desirable to understand the mechanism of variability. Therefore, electrical measurement of random fluctuations is a useful technique to observe such microscopic effects. It is necessary to collect a lot of data of σ (standard deviation) values for various kinds of transistors fabricated by different process conditions. If such data are properly compared and analyzed, it may become possible to extract quantitative information about random fluctuations. Based on this consideration, a simple normalization method for comparing σ values of random threshold voltage fluctuations was proposed. The method was used to compare devices of various origins to analyze the causes of random fluctuations [2.1].

This chapter is divided into two sections. First, we will illustrate the fundamental experimental setup to characterizing CMOS devices. Second, the method of normalizing the Vth variation (Takeuchi plot) used in this thesis will be introduced, and its fundamental theory will be described in detail.

6

2.2 Experimental Setup

The experimental setup for the current-voltage measurement of devices is illustrated in Fig. 2.1. Based on the PC controlled instrument environment by HP-IB (GP-IB, IEEE-488 Standard) interface, the complicated and long-term characterization procedures during analyzing the behaviors in MOSFETs can be easily achieved. As shown in Fig. 2.1, the equipments, including the semiconductor parameter analyzer (HP 4156C), low leakage switch mainframe (HP E5250A), dual channel pulse generator (HP 8110A), cascade guarded thermal probe station and a thermal controller, provides an adequate capability for measuring the device characteristics. In addition, programs written by HT-Basic were used to execute the measurement via HP-IB interface.

2.3 Theory of Takeuchi Plot

It is well known that standard deviation of threshold voltage σVth usually

where L is channel length and W is channel width. Here, the coefficient A_VT (Pelgrom coefficient) can be taken as a normalized σVth with respect to the channel size, and is often used for evaluating and comparing fluctuations. By using A_VT, fair comparison between FETs with different geometry is possible. However, it is not suitable for comparing different kinds of transistors, where gate oxide thickness or threshold voltage is not necessarily identical. According to a simple model [2.3], the σVth

7 dominated by RDF is expressed by

1 4 channel impurity concentration, and Wdep is the width of the channel depletion layer.

Note that the dependence on L and W is common to (2.1) and (2.2). At the same time, the NsubWdep term is also included in the theoretical calculation of Vth as

sub dep

where Tinv is the electrical gate oxide thickness at inversion, and VO is defined as

    0 1

O fb s

V V . V. (2.5) Here, Vfb is the flat-band voltage, and ФS is the surface band bending at inversion.

8

Equation (2.4) indicates that σVth is proportional to T (V_{inv th}V ) / LW_O . In the Takeuchi plot, σV_th is normalized by T (V_{inv th}V ) / LW_O . Here, T_inv, V_th , V_O, L and W are the median values of the devices.

As an example, the measured data for σVth are plotted in Fig. 2.2(a). The slope A_VT is a conventional index of V_th variation and depends on V_th and T_inv. The measurement of σVth is also plotted with a different x-axis as shown in Fig. 2.2(b), where the slope is defined as B_VT [2.4]. The slope is an indicator of V_th variation. It is found that BVT remains constant with varying Vth and Tinv. It is due to Vth variation normalized in terms of T_inv and V_th. Therefore, B_VT is a useflu tool to investigate the origins of Vth variation.

Moreover, when Vth variation is dominated solely by RDF, the analytically calculated B_VT equals q/3_ox (about 1.2). Since the analytical calculation does not take the effect of the discreteness of the channel dopant on the channel surface direction into account, it underestimates B_VT. According to the 3-D technology computer-aided design (3-D-TCAD) calculation, which takes the discreteness of the channel dopant fully into account, B_VT of RDF is 1.5 [2.1]. In Fig. 2.3, B_VT of PMOS is 1.7 and close to that of RDF (which is 1.5). This result indicates that the Vth

variation of PMOS is dominated by RDF [2.5-2.9]. B_VT of NMOS is 2.7 and larger than that of RDF (which is 1.5). This result indicates that Vth variation of NMOS is dominated not only by RDF but also by other factors.

To explain the larger B_VT of NMOS, a Boron clustering model is proposed. In general, it is well known that Boron atoms with high concentration are clustered in Si [2.10]. Some Boron atoms of channel dopants gather with weak binding force and act as one Boron cluster. In this case, the charge of a carrier q is replaced with nq and

9

Fig. 2.4 shows the relationship between B_VT and the number of clustering Boron atoms, n, calculated by the analytical and 3-D-TCAD calculation [2.11]. On the basis of the 3-D-TCAD calculation and measured B_VT of 2.7, actual B_VT can be explained by a cluster of five Boron atoms.

10

Fig. 2.1 The experimental setup and environment for basic I-V measurement of MOSFET’s.

Fig. 2.1 The experimental setup and environment for basic I-V measurement of MOSFET’s.

Fig. 2.1 The experimental setup for the current-voltage measurement of MOSFETs.

Automatic controlled characterizations system is setup based on the PC controlled instrument environment.

11

(a)

(b)

Fig. 2.2 Measured NMOS V_th variation with (a) slope A_VT and (b) slope B_VT. The slope AVT depends on Vth and Tinv while BVT does not [2.4].

12

Fig. 2.3 Example of Takeuchi plots for NMOS and PMOS. BVT of NMOS is larger than that of PMOS.

0 2 4 6 8

0 5 10 15 20 25

 V th (m V )

0.5 0.5 -1 inv th 0

T (V +V )/LW (nm V μm )

Control(N) B

_VT

=2.7

Control(P) B

_VT

=1.7

13

Fig. 2.4 The analytical calculation and the 3D-TCAD simulation results of a Boron clustering model [2.11].

14

Chapter 3

The Variability of Strained n-MOSFETs

3.1 Introduction

Recently, researches have shown an increasing interest in the strain technology.

Strained silicon technology is essential for the continuation of the scaling in MOSFET devices, owing to its high impact on carrier mobility and thus on drive current improvement [3.1]. When applied to the direction of the channel, tensile strain improves the performance of n-MOSFET devices, while compressive strain is beneficial for p-MOSFET devices. The local strain, such as capping layer, SiGe on variation in scaled bulk CMOS. It already profoundly affects the SRAM design [3.2]

and, in logic circuits, causes statistical timing problems [3.3]. In both cases, statistical variability restricts threshold and supply voltage scaling, causing static and dynamic power dissipation problems [3.4].

In this chapter, we will demonstrate V_th variation which can be suppressed by advanced strained-Si technology meanwhile the performance of devices keeps improved for n-MOSFETS. Extensive comparisons between strained and control

15

n-MOSFETs will be justified on examining the effects of temperature, drain bias, and substrate bias. In addition, the impact of stress-induced random interface traps fluctuation (RIF) on the device variability will also be verified.

3.2 Device Preparation

The devices were fabricated by the advanced 40nm CMOS technology at UMC.

The schematic cross section diagram of n-MOSFET splits is shown in Fig. 3-1. In this figure, Fig. 3-1(a) is the control device, Fig. 3-1(b) is the SiC on S/D device (uniaxial-strain) and Fig. 3-1(c) is the SiC on S/D-E device (uniaxial-strain). Both n-MOSFETs are <100> channel on (100) substrate. All these test devices have 12Å EOT gate oxide with SiON process. Devices with various areas were measured for Takeuchi plots. The device threshold voltage was measured by the extrapolation and constant current method.

3.3 Performance of Strained n-MOSFETs

In Fig. 3.2, the I_on-I_off curve of the SiC S/D-E devices show 23.6% current gain over the control (bulk-Si) and 13% improvement for typical SiC S/D devices.

Moreover, Fig. 3.3 shows 67% enhancement of I_D,sat for the SiC S/D-E devices over the control. As shown in Fig. 3.4, the peak mobility of the SiC S/D-E devices exhibits a 94% increase in comparison to the control.

3.4 Variability of Strained n-MOSFETs

Figure 3.5 shows the Takeuchi plot of the n-MOSFET splits, in which the B_VT of strained devices are smaller than that of control. In particular, SiC S/D-E shows the

16

reduction of 26% to the control in Fig. 3.6. To explain the smaller BVT of strained devices, we consider that the strain effect could reduce the number of clustering Boron atoms by using Boron clustering model [3.5]. In addition, the Carbon diffuses out to the vicinity of S/D junction and substrate region is also capable of describing the suppression of Vth variation. The diffusion of interstitial diffuser species such as Boron through annihilation of interstitials (Boron TED) will be reduced by the Carbon, resulting in decreasing Vth variation [3.6-3.7]. In other words, as the stressors (Carbon) diffuse out to the vicinity of S/D junction and channel region, the effective dopant concentration is decreased, and Vth fluctuation is improved. Moreover, the SiC S/D and SiC S/D-E with low C% have larger B_VT than that of SiC S/D-E due to less channel strain effect [3.8]. Therefore, the more the strain in channel is, the smaller the B_VT of device becomes.

3.5 Factors Affecting the V

th

Variation

3.5.1 Effect of the Temperature

To understand the effect of the temperature on strained n-MOSFETs, devices are measured at elevated temperature (85^OC). It was found that BVT is larger at 85^OC in Fig. 3.7 for all the n-MOSFET device splits. As the temperature increases, the thermal fluctuation of the lattice becomes larger. The carrier moving through the crystal is easier to be scattered by a vibration of the lattice results in enhanced B_VT. Moreover, a higher leakage current of device at elevated temperature is also a source of increasing B_VT, i.e.,

17

where m is the body effect coefficient [3.9]. Therefore, the Vth variation is increased as the device is heated. Also, the result shows the amount of enhanced B_VT of SiC S/D and SiC S/D-E is similar to that of control which exhibits no degradation compared to the control.

3.5.2 Effect of the Drain Bias

The effect of the drain bias (V_DS) on V_th variation was also examined. Fig. 3.8 shows the Vth variation increases with increasing drain bias. This is because the depletion region around the drain junction becomes wider as the drain bias increases such that more ionized impurities are produced. SiC S/D and SiC S/D-E exhibit weak dependence of V_th variation on the drain bias as a result of the strain effect. Because there are less Boron atoms clustered in strained-Si, the effect of RDF becomes minor.

It indicates good SCE immunity (small DIBL) and this immunity is a primary requirement for small variability because devices are operated at high drain bias.

3.5.3 Effect of the Substrate Bias

Dependence of BVT on substrate bias (VBS) is shown in Fig. 3.9. BVT increases as substrate bias increases. It is well known that ionized impurities in depletion region are the major source of Vth variation. By applying substrate bias, more ionized impurities are produced since the bulk depletion width becomes wider results in enhanced BVT. Also, based on the same reasoning as that in section 3.4.2, SiC S/D and SiC S/D-E show better B_VT as substrate bias increases due to the strain effect which could reduce Vth variation.

18 3.5.4 Discussion of the Bias Effect

Figure 3.10 shows the variances in depletion width under different bias conditions. It is well known that the depletion width increases with increasing bias.

Moreover, random ionized impurities in the depletion region are the dominant source of V_th variation. As substrate concentration is increased, RDF becomes more serious since Vth variation is proportional to Nsub1/4

as derived in section 2.3, i.e., dramatic as the substrate concentration is increased.

3.6 Impact of Stress-induced Random Interface traps

3.6.1 Introduction

A large number of variation effects of both types have been revealed in many studies. Examples include: random dopant fluctuation (RDF) [3.10], line-edge roughness (LER) [3.11-3.12], and local oxide thickness variations [3.13]. In addition to these effects, recent study [3.14] has proved that process-induced random interface traps fluctuation (RIF) are required for proper interpretation of Vth variation in CMOS technologies. However, so far, none has been reported on the effect of stress-induced random interface traps. Thus, in this section, we will discuss the device variability after FN and PBTI stresses.

19 3.6.2 Charge Pumping Measurement

The charge pumping (CP) measurement is efficient for the reliability characterization. However, the charge pumping measurement can’t be used reliably in the small size devices due to the small charge pumping current and the gate leakage current. Recently, a low leakage Incremental Frequency Charge Pumping (IFCP) measurement for CMOS devices has been developed [3.15] to get more reliable results. Since charge pumping current is proportional to the generated interface traps, we use IFCP to evaluate the interface traps for the stressed devices.

3.6.3 Variability After FN Stress

Figure 3.11 shows the measured ICP for studying the vertical field effect using FN stress (V_GS-V_th= 2V for 300sec). It is observed that the I_CP of SiC S/D-E is larger than the others which could be attributed to the Carbon out-diffusion [3.16] and the I_CP of SiC S/D is the smallest one which exhibits better reliability. The average interface traps generation among these three devices during stress time, from 100sec to 500sec, is shown in Fig. 3.12. The number of interface traps increases with increasing stress time. Since the positions and number of charges trapped at the SiO₂/Si interface randomly vary, it is possible for this variation to affect the V_th variation [3.17]. Thus, the comparison of BVT during stress time is shown in Fig. 3.13 to verify the possibility. Also, Fig. 3.14 shows the relationship of B_VT with interface traps. It is obvious that BVT is aggravated after FN stress. Moreover, the aggravated B_VT is proportional to interface traps. This result indicates that stress-induced interface traps are the dominant source of the enhanced Vth variation after FN stress.

20 3.6.4 Variability After PBTI Stress

By applying similar analysis, we apply the PBTI stress (VGS-Vth= 2V at 85℃) to produce the interface traps at the SiO₂/Si interface which would show a more aggravated BVT. Fig. 3.15 shows the measured ICP after PBTI stress (VGS-Vth= 2V for 300sec, at 85℃). Based on the same reasoning as described in 3.5.3, the I_CP of SiC S/D-E is larger than the others. In addition, the ICP of all n-MOSFET splits after PBTI stress are larger than that of FN stress. It indicates that more interface traps are produced after PBTI stress as shown in Fig. 3.16. Fig. 3.17 shows the comparison of B_VT during stress time. Fig. 3.18 shows the relationship of B_VT with interface traps.

We observe a more aggravated BVT after PBTI stress which is attributed to the more interface traps generation, but the aggravated B_VT is also proportional to interface S/D and SiC S/D-E is very important and even more than in control devices.

It was also found that the amount of enhanced BVT is larger in strained devices.

The distance between inversion layer electrons and interface traps located at the SiO2/Si interface can be a key parameter to explain the impact of strain on the enhanced B_VT. Fig. 3.20 schematically shows the electron distributions in the Δ2 and Δ4 valleys in the inversion triangular potential, as well as the location of Nit and Nsub

21

scattering centers [3.18]. It is well known that in strained-Si, most electrons are in the twofold valleys (Δ2) where the electron distribution is more confined near the interface than in the fourfold valleys (Δ4). Thus, the Coulomb scattering limited by interface traps becomes strong causing a great impact on enhanced V_th variation.

22

(a)

(b)

(c)

Fig. 3.1 The cross-section view of the experimental devices. (a) control, (b) SiC S/D (uniaxial-strain), and (c) SiC S/D-E devices (uniaxial-strain). All of them

are <100> channel on (100) substrate.

23

Fig. 3.2 The Ion-Ioff characteristics of all the nMOSFET devices. SiC S/D-E device can improve the driving current by an increment of 23% over the control (Si-bulk).

1000 1200 1400 1600

1E-8 1E-7 1E-6

Control(N) SiC S/D SiC S/D-E

I

off

(A /u m )

I

_on

(uA/um)

nMOSFETs

13.5% 10.1%

24

Fig. 3.3 The ID-VD curves of the splits and control. The SiC S/D-E device shows 67%

I_D,sat enhancement over control devices.

0.0 0.2 0.4 0.6 0.8 1.0

0 4 8 12 16 20

I D (m A )

V _D (V)

Control(N) SiC S/D SiC S/D-E V

_G

-V

_th

=1V

27%

67%

25

Fig. 3.4 A 94% electron mobility enhancement is obtained for the long SiC S/D-E device compared to the control.

0.4 0.5 0.6 0.7 0.8 0.9 1.0 100

200 300 400 500 600 700

SiC S/D-E Universal

 e ff (cm

2

/V -s )

E _eff (MV/cm)

Control(N) SiC S/D

94%

32%

26

Fig. 3.5 Takeuchi Plots of n-MOSFETs. The slope indicates the value of BVT.

0 2 4 6 8

0 5 10 15 20 25 30 35

 V th (m V )

0.5 0.5 -1

inv th 0

T (V +V )/LW (nm V μm )

Control(N) B

_VT

=2.7 SiC S/D B

_VT

=2.2

SiC S/D-E w/ low C% B

_VT

=2.1

SiC S/D-E B

_VT

=2.0

27

Fig. 3.6 Comparison of BVT for n-MOSFETs. BVT of SiC S/D-E shows a 26%

improvement to the control.

0.0 0.5 1.0 1.5 2.0 2.5 3.0

B

VT

( m V n m

-0.5

V

-0.5

 m )

Control SiC S/D

SiC S/D-E w/ low C%

SiC S/D-E

26%

28

Fig. 3.7 Dependence of BVT on the temperature. Strained devices show no degradation compared to control devices.

1.0 1.5 2.0 2.5 3.0 3.5

B

VT

( m V n m

-0.5

V

-0.5

 m )

SiC S/D-E SiC S/D

25

^O

C 85

^O

C

Control

29

Fig. 3.8 VDS dependence of σVth. Strained devices exhibit weak dependence of Vth

variation on the drain bias.

0.0 0.2 0.4 0.6 0.8 1.0 1.2 0

5 10 15 20 25

V _DS (V)

 V th (m V )

Control(N)

SiC S/D

SiC S/D-E

30

Fig. 3.9 Dependence of BVT on VBS. Strained devices show better BVT as substrate bias increases.

0.5 0.0 -0.5 -1.0 -1.5 -2.0 1.5

1.8 2.1 2.4 2.7 3.0 3.3

B

VT

( m V n m

-0.5

V

-0.5

 m )

V _BS (V)

Control(N)

SiC S/D

SiC S/D-E

31

Fig. 3.10 Schematic diagram of the depletion region profile under different bias conditions.

32

Fig. 3.11 The charge pumping currents of all the n-MOSFETs after FN stress.

-1.0 -0.5 0.0 0.5 1.0

0 50 100 150 200 250 300 350 400

V _gh (V)

I cp @ 1 M H z (p A )

FN stress@25

^O

C V

_G

-V

_th

=2V,300sec

Control(N)

SiC S/D

SiC S/D-E

33

Fig. 3.12 The average interface traps of all the n-MOSFETs after FN stress.

1 2

3 4 5 6

N it (x10

10

/c m

2

)

Stress Time(x100sec)

FN stress@25

^O

C,V

_G

-V

_th

=2V Control(N)

SiC S/D SiC S/D-E

2 3 4 5

34

Fig. 3.13 The evolution of BVT for all the n-MOSFETs during FN stress.

1 2.0

2.4 2.8 3.2 3.6

B

VT

( m V n m

-0.5

V

-0.5

 m ) FN stress@25

^O

C,V

_G

-V

_th

=2V Control(N)

SiC S/D SiC S/D-E

Stress Time(x100sec)

2 3 4 5

35

Fig. 3.14 Relationship of BVT with interface traps for all the n-MOSFETs after FN stress.

2.4 2.8 3.2 3.6 4.0 4.4 4.8 2.0

2.4 2.8 3.2 3.6

B

VT

( m V n m

-0.5

V

-0.5

 m ) FN stress@25

^O

C,V

_G

-V

_th

=2V Control(N)

SiC S/D SiC S/D-E

N _it (x10 ¹⁰ /cm ² )

36

Fig. 3.15 The charge pumping currents of all the n-MOSFETs after PBTI stress.

-1.0 -0.5 0.0 0.5 1.0

0 100 200 300 400 500

V _gh (V)

I cp @ 1 M H z (p A ) PBTI stress@85

^O

C V

_G

-V

_th

=2V,300sec

Control(N)

SiC S/D

SiC S/D-E

37

Fig. 3.16 The average interface traps of all the n-MOSFETs after PBTI stress.

2 1 3 4 5 6 7

N it (x10

10

/c m

2

)

Stress Time(x100sec)

PBTI stress@85

^O

C,V

_G

-V

_th

=2V Control(N)

SiC S/D SiC S/D-E

2 3 4 5

38

Fig. 3.17 The evolution of BVT for all the n-MOSFETs during PBTI stress.

1 2.0

2.4 2.8 3.2 3.6

B

VT

( m V n m

-0.5

V

-0.5

 m )

Stress Time(x100sec)

PBTI stress@85

^O

C,V

_G

-V

th

=2V Control(N)

SiC S/D SiC S/D-E

2 3 4 5

39

Fig. 3.18 Relationship of BVT with interface traps for all the n-MOSFETs after PBTI stress.

2 3 4 5 6 7

2.0 2.4 2.8 3.2 3.6 4.0

B

VT

( m V n m

-0.5

V

-0.5

 m )

N _it (x10 ¹⁰ /cm ² )

PBTI stress@85

^O

C,V

_G

-V

_th

=2V Control(N)

SiC S/D

SiC S/D-E

40 stress and (b) PBTI stress.

0

41

Fig. 3.20 Schematics of the valley configuration in Si and strained-Si inversion layers to illustrate the larger σVth in strained devices after stress.

42 realize the high-speed logic CMOS devices. Recently, various strain technologies have been utilized to enhance the drive current. It is necessary to understand the introduced uniaxial and biaxial strains in n-MOSFET or p-MOSFET devices. Initially, the typical mobility enhancement of n-type strained-Si is much larger than that of p-type devices. Several techniques have been further developed to enhance the p-MOSFET performance, i.e., SiGe on S/D device [4.1]. Materials with same crystal structure but different lattice are good candidates for the strain engineering. The SiGe has been successfully incorporated in the source and drain of p-MOSFET devices to strain the channel compressively and increase the hole mobility. However, as the devices being scaled, a variety of process-induced variations will need to be overcome.

One of the most critical issues is V_th variation. We have demonstrated in previous chapter that strained n-MOSFET with embedded SiC on source and drain could suppress variability.

In this chapter, we will demonstrate V_th variation is suppressed by advanced strained-Si technology meanwhile the performance of devices keeps improved for p-MOSFETs. Extensive comparisons between strained and control p-MOSFETs will be justified on examining the effects of temperature, drain bias, and substrate bias. In addition, the impact of stress-induced random interface traps fluctuation (RTF) on the

43 device variability will be also verified.

4.2 Device Preparation

The devices were fabricated by the advanced 40nm CMOS technology at UMC.

The schematic cross section diagram of p-MOSFET splits is shown in Fig. 3-1. In this figure, Fig. 4-1(a) is the control device, Fig. 4-1(b) is the SiGe on S/D device (uniaxial-strain) and Fig. 4-1(c) is the SiGe on S/D with EDB (Embedded Diffusion Barrier, an undoped SiGe layer) device (uniaxial-strain). Both p-MOSFETs are <110>

channel on (100) substrate. All these test devices have 12Å EOT gate oxide with SiON process. Devices with various areas were measured for Takeuchi plots. The

channel on (100) substrate. All these test devices have 12Å EOT gate oxide with SiON process. Devices with various areas were measured for Takeuchi plots. The

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