Chapter 1. Introduction
1.6. Organization of Thesis
This thesis is organized as follows: The important parameters about transistors and CMOS inverter, the sputter systems, and fabrication method are presented in Chapter 2. In Chapter 3, the novel fabrication process of the ambipolar TFTs is described introduced in detail, important parameters such as mobility, threshold voltage, subthreshold swing and on-off ratio are also described. The experimental results, including the IDS-VDS characteristic, IDS-VGS
characteristic, voltage gain, dynamic behaviors are discussed in Chapter 4.
Finally, the conclusions of this thesis are presented in Chapter 5.
Chapter 2
Principles and Theories
Important parameters associated with transistor and CMOS inverter are presented in this chapter. Besides, the principle of sputter system is described detail. Finally the operational principle for TFTs is described.
2.1. Important parameters of TFTs
The quality of a transistor can be examined through several parameters such as a high mobility, a threshold voltage (VT) close to 0, and a small subthreshold swing (S.S).
2.1.1. Mobility ()
Under the external bias field, carriers can transport in the material. It is called mobility. The value of mobility can be defined in both linear and saturation regions.
(i)When the gate voltage (VG) is low, the transistor works in linear region. The drain current (ID) is linear to the VG. The ID can be expressed in terms of Eq.
(2-1).
I µC V V V (2-1) where
C is the gate oxide capacitance per unit area,
W is channel width, L is channel length,
V is the threshold voltage.
If V is much smaller than V V, ID can be approximated as:
I µC V VV (2-2) The transconductance (gm) is defined as
g
|VD=const. =
µCV (2-3) Therefore, can be obtained by
µ
g (2-4) (ii)When V is larger thanV , the characteristic of TFTs is in saturation region.
The ID can be expressed as:
I µC V V (2-5) Followed by taking square of the ID, this term is taken differentiation to the
VG, which can be expressed as:
µ (2-6)
can be expressed in Eq. (2-7).
µ "
(2-7)
2.1.2 Threshold voltage (VT)
The VT of a MOSFET is defined as the VG where an inversion layer forms at the interface between the insulating layer and the substrate of the transistor.
Conventionally the VG at which the electron density at the interface is the same as the hole density in the neutral bulk material is called the VT. Practically speaking, the VT is the voltage at which there are sufficient electrons in the inversion layer that provides a low resistance conducting path between source and drain of MOSFET. If the VG is below the VT, the transistor is turned off and ideally there is no current from the drain to the source of the transistor. As shown in Fig. 2-1, if the VG is above the VT, the transistor is turned on, due to there being many electrons in the channel at the oxide-silicon interface, creating a low-resistance channel where charges can flow from drain to source.
2.1.3 Subthreshold swing (S.S)
Subthreshold swing (S.S in V/dec) is a typical parameter to describe the control ability of gate toward channel. It is defined as the amount of VG required to increase/decrease ID by one order of magnitude. Subthreshold swing, indicated in Fig.2-1, should be independent of VD and VG. However, in reality, S.S. might increase with drain voltage due to short-channel effects such as charge sharing, avalanche multiplication, and punchthrough-like effect. The S.S.
is also related to VG due to undesirable factors such as serial resistance and interface states.
Fig. 2-1 Threshold voltage and subthreshold swing diagram
2.1.4 On-off ratio
On-current represents for the ID when transistor is in on state. Contrary, off-current means the ID when transistor is in off state. When the on/off current ratio is large, the leakage current can be regarded as negligible.
2.2. Important Parameters of CMOS Inverter 2.2.1. Voltage Gain
In electronics, gain is a measure of the ability of a circuit (often an amplifier) to increase the power or amplitude of a signal. It is usually defined as the mean ratio of the signal output of a system to the signal input of the same system.
Voltage gain can be expressed as in Eq. (2-8) Voltage gain =##$%&
'( (2-8)
2.2.2. Dynamic behavior
Dynamic behavior is an important parameter for CMOS inverter. Propagation delay and power dissipation are the key analysis in dynamic behavior. The delay of the CMOS inverter is a performance metric for how fast the circuit is. Fig.2-2 shows this delay is dependent upon the RC charging or discharging of the load
capacitor by the PMOS or NMOS devices respectively and provides a quantitative feel for the time that is taken by the output of the inverter to completely respond to a change at its input.
Fig.2-2 Charging and discharging process
Table 2-2 lists the definitions of temporal parameters of digital circuits. All percentages are of the steady state values.
Table 2-2 Parameters of digital circuits
Graphical representation of dynamic behavior is shown in Fig. 2-3.
Fig. 2-3 Graphical depiction for dynamic behavior
2.3 Principle of Sputter Deposition
Sputter deposition is a physical vapor deposition (PVD) method on their agglomerates thin films. Sputtering is a process whereby atoms are ejected from a solid target material due to strike of the target by energetic ions on target.
Figure. 2-4 (a) shows the construction of a sputter system. The primary particles for the sputtering process can be supplied in a number of ways, for example by a plasma, an ion source, an accelerator or by a radioactive material emitting alpha
particles. As shown in Fig. 2-4(b), argon (Ar) was ionized under high electrical field. The target particle is deposited on the substrate by Ar+ striking on the target.
(a)
(b)
Fig. 2-4 (a) Sputter system diagram and (b) Sputter mechanism diagram.
Sputter system
high rate. RF sputtering works well to produce highly insulating oxide films but only with the added expense of RF power supplies and impedance matching
high rate. RF sputtering works well to produce highly insulating oxide films but only with the added expense of RF power supplies and impedance matching networks. Fig
respectively.
Fig. 2-4 (
Sputter system has two operate modes
requency) mode. The common arrangement for a D.C.
the target material in negative
high rate. RF sputtering works well to produce highly insulating oxide films but only with the added expense of RF power supplies and impedance matching
Figs. 2-4(c)
(c) DC mode of
has two operate modes
The common arrangement for a D.C.
negative bias state, while The desired operating pressure is
rotary pump and a high vacuum pump such as turbo pump or . An inert gas, such as argon, is admitted to the chamber by a fine
The sputtered atoms are neutrally charged and so are by the magnetic trap. Charge build
RF sputtering where the sign of the anode
high rate. RF sputtering works well to produce highly insulating oxide films but only with the added expense of RF power supplies and impedance matching
and (d) show DC sputter
mode of sputter system of sputter system.
has two operate modes
The common arrangement for a D.C.
bias state, while The desired operating pressure is achieved
and a high vacuum pump such as turbo pump or . An inert gas, such as argon, is admitted to the chamber by a fine
The sputtered atoms are neutrally charged and so are
by the magnetic trap. Charge build-up on insulating targets can be avoided with where the sign of the anode
high rate. RF sputtering works well to produce highly insulating oxide films but only with the added expense of RF power supplies and impedance matching The common arrangement for a D.C.
bias state, while the
achieved by using a suitable vacuum
and a high vacuum pump such as turbo pump or . An inert gas, such as argon, is admitted to the chamber by a fine
The sputtered atoms are neutrally charged and so are
up on insulating targets can be avoided with where the sign of the anode
high rate. RF sputtering works well to produce highly insulating oxide films but only with the added expense of RF power supplies and impedance matching
show DC sputter system and RF
sputter system and (d) Radio of sputter system.
direct current) The common arrangement for a D.C. sputter
the substrate
by using a suitable vacuum
and a high vacuum pump such as turbo pump or . An inert gas, such as argon, is admitted to the chamber by a fine
The sputtered atoms are neutrally charged and so are
up on insulating targets can be avoided with where the sign of the anode-cathode bias is varied at a high rate. RF sputtering works well to produce highly insulating oxide films but only with the added expense of RF power supplies and impedance matching
and a high vacuum pump such as turbo pump or . An inert gas, such as argon, is admitted to the chamber by a fine
The sputtered atoms are neutrally charged and so are unaffected up on insulating targets can be avoided with cathode bias is varied at a high rate. RF sputtering works well to produce highly insulating oxide films but only with the added expense of RF power supplies and impedance matching
by using a suitable vacuum system, and a high vacuum pump such as turbo pump or . An inert gas, such as argon, is admitted to the chamber by a fine
unaffected up on insulating targets can be avoided with cathode bias is varied at a high rate. RF sputtering works well to produce highly insulating oxide films but only with the added expense of RF power supplies and impedance matching and a high vacuum pump such as turbo pump or . An inert gas, such as argon, is admitted to the chamber by a fine
unaffected up on insulating targets can be avoided with cathode bias is varied at a high rate. RF sputtering works well to produce highly insulating oxide films but only with the added expense of RF power supplies and impedance matching system,
2.4 Operational Basics of Field Effect Transistors
Generally, thin film transistors (TFTs) are composed of four components:
substrate, semiconductor (also called active layer), insulator and electrodes.
The configuration of these elements with two different structures, one is top contact and the other is bottom contact TFTS, are depicted in Fig. 2-5. The electrical characteristics of TFTs can be adequately described by models developed for inorganic semiconductors.
Fig. 2-5 Schematic view of (a) top contact and (b) bottom contact TFTs
The TFTs could be divided into two parts, according to the type of charges transported by the semiconductor. In semiconductors with n-type channel, the charges transported are negative. On the other hand, in semiconductors with
biased positively with respect to the grounded source electrode, they operate in the depletion mode, and the channel region is depleted of carriers resulting in high channel resistance. When the gate electrode is biased negatively, they operate in the accumulation mode and a large concentration of carriers is accumulated in the transistor channel, resulting in low channel resistance. For n-type TFT operation, the electrode polarity is reversed and the majority carriers are electrons instead of holes. For instance, a p-type semiconductor is shown in Fig. 2-6 (a) When VD=VS=VG =0V, a negative bias is forced on the gate to form the ohmic current ID. After that, when VD=VS=0V and VG<0V, the gate current would across the insulator layer and some area of insulator-semiconductor interface would bend the band gap of the semiconductor. Then, the accumulation region is formed as shown in Fig. 2-6(b). The ohmic contact between source and drain electrodes leads to additional charges. When positive bias are applied on the gate electrode, an opposite curved band gap would occur in the insulator-semiconductor interface. This result conducts the depletion region of carriers. The higher bias on the gate electrode, the larger depletion the region expands. Finally, all of the semiconductor layer will be depleted. The voltage across the insulator and semiconductor layers depends on the position of the channel which is a functional relationship when drain voltage has strongly
negative bias effect
accumulation mode: (a) VD=VS=VG=0 V, (b) VD=VS= 0 V, VG VS = VD = 0 V, VG >0, (d) VS= 0 V, VG
negative bias effect
Fig. 2-6
accumulation mode: (a) VD=VS=VG=0 V, (b) VD=VS= 0 V, VG VS = VD = 0 V, VG >0, (d) VS= 0 V, VG
negative bias effect as shown in Fig. 2
Schematic of organic field
accumulation mode: (a) VD=VS=VG=0 V, (b) VD=VS= 0 V, VG VS = VD = 0 V, VG >0, (d) VS= 0 V, VG
shown in Fig. 2
Schematic of organic field
accumulation mode: (a) VD=VS=VG=0 V, (b) VD=VS= 0 V, VG VS = VD = 0 V, VG >0, (d) VS= 0 V, VG
shown in Fig. 2-6 (d).
Schematic of organic
field-accumulation mode: (a) VD=VS=VG=0 V, (b) VD=VS= 0 V, VG VS = VD = 0 V, VG >0, (d) VS= 0 V, VG accumulation mode: (a) VD=VS=VG=0 V, (b) VD=VS= 0 V, VG VS = VD = 0 V, VG >0, (d) VS= 0 V, VG ＜＜＜＜VD＜＜＜＜
＜
＜＜
＜0.
effect transistors operation in accumulation mode: (a) VD=VS=VG=0 V, (b) VD=VS= 0 V, VG
＜
Chapter 3.
Experimental Method
The device fabrication and processing parameters are described in detail. The method of fabrication process of CMOS-like inverter is also presented in this chapter.
3.1 Experimental Steps 3.1.1 Substrates Cleaning
The dimensions of substrate (si) are 2 cm x 2 cm. The substrate were cleaned by DI water for 5 minutes and HF solution (HF: H2O=1: 100) for 10 seconds, respectively. Sequentially, the cleaning was completed by blowing off the moisture and baking at 100℃ for 2 hours.
3.1.2 Inorganic Active Layer Deposition
The sputter system with a background pressure < 8 × 10-6 torr shown in Fig.
3-1 was employed to deposit a-IGZO thin films. The deposition was came out at
RF power = 80W, pressures working at 8 x 10-6 torr, oxygen and argon flow rate are equal to 0.6 sccm and 0.8 sccm, respectively.
Fig. 3-1 Sputter system
3.1.3 Annealing Process
Using atmospheric anneal furnace in nitrogen ambience to rearrange a-IGZO lattice again. After annealing process, the electrical characteristic of the device is better than the device without annealing. Fig. 3-2 shows the instrument of atmospheric anneal furnace.
Fig. 3-2 Tube furnace
3.1.4 Organic active layer and metal electrodes deposition
The thermal evaporation system with background pressure about 3 x 10-6 shown in Fig. 3-3 was employed to deposit the pentacene layer and gold (Au) electrodes. The evaporation rate of pentacene was about 0.3~0.4 Å /sec.
Subsequently, the Au electrodes were deposited onto the active layer with an evaporation rate of 1~1.5 Å /sec at a pressure of 5 x 10-6 torr.
Fig. 3-3(a) A thermal evaporation system and (b) the photo of the thermal evaporated facility.
3.2 The fabrication process of a-IGZO/Pentacene TFTs
The bottom gate a-IGZO TFT structure was adopted in this study and the fabrication produces are depicted in Figure 3-4. The unit TFT was fabricated on heavily doped (n++) si wafer with 100-nm thick thermally grown oxide layer as the gate electrode and insulator, respectively. A 40-nm-thick a-IGZO film was deposited on to serve as the active channel (RT) by RF sputtering and the deposition was done in an oxygen atmosphere (~8 x 10-6) without any
intentional substrate heating. After deposited a-IGZO film, pentacene layer was deposited by thermal coater. Finally, the Au source/drain electrodes were patterned through a stencil mask by thermal evaporation. Finally, two identical transistors were interconnected with each other to complete the CMOS inverter. All of our device characterizations were carried out in the dark at RT by using a semiconductor parameter analyzer (Keithley 4200).
(A)Start with n++Si / thermal oxide wafer & wafer clean
(B)Deposit a-IGZO thin film with sputter, no intentional heat
(C) Deposit pentacene layer by thermal coater
(D)Thermal evaporation of Au source/drain electrode (40nm)
(E)Ambipolar TFT is Composed of 2 single devices
Fig. 3-4 Process of ambipolar TFT flow chart (A) Start with n++Si / thermal oxide wafer & wafer clean, (B) Deposit a-IGZO thin film with sputter, no intentional heat, (C) Deposit pentacene layer by thermal coater, (D) Thermal evaporation of Au source/drain electrode (40nm) and
(E) Ambipolar TFT is Composed of 2 single devices
3.3 Electical Measurement and Morphology analyses 3.3.1 Film Morphology
An atomic force microscope (AFM) shown in Fig. 3-5 was utilized to measure the morphology of deposited active layer. The AFM was set to tapping mode and the probe oscillation frequency was 300 Hz. The tapping mode overcame the limitations arose due to thin layer of the condensed phase that formed on most sample surfaces in an ambient imaging environment. The grain size and shape of pentacene are critical when the pentacene crystals deposited on the different insulator layers. Measurements of the grain morphology by AFM were operated in the atmospheric condition. As shown in Fig. 3-6, pentacene thin films with three kinds of thicknesses, 20, 30, 40 nm, were measured by atomic force microscope (AFM). The roughness of 20, 30, and 40nm thick films were 0.162 nm, 0.151 nm, 0.137 nm, respectively.
Fig.3-5 A schematic model of AFM.
Fig. 3-6 (from left to right) AFM images of 20, 30, 40 nm thick a-IGZO films.
3.3.2 Electrical characteristics of OTFT devices
The electrical characteristics of the devices, such as degradation and hysteresis, can be evaluated by Keithley 4200 semiconductor analyzer. In addition, the relationship between IDS-VGS and IDS-VGS curves can be extracted from measurement results.
The relationship between wafers surfaces and active layers will affect the Subthreshold swing (S.S). Annealing process will cause the Threshold voltage (Vth) shift.
Chapter 4.
Results and Discussion
4.1 Optimization of the Characteristics of a-IGZO Thin Film Transistors
In order to control the electrical characteristics of a-IGZO film, TFT with the channel deposited by optimized deposition conditions (Ar / O2 flow rate =10 sccm/0.6 sccm) was fabricated. However, post annealing process strongly affects the electrical properties of a-IGZO film; it is one of the key parameter to control the characteristics of TFT behavior. As shown in Fig. 4-1(a), the threshold voltage (Vth) shifted negatively after annealing at 350 ℃ in N2
environment for 2 hours. Fig. 4-1(b) shows the IDS-VDS characteristics of the a-IGZO TFT after annealing at 350 ℃ for 1 hour. According to Figs. 4-1(a) and (b), the transfer characteristics of a-IGZO TFTs were optimized by adjusting oxygen/argon ratios during RF sputter and varying different post-annealing conditions.
Fig.4-1 (a) IDS-VGS curves of a-IGZO TFT with different annealing time.
(b) IDS-VDS curves of a-IGZO TFT after annealing.
4.1.1. Discussions
In IDS-VGS curves, the post annealing time from 0 to 2 hour in a half hour increment. It is noted that when the annealing time is over than 2 hour; TFTs do not exhibit an appreciable electrical characteristic and thus, are omitted from this plot. Consider the behavior of annealing time beyond 2 hour, the decrease of VTH is possibly associated with crystallization (i.e., grain boundary-inhibited transport).
4.2 Characteristics of Pentacene/a-IGZO Ambipolar TFTs
In order to optimize the electrical characteristics, several combinations of thicknesses were investigated. First, at by fixing a-IGZO thickness at 40 nm, change pentacene with thickness from 20 to 40 nm were fabricated and measured electrical property are shown in Figs. 4-2 (a) to (c). The reason for choosing a-IGZO thickness at 40 nm is that the thicker films can accumulate more carriers to attain high voltage gain.
(a)
(b)
(c)
Fig. 4-2 Thickness effect on devices (a) pentacene = 20 nm, IGZO = 40nm (b) pentacene = 30 nm, IGZO = 40nm and (c) pentacene and IGZO = 40 nm
When thicknesses of a-IGZO and pentacene films are 40 nm and 20 nm, respectively, a-IGZO layer will suppress pentacene layer's IDS-VDS curves.
Increasing pentacene layer to 40 nm, the current is not saturated at high VDS. It is noted that at the thickness of pentacene layer of 40 nm and a-IGZO layer of 20 nm, p-type layer will also suppress the n-type's electrical characteristics. Fig. 4-3 shows the effect of IDS-VDS curve.
Fig. 4-3 IDS-VDS curves (a-IGZO/pentacene 20nm/40nm)
The optimal thicknesses of a-IGZO layer and pentacene layer were found
thin film (30nm) were deposited in order on the Si substrate with a thermally grown SiO2 layer (100nm). Au was used as source and drain electrodes by thermal evaporation. Without any passivation layer, the TFT characteristics were successfully measured in ambient air. IDS-VGS curves are shown in Fig. 4-4.
On/off current ratio is decreased when VDS is increased. Take n-type operation for example, when VDS > VGS, holes are induced and injected into active layer
On/off current ratio is decreased when VDS is increased. Take n-type operation for example, when VDS > VGS, holes are induced and injected into active layer