Chapter 3. Experimental Method
3.2 The Fabrication Process of a-IGZO/Pentacene TFTs
The bottom gate a-IGZO TFT structure was adopted in this study and the fabrication produces are depicted in Figure 3-4. The unit TFT was fabricated on heavily doped (n++) si wafer with 100-nm thick thermally grown oxide layer as the gate electrode and insulator, respectively. A 40-nm-thick a-IGZO film was deposited on to serve as the active channel (RT) by RF sputtering and the deposition was done in an oxygen atmosphere (~8 x 10-6) without any
intentional substrate heating. After deposited a-IGZO film, pentacene layer was deposited by thermal coater. Finally, the Au source/drain electrodes were patterned through a stencil mask by thermal evaporation. Finally, two identical transistors were interconnected with each other to complete the CMOS inverter. All of our device characterizations were carried out in the dark at RT by using a semiconductor parameter analyzer (Keithley 4200).
(A)Start with n++Si / thermal oxide wafer & wafer clean
(B)Deposit a-IGZO thin film with sputter, no intentional heat
(C) Deposit pentacene layer by thermal coater
(D)Thermal evaporation of Au source/drain electrode (40nm)
(E)Ambipolar TFT is Composed of 2 single devices
Fig. 3-4 Process of ambipolar TFT flow chart (A) Start with n++Si / thermal oxide wafer & wafer clean, (B) Deposit a-IGZO thin film with sputter, no intentional heat, (C) Deposit pentacene layer by thermal coater, (D) Thermal evaporation of Au source/drain electrode (40nm) and
(E) Ambipolar TFT is Composed of 2 single devices
3.3 Electical Measurement and Morphology analyses 3.3.1 Film Morphology
An atomic force microscope (AFM) shown in Fig. 3-5 was utilized to measure the morphology of deposited active layer. The AFM was set to tapping mode and the probe oscillation frequency was 300 Hz. The tapping mode overcame the limitations arose due to thin layer of the condensed phase that formed on most sample surfaces in an ambient imaging environment. The grain size and shape of pentacene are critical when the pentacene crystals deposited on the different insulator layers. Measurements of the grain morphology by AFM were operated in the atmospheric condition. As shown in Fig. 3-6, pentacene thin films with three kinds of thicknesses, 20, 30, 40 nm, were measured by atomic force microscope (AFM). The roughness of 20, 30, and 40nm thick films were 0.162 nm, 0.151 nm, 0.137 nm, respectively.
Fig.3-5 A schematic model of AFM.
Fig. 3-6 (from left to right) AFM images of 20, 30, 40 nm thick a-IGZO films.
3.3.2 Electrical characteristics of OTFT devices
The electrical characteristics of the devices, such as degradation and hysteresis, can be evaluated by Keithley 4200 semiconductor analyzer. In addition, the relationship between IDS-VGS and IDS-VGS curves can be extracted from measurement results.
The relationship between wafers surfaces and active layers will affect the Subthreshold swing (S.S). Annealing process will cause the Threshold voltage (Vth) shift.
Chapter 4.
Results and Discussion
4.1 Optimization of the Characteristics of a-IGZO Thin Film Transistors
In order to control the electrical characteristics of a-IGZO film, TFT with the channel deposited by optimized deposition conditions (Ar / O2 flow rate =10 sccm/0.6 sccm) was fabricated. However, post annealing process strongly affects the electrical properties of a-IGZO film; it is one of the key parameter to control the characteristics of TFT behavior. As shown in Fig. 4-1(a), the threshold voltage (Vth) shifted negatively after annealing at 350 ℃ in N2
environment for 2 hours. Fig. 4-1(b) shows the IDS-VDS characteristics of the a-IGZO TFT after annealing at 350 ℃ for 1 hour. According to Figs. 4-1(a) and (b), the transfer characteristics of a-IGZO TFTs were optimized by adjusting oxygen/argon ratios during RF sputter and varying different post-annealing conditions.
Fig.4-1 (a) IDS-VGS curves of a-IGZO TFT with different annealing time.
(b) IDS-VDS curves of a-IGZO TFT after annealing.
4.1.1. Discussions
In IDS-VGS curves, the post annealing time from 0 to 2 hour in a half hour increment. It is noted that when the annealing time is over than 2 hour; TFTs do not exhibit an appreciable electrical characteristic and thus, are omitted from this plot. Consider the behavior of annealing time beyond 2 hour, the decrease of VTH is possibly associated with crystallization (i.e., grain boundary-inhibited transport).
4.2 Characteristics of Pentacene/a-IGZO Ambipolar TFTs
In order to optimize the electrical characteristics, several combinations of thicknesses were investigated. First, at by fixing a-IGZO thickness at 40 nm, change pentacene with thickness from 20 to 40 nm were fabricated and measured electrical property are shown in Figs. 4-2 (a) to (c). The reason for choosing a-IGZO thickness at 40 nm is that the thicker films can accumulate more carriers to attain high voltage gain.
(a)
(b)
(c)
Fig. 4-2 Thickness effect on devices (a) pentacene = 20 nm, IGZO = 40nm (b) pentacene = 30 nm, IGZO = 40nm and (c) pentacene and IGZO = 40 nm
When thicknesses of a-IGZO and pentacene films are 40 nm and 20 nm, respectively, a-IGZO layer will suppress pentacene layer's IDS-VDS curves.
Increasing pentacene layer to 40 nm, the current is not saturated at high VDS. It is noted that at the thickness of pentacene layer of 40 nm and a-IGZO layer of 20 nm, p-type layer will also suppress the n-type's electrical characteristics. Fig. 4-3 shows the effect of IDS-VDS curve.
Fig. 4-3 IDS-VDS curves (a-IGZO/pentacene 20nm/40nm)
The optimal thicknesses of a-IGZO layer and pentacene layer were found
thin film (30nm) were deposited in order on the Si substrate with a thermally grown SiO2 layer (100nm). Au was used as source and drain electrodes by thermal evaporation. Without any passivation layer, the TFT characteristics were successfully measured in ambient air. IDS-VGS curves are shown in Fig. 4-4.
On/off current ratio is decreased when VDS is increased. Take n-type operation for example, when VDS > VGS, holes are induced and injected into active layer due to electric field between gate and drain electrode. Mobility of 0.02 and 4.57 cm2 V/s were estimated for holes and electrons, respectively.
Fig. 4-4 IDS-VGS curve of optimized thicknesses of a-IGZO /pentacene layer
4.2.1. Discussions
There have several interesting phenomena observed during optimizing the thickness of a-IGZO/ pentacene. In the Figs. 4-2(a) and 4-3, at low VGS, the current was not saturated at high VDS, instead, it increased steeply. For example, when operated in n-type region, VGS and VDS are positively biased, when VDS-VGS>0, VDS can be treated as 0 while VGS as negative. Thus, when the voltage difference becomes larger than the amount pentacene film can sustain, holes accumulate under the drain electrode. Both electrons in n-type region and holes in p-type region contribute to the current at this moment.
4.3 Complementary Metal-Oxide-Semiconductor-Like inverter
A CMOS-like inverter was fabricated combining two ambipolar TFTs containing a-IGZO/pentacene layers. The cross-sectional view of this CMOS-like inverter and equivalent circuit are shown in Figs. 4-5 (a) and (b).
Fig.
both
constantly biased at ±50V. Our inverter about
inverter in n studies for CMOS grain boundary
conventional CMOS inverter, our CMOS quadrants
Fig. 4-5 CMOS
In the inverter circuit, the gate served as an input node and was shared by both transistors. The input voltage (Vin) range was 0V~ ±50V while V
constantly biased at ±50V. Our inverter about 70. In Fig.
inverter in n-type region.
studies [22, 23] reported the for CMOS and
grain boundary
conventional CMOS inverter, our CMOS
quadrants, because the ambipolar TFTs have both n (a)
CMOS-like inverter (a) planar structure diagram (b) simplified
In the inverter circuit, the gate served as an input node and was shared by transistors. The input voltage (Vin) range was 0V~ ±50V while V
constantly biased at ±50V. Our inverter
70. In Fig. 4-6, maximum gain up to 70 was obtained when operating the type region.
reported the
and small hysteresis
grain boundary in the surface between active layer and conventional CMOS inverter, our CMOS
because the ambipolar TFTs have both n
like inverter (a) planar structure diagram (b) simplified circuit diagram
In the inverter circuit, the gate served as an input node and was shared by transistors. The input voltage (Vin) range was 0V~ ±50V while V
constantly biased at ±50V. Our inverter
, maximum gain up to 70 was obtained when operating the type region. In p-type region the maximum gain up to 53.
reported the voltage gain of devices hysteresis
in the surface between active layer and conventional CMOS inverter, our CMOS
because the ambipolar TFTs have both n
like inverter (a) planar structure diagram (b) simplified circuit diagram
In the inverter circuit, the gate served as an input node and was shared by transistors. The input voltage (Vin) range was 0V~ ±50V while V
constantly biased at ±50V. Our inverter exhibits
, maximum gain up to 70 was obtained when operating the type region the maximum gain up to 53.
voltage gain of devices hysteresis were observed.
in the surface between active layer and conventional CMOS inverter, our CMOS
because the ambipolar TFTs have both n
like inverter (a) planar structure diagram (b) simplified circuit diagram
In the inverter circuit, the gate served as an input node and was shared by transistors. The input voltage (Vin) range was 0V~ ±50V while V
exhibits a high gain value (
, maximum gain up to 70 was obtained when operating the type region the maximum gain up to 53.
voltage gain of devices about
like inverter (a) planar structure diagram (b) simplified
In the inverter circuit, the gate served as an input node and was shared by transistors. The input voltage (Vin) range was 0V~ ±50V while V
a high gain value (
, maximum gain up to 70 was obtained when operating the type region the maximum gain up to 53.
about 10. Higher voltage gain
like inverter (a) planar structure diagram (b) simplified
In the inverter circuit, the gate served as an input node and was shared by transistors. The input voltage (Vin) range was 0V~ ±50V while V
a high gain value (-dV
, maximum gain up to 70 was obtained when operating the type region the maximum gain up to 53.
Higher voltage gain teresis implies
in the surface between active layer and insulator
like inverter can be operated in 2 type and p-type behavior.
like inverter (a) planar structure diagram (b) simplified
In the inverter circuit, the gate served as an input node and was shared by transistors. The input voltage (Vin) range was 0V~ ±50V while VDD was dVout/dVin) , maximum gain up to 70 was obtained when operating the type region the maximum gain up to 53. Previous Higher voltage gain implies small insulator. Unlike like inverter can be operated in 2 type behavior.
In the inverter circuit, the gate served as an input node and was shared by was ) , maximum gain up to 70 was obtained when operating the Previous
This makes the circuit design simpler, and can be adopted for display circuit applications.
Fig. 4-6 Voltage transfer curve and their corresponding gains of ambipolar TFTs operated in the (a) first and (b) third quadrant
Dynamic response was performed by measuring the output signal Vout with respect to the input signal Vin using an oscilloscope with 1MΩ input impedance.
At the frequency of 1 Hz, the input 30 V can invert to ~15 V. Until to the frequency of 20 Hz, the inverting action shows a little RC delay at on and off
operating in the frequency range of 1Hz and 20 Hz. The rising (tr) and falling times (tf) at 20 Hz in our inverter was measured to be about ~2ms and 0.9 ms, respectively. Previous study published in APL [22] reported that the devices only can operate in the frequency less than 10 Hz. Our devices hence have the fastest frequency response in previous research. [22, 23]
Fig. 4-7 The dynamic behavior of CMOS-like inverter. The top diagram is at 1 HZ. The bottom diagram is at 20 HZ
4.3.1. Discussions
In section 4.2, another interesting phenomenon observed during the optimization of thickness is the relationship between thickness and voltage gain.
Figures. 4-8 (a) and (b) show the voltage gain diagrams. In Fig. 4-8 (a), pentacene layer and a-IGZO thin film are both at 20 nm. In Fig. 4-8 (b) pentacene layer and a-IGZO thin film are both both at 40 nm. Their IDS-VGS
characteristic has no obviously different. However, the voltage gain is higher because the thicker active layers. The reason is that thicker films can accumulate more carriers to attain high voltage gain.
(a) (b)
Fig. 4-8 Voltage gain of CMOS-like inverter. Pentacene/a-IGZO films are
The other important parameters of CMOS inverter is dynamic behavior. To make a faster inverter (work at high frequency), Propagation delay (tP) is a key.
So to reduce the propagation delay (tP), it is necessary increase kn 、kp 、W/L and VDD and reduce the load capacitance (CL).
Another important issue of CMOS inverter is power consumption. The power consumption can be expressed in Eq. (4-2).
E = Energy / transition =)
" C" V## (4-1) P = Power =2 " f " E f " C" V## (4-2) f : cycle / sec
The output is the opposite of the input is an ideal model of inverter. However, in order to make a low power consumption inverter, load capacitance (CL), work frequency and VDD need to be reduced. However, the power is a function of
consumption and time delay, increase of W/L implies the larger size, and VDD
increase results in more power dissipation.
NMOS logic also can be the CMOS inverter. However, the resistance cause more power consumption when Vdd is high, as shown in Fig. 4-9. For our devices, increasing W/L of the ambipolar TFT near drain side can reduce the resistance achieve low power consumption.
Fig. 4-9 Power consumption issue from NMOS logic and CMOS-like inverter
Chapter 5
Conclusion And Future Works
5.1 Conclusions
In this study, we fabricated ambipolar TFTs through a hybrid route by combining organic/oxide semiconductors. These ambipolar TFTs can be a CMOS-like inverter circuit. The contributions of this study are: (1) Largest gain and fastest operation frequency are achieved in CMOS-like inverter. (2) leading the researches regarding to the CMOS-like inverter composed of a-IGZO and pentacene.
First of all, in order to control the electrical characteristics of a-IGZO TFTs, optimization by adjusting oxygen/argon ratios during RF sputter and adjustment of post-annealing conditions were required. Annealing time over than 2 hour; TFTs do not exhibit an appreciable characteristic. One hour is the best time duration of annealing process for our device with 100-nm thick thermally grown oxide layer as the insulator. Both n channel and p channel behaviors of the ambipolar TFTs were analyzed together with their
corresponding inverter circuits. The optimal thicknesses of a-IGZO layer and pentacene layer were found to be 40nm and 30nm, respectively. The initial inverter showed a high voltage gain about 70 under the supply voltage (VDD) of 50V. Dynamic behavior of the inverter at 20 Hz rising (t r) time and falling times (t f) were measured to be about ~2ms and 0.9 ms, respectively.
The largest gain and fastest dynamic behavior were achieved in our COMS-like inverter.
Fig. 5-1 CMOS-like inverter achievements
Overall, a-IGZO/pentacene TFTs exhibits an ambipolar behavior with balanced field effect mobility and qualifies themselves as promising candidates
for the applications in AMFPDs. Table 5-1 compares our latest results (the gain value of 70) and similar studies reported elsewhere. [12, 22].
Table 5-1 Summary & comparison for ambipolar TFTs and inverters
5.2 Future Works
Using platinum (Pt) as the electrodes and buffer layer between active layer and insulator is a way to enhance hole’s transport. Platinum enables both n-type and p-type characteristics for a-IGZO at the same time. The fabrication process can be simplified.
Operating voltage, output frequencies, and gain values of CMOS-like inverter will be further studied and optimized. These ambipolar TFTs open a viable way to fabricate high performance logic devices with mechanical flexibility and good reliability in air ambient.
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