Organization of This Dissertation - 對於利用氮化矽局部電荷儲存之快閃記憶元件可靠度問題的探討

Chapter 1 Introduction

1.3 Organization of This Dissertation

1.3 Organization of This Dissertation

We will address each issue in this dissertation, which is thus organized in the following manner. An overview of the Flash memory cell technologies and the concepts of a trapping-nitride localized-charge storage cell (the NBit cell here) and its reliability issues have been presented here. We will discuss the mechanisms that dominate the charge loss in chapter 2. In chapter 3, the charge gain behavior is addressed. Vt drop-down in an over-erased cell is characterized in chapter 4. Various read disturb modes are modeled in chapter 5. We will disclose the causes of erase speed degradation in chapter 6. Conclusions follow in chapter 7.

two-bit-per-cell, localized charge storage

O

N O

n

⁺

n

⁺

G

S D

Bit-S (2

^nd

-bit)

Bit-D (1

^st

-bit)

p-substrate

Fig.1.1 Schematic representation of an NBit cell.

Fig.1.3 Junction bias effect on the reverse read scheme.

Fig.1.2 Concept of reverse read is depicted by the drain depletion region in which the effect of injected charges is screened out.

O

N e- trapped electrons

low

N e- trapped electrons

low V

high V

depletion region

to be read

Bit-S Bit-D

O

N e- trapped electrons

low

N e- trapped electrons

low V

high V

depletion region

to be read

Bit-S Bit-D

0.0 0.4 0.8 1.2 1.6 2.0

V

of Bit-S (V )

V

(V)

Fig.1.4 (a) Definition of the forward- and the reverse-read Vt of Bit-S.

(b) ∆Vt-REV versus ∆Vt-FWD plot of the Bit-S in (a). Operating-V_t window is saturated due to the so-called 2^nd-bit effect.

(a)

e-V

_t-REV

of Bit-S by V

=1.8V O

O N

V

_t-FWD

of Bit-S by V

=1.8V

e-V

_t-REV

of Bit-S by V

=1.8V O

O N

V

_t-FWD

of Bit-S by V

=1.8V

∆ V

t-REV

(V)

∆ V

_t-FWD

(V)

slope ~ 1 slope << 1

Table 1.1 Operating principles and bias conditions of an NBit cell.

Bit-D Bit-S

Vg Vd Vs Vg Vd Vs

Program ( CHE )

^11V ^5V ^0V ^11V ^0V ^5V

Erase ( BTBT HH )

^-3V ^8V ^0V ^-3V ^0V ^8V

Read ( Reverse )

^2.5V ^0V ^1.5V ^2.5V ^1.5V ^0V

Fig.1.6 Two-bits erasing characteristics of an NBit cell. Bit-S Bit-D

D Bit-S Bit-D

D S

Both ERS Bit-S Bit-D

D Bit-S Bit-D

S D

Both PGM Bit-S Bit-D

D Bit-S Bit-D

S D

Bit-D PGM Bit-S ERS Bit-S Bit-D

S DD

Both PGM Bit-S Bit-D

D S

Both PGM Bit-S Bit-D

S D

10

⁰

10

⁴

10

⁵

10

⁶

0 1 2 3 4 5 6 7

erase state

program state

V

(V )

P/E Cycles

10

⁰

10

⁴

10

⁵

10

⁶

0 1 2 3 4 5 6 7

erase state

program state

V

(V)

Retention time (sec.)

Fig.1.7 Vt versus retention time of a fresh NBit cell. The bake temperature is 150C.

Fig.1.8 Endurance characteristics of an NBit cell.

Fig.1.9 Vt versus retention time of a 10K P/E cycled NBit cell. The storage temperature is 25C.

Program-state V

drops down!

10⁰ 10¹ 10² 10³ 10⁴ 10⁵ 0

1 2 3 4 5 6 7

V

(V )

Retention time (sec.)

program state

erase state

Erase-state V

drifts up!

Fig.1.10 Representation of the reliability issues we have observed in an NBit cell.

P/E cycles Storage time

V

High-state V_tloss

Low-state V_tdrift-up, and Read disturb

Low-state V_tdrop-down Cycling window degradation

(Erase speed degradation) Over erase

Operating-V_twindow

P/E cycles Storage time

V

High-state V_tloss

Low-state V_tdrift-up, and Read disturb

Low-state V_tdrop-down Cycling window degradation

(Erase speed degradation) Over erase

Operating-V_twindow

Chapter 2

Charge Loss in a High-Vt Cell

2.1 Motivation

In previous chapter, we have showed that a fresh cell has good charge retentivity (Fig.1.7). However, charge retention in a P/E cycled cell degrades (Fig.1.9). Fig.2.1 shows that charge loss increases with cycle numbers. In addition, this charge loss exhibits strong temperature dependence (Fig.2.2).

It is still controversial about the mechanisms to explain the observed charge loss in the localized trapping-storage cells. Saifunís group has proposed that thermionic emission and then re-distribution or leak-out of the stored electrons are the cause of Vt loss in an un-cycled cell [2.1]. They also claimed that lateral re-distributions of the trapped charges, especially some residual holes, account for the Vt loss in a cycled one [2.2-2.3]. However, we do not find any direct evidence of ì netî residual holes in a cycled cell which is at program state. Meanwhile, we find that the Vt loss is strongly dependent on the applied Vg bias during retention test. Charge loss along the vertical direction is suspected. In the following sections, we would develop the models in detail.

2.2 Experimental

2.2.1 Device Samples

The cell used in this work (and in the dissertation) is made of an n-channel MOSFET with an oxide-nitride-oxide (ONO) gate dielectric structure (Fig.1.1).

Typically, the thickness of each ONO layer is 9nm (top oxide), 6nm and 6nm, and Wg/Lg is 0.38µm/0.48µm. An ONO capacitor (2.5×10⁵µm²) with uniform stress and charge storage is also used. The effect of lateral charge migration can be excluded in this device. The evolution of the flatband voltage (Vfb) of the ONO capacitor with time is monitored to study the charge retention behavior. Finally, a 64Mb chip with a sector size of 512Kb which is composed of such cells is also characterized. It is used to demonstrate that the observed phenomena in a single cell and the utilized methods to characterize it are consistently applicable to a real product.

2.2.2 Characterization Techniques

Two specific methods are utilized to study the lateral spreading of the injected carriers. Assuming that electrons are trapped in the nitride layer above the channel nearby the junction, a Vt versus Vj measurement is used to investigate the lateral extent of the trapped electrons (Fig.2.3 (a)). Here, Vt is defined as the applied gate voltage that induces a drain current of 1µA. These trapped electrons will raise the potential barrier nearby the injection junction. An increased Vt, which is proportional to the trapped electron density, will be measured at a low junction bias (Vj1 in Fig.2.3).

As a sufficiently high junction bias (V_j2 in Fig.2.3) is applied, the junction depletion region will extend toward the channel. The trapped electrons will have little effect on the measured I-V characteristics when they are located within the junction depletion region [2.4]. The trapped electron density and its lateral extent can be estimated by this measurement (Fig.2.3 (b)).

A charge-pumping (CP) method [2.5], which is also able to probe the lateral distribution of trapped charges, is also used. Letís see Fig.2.4 (a). A trapezoidal pulse train (Gate pulse P) with a fixed high level (Vgh) and successively decreasing low levels (Vgl) is applied to the gate of the device. The substrate and the drain are grounded and the source is floating. The charge-pumping current IcpP (=Id=Ib) versus Vgl is measured. The fixed Vgh is sufficiently high to ensure that the entire channel is inverted. By varying Vgl, only the part of channel that undergoes inversion-accumulation-inversion over a pulse cycle contributes to IcpP. Since the trapped electrons (near the drain side) cause an increase of the local flatband voltage, an IcpP shift along the Vgl axis will be observed in a programmed cell. Based on the measured IcpP versus Vgl curves of an un-programmed and a programmed cells (Fig.2.4 (b)), the trapped electron density can be extracted [2.5]. The trapped hole density can be profiled in a similar manner by a pulse train with a fixed low level and successively increasing high levels (Gate pulse E in Fig.2.4 (a)) applied to the gate. The lateral migration of trapped charges in both the program and the erase states can also be estimated by this technique.

2.2.3 Characterization Results

We use the Vt versus Vd characteristics to give an indication of the density and the lateral extent of the trapped electrons in a programmed cell. Fig.2.5 shows the Vt-Vd characteristics of a 100K P/E cycled cell in the program state before and after 24 hours storage. The storage temperature is 85C. It can be seen that the Vt has dropped due to charge loss, however, the shape of Vt versus Vd curves is essentially unchanged and there is no crossover in the Vt versus Vd characteristics before and after 85C, 24 hours storage. This indicates that lateral migration of electrons does not occur. We have also applied the charge-pumping technique to probe the lateral electron extent (Fig.2.6). If the trapped electrons spread laterally during the storage period, an increased Icp will be observed due to the extension of the trapped electron area. As indicated in Fig.2.6, the leftward shift of the Icp implies a decrease of the trapped electron density. However, no clear evidence of lateral electron movement is shown in the charge-pumping characteristics. On the other hand, we find the charge loss is strongly dependent on the applied vertical field during the retention test (Fig.2.7). It gives us a hint that the stored charges may leak out along the vertical direction: from the trapping nitride through the bottom oxide to the substrate.

In order to correlate the Vt loss to charge escape through the bottom oxide, the temporal evolution of the flatband voltage of an ONO capacitor was measured (Fig.2.8). The ONO capacitor has undergone a negative gate stress (-100nA for 1000 seconds, to emulate the P/E cycling effect) and then was programmed to a high-Vt state by +FN injection. Since the structure has uniform charge storage, lateral re-distribution effect of the stored charges can be excluded. Charge loss through the bottom oxide should be the only cause for the flatband voltage shift. The gate bias in the measurement is from Vg=0V to Vg=-6V. The measured results are shown in Fig.2.9. The flatband voltage shift indeed exhibits vertical field dependence, which is similar to the Vt loss behavior we observed in a single cell (Fig.2.7).

2.3 Charge Loss Model

We thus propose the physical mechanism to explain the charge loss behavior in a P/E cycled cell, as shown in Fig.2.10. The field- and temperature-accelerating effects and the cycling-enhanced effect on the charge loss suggest that the nitride charge escape is through thermionic-field emission and subsequent oxide trap-assisted tunneling. Frenkel-Poole model has been recognized to be the dominant charge carrier transport mechanism in nitride [2.6]. According to the model, the emission time

constant τen of an electron in a nitride trap of energy depth of φen below the nitride

where En is the nitride field and εn is the nitride dielectric constant. If the trapped electron density (corresponding to the trap level of φen) is Nen0 right after programming, it will evolve with time as:

In a Frenkel-Poole emission limited condition (i.e, τox in Fig.2.10 sufficiently fast), the nitride charge escape current can be derived as:

assuming that the trapped electron distribution (right after programming) is continuous in the energy spectrum and is with a constant trapping density (Nen0) in the nitride. The corresponding Vt loss would be:

According to Eq. (2.4), Vt and Vfb evolution is linearly dependent on log(t), which is as shown in Fig.2.7 and Fig.2.9 for a single cell and a capacitor, respectively.

Besides, the charge loss is proportional to the square root of the nitride field, which is proportional to (V0-Vg). This is shown in Fig.2.11. Here, V0 is the built-in potential, including the flatband voltage and trapped charge effects, at program state. From a 2D device simulation [2.7], V0 is around 2V in the single cell and 5V in the capacitor.

Learning from Fig.2.7, it is apparent that Vg is an effective accelerating factor for retention lifetime measurement. If we assume that during the discharge time tѽ all the nitride traps with time constants less than tҏ will be completely emptied and all other traps will be unaffected, the memory retention time will be equal to the nitride charge detrapping time (we assume oxide trap assisted tunneling is sufficiently fast.).

According to Eq. (2.1), we would further expect that: calculated to be 2.6 decade/V^0.5 in our sample.

In Fig.2.12, we plot the retention lifetime versus (V0-Vg)^0.5. The symbols represent the measured result. The extracted slope in Fig.2.12 is about 2.75 decade/V^0.5 which is close to the theoretical value of 2.6 decade/V^0.5. The extrapolated memory retention time at Vg=0V is about 10⁷ sec. for ∆Vt=1.5V and is above 10 years for ∆Vt=2.0V.

We have also plotted the retention lifetime versus (V0-Vg)^0.5 of an ONO capacitor as shown in Fig.2.13. The slope is 2.49 dec/V^0.5 which is quite close to the theoretical value (2.6 decade/V^0.5) and the slope of a memory cell (2.75 decade/V^0.5). It implies that the vertical charge loss occurs in an ONO capacitor with uniform charge storage and also in a memory cell with localized charge storage.

In this model, cycling-induced oxide defect is considered to be the stepping stone of the charge loss. Fig.2.14 shows the increase of the charge-pumping current (right axis) of the cell versus cycle numbers. The charge-pumping current is a direct measurement of the density of the interface states (Nit). It can be found that Icp,max

(Fig.2.4(b)) increases with cycle numbers. The growth rate follows a power law with the power factor of 0.5. It is quite consistent with the generation of interface states in a stressed NMOSFET [2.8], which implies that the bottom oxide is damaged during

P/E cycling. It is also suggested that bulk oxide defects (Qox) are also created meanwhile [2.9]. However, itís hard to measure the bulk oxide trap density directly.

We plot the charge loss versus cycle numbers on a log-log plot (Fig.2.14, left axis). A power law dependence with the power factor of 0.24, which is quite close to the generation rate of bulk oxide traps in a stressed NMOSFET [2.8], is obtained. It provides an indirect evidence of the role of oxide trap and its generation during P/E cycling.

2.4 Product Demonstration

The model is successful verified by a single cell and a capacitor. We would like to apply the same field accelerating method to a memory array under real product operation. A 64Mb chip used in this study is fabricated by 0.25µm process with a sector size of 512Kb. The cycling is performed on a MOSAID tester [2.10] and all bits are programmed and erased within one cycle. During retention test, checker-board pattern is used. In other words, each cell has one programmed bit and one erased bit at the same time.

In Fig.2.15, the Vt evolution with retention time at Vg=-3V is measured for a chip before and after 10K cycles. Charge loss is observed for the cycled high-Vt cells. To simplify the notation, the <Vt> is used to represent the mean value of the high-Vt distribution. In Fig.2.16, the field-accelerating effect on the ∆<Vt> is observed and the dependence is quite similar to the single cellís results (Fig.2.7). At both cases, charge loss increases with increasing vertical field. In Fig.2.17, the cycle number dependence of the ∆<Vt> is measured at Vg=-7V. The charge loss increases with the cycle number and a power law dependence with the power factor of 0.223 is observed. Once again, it is close to the power factor of 0.29 obtained in a single cell (Fig.2.14). From Fig.2.15 to Fig.2.17, we know that the single cell and the product are well-correlated, and the validity of field acceleration is confirmed at product level as well as in a single cell.

2.5 Temperature Effect

The temperature-accelerating method is widely used in the retention test of a floating-gate cell [2.11]. We also investigate such application. Fig.2.18 shows the charge loss versus time at T=25C, 85C and 150C, respectively. In addition to the

strong dependence on the bake temperature, the retention loss at 150C shows a saturation behavior. Further study by using a charge-pumping technique reveals that amounts of the interface traps are annealed (Fig.2.18 (b)). We would suspect that trap annealing effect plays a role during the high-temperature bake period.

Letís also apply the high-temperature baking test to a chip. The chip firstly undergoes 10K P/E cycles. Two kinds of retention test procedure are compared. One is purely to bake the chip at 150C for 50 hours, and the other is to apply an extra field acceleration (by Vg=-3V, 18.5 hours) to the chip before baking.

In Fig.2.19, the ∆<Vt>ís of sectors with and without a preceding field acceleration are compared after baking. ∆<Vt(field)> and ∆<Vt(bake)> represent Vt loss due to field acceleration and bake, respectively. Fig.2.20 shows similar results of different accelerating vertical field. Some interesting phenomena are observed. Firstly, regardless of cycle numbers, ∆<Vt(bake)> is reduced if a preceding field acceleration has been applied. Secondly, the overall retention loss is similar for both cases at low cycle numbers, however, it is larger for the field-acceleration-and-then-bake one after 10K cycles. Thirdly, charge loss by field acceleration (∆<Vt(field)> by Vg=-5V, 18.5 hours) could be larger than that by high-temperature bake only (∆<Vt(bake)> at T=150C, 50 hours without a preceding field acceleration) as shown in Fig.2.20. And finally, the same ∆<Vt(bake)> (~0.2V) is found in 10K cycled sectors after strong field acceleration, though the accelerating field and ∆<Vt(field)> are quite different (Fig.2.20).

To investigate the relationship between these two accelerating methods, emulated single cells are firstly cycled up to 10K times. Retention loss is measured firstly by a negative-Vg acceleration with various time, and then by another high-temperature bake at T=150C for 50 hours, as illustrated in Fig.2.21. The ∆Icp,maxís before and after baking are also described. The overall Vt loss (∆Vt(field)+∆Vt(bake)) is a constant value (~0.5V) as ∆Vt(field) is less than 0.3V, and it drops further (about additional 0.2V) when ∆Vt(field) exceeds 0.5V. If the two accelerating factors, temperature and field, are interchangeable, ∆Vt(bake) will increase with decreasing ∆Vt(field). In Fig.2.22, ∆Vt(bake) following various field-accelerating conditions is collected and is plotted along with its preceding ∆Vt(field). ∆Vt(bake) shows a negative linearly correlation with ∆Vt(field) as ∆Vt(field) is less than 0.5V. It implies that both methods are interchangeable if the overall retention loss is within 0.5V. However, if ∆Vt(field)

is more than 0.5V, the following bake would result in an additional, constant Vt loss (~0.2V).

Trap annealing is proposed to explain these phenomena. During high-temperature bake, traps are annealed [2.12-2.14]. As shown in Fig.2.23, the annealing effect would re-fresh the cell [2.14] and the charge leaky paths through the bottom oxide are reduced. Vt loss is thus saturated at 0.5V. However, larger Vt loss may be found by field acceleration since traps are not annealed in this approach. Once the field-accelerated Vt loss exceeds the saturated value (as seen by temperature acceleration), the additional, constant Vt loss in the following bake period is due to the interface state annealing effect.

2.6 A Simple Monitor of Charge Retentivity

In Fig.2.14 and Fig.2.17, we suggest that the bottom oxide damage may be responsible for the retention loss induced by field acceleration, since the power factor (0.223 or 0.29) is quite consistent with the published oxide trap generation rate [2.8].

Since the generation of interface traps is an indicator of the bottom oxide damage,

∆Icp,max (∝∆Nit) is expected to be related to charge loss. In Fig.2.24, a positive correlation is found between a field-induced ∆Vt and the ∆Icp,max. Meanwhile, it has been demonstrated that the bake-induced ∆Vt are also positively correlated with the Icp [2.14-2.15].These results strongly support that the charge loss by both kinds of accelerating method are related to bottom oxide damage. Furthermore, the cycling number dependence of ∆Icp,max of cells of four process conditions is characterized (Fig.2.25). Though the magnitude is difference, the power law dependence still stands and the power factors are similar. After baking at 150C for 50 hours, the corresponding ∆Vtís of these 10K cycled cells are measured (Fig.2.26). A positive correlation between ∆Vt and ∆Icp,max is also identified. It implies that ∆Icp,max after P/E cycling would be a good monitor of the charge retentivity of the NBit cell.

2.7 Summary

Charge loss of the NBit cell at program-state is investigated. It is found that the charge loss is negligible in a fresh cell. Charge loss increases with cycle numbers and shows strong dependence on temperature and the applied vertical field during retention test.

Our study find that lateral re-distribution of trapped charges has little effect in a highly cycled cell. Vt loss is attributed mostly to nitride charges escape by Frenkel-Poole emission and subsequent oxide trap-assisted tunneling. These oxide traps are created during P/E cycling. A linear dependence of the nitride charge loss on the square-root of the electric field is obtained. This model is well confirmed by both the single cell and the product characterization. According to these concepts, a Vg -accelerating technique and a temperature-accelerating method are therefore developed.

No matter which accelerating factors are used, evidences have been provided to demonstrate that the retention loss of NBit cells is related to the bottom oxide damage, i.e. the charge loss path is the same. The field and temperature accelerations are found to be interchangeable. Stress-induced interface state density is a good monitor of cellís retention. In addition, the annealing of interface states would be another source of the observed Vt loss in a highly cycled cell, and the annealing of oxide traps would cause the saturation of Vt loss when baking at high temperature.

10

⁰

10

⁴

10

⁵

10

⁶

0.0 -0.2 -0.4 -0.6 -0.8 -1.0

∆ V

(V)

P/E cycles

Fig.2.1 Charge loss versus cycles of an NBit cell. The bake is at 150C for 24 hours.

10

⁴

10

⁵

2.5 3.0 3.5 4.0 4.5 5.0 5.5

fresh

T=25C T=85C

∆ V

(V)

Retention time (sec.)

100K P/E

Fig.2.2 Program-state charge loss versus retention time in a fresh and a 100K P/E cycled NBit cells. T=25C and 85C.

V _j

∆ V _t wider electron distribution

V

_j2

V

_j1

V _j

∆ V _t wider electron distribution

V

_j2

V

_j1

Fig.2.3 (a) Concept of Vt-Vj measurement to explore the trapped electron extent in an NBit cell. (b) Illustration of Vt-Vj characteristics by which charge lateral extent can be estimated. The dashed one has a wider electron

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