Organization of This Thesis - 具基體雜訊考量之射頻電壓控制振盪器電路設計

Chapter 1 Introduction

1.3 Organization of This Thesis

This thesis is organized as follows. In chapter 2, four types of MOS structure varactor are realized and the high-frequency characteristics of them are compared. In chapter 3, two testkeys corresponding to different isolation structures are designed to verify which structure has better isolation capability. The measured parameters of the testkeys are shown. In chapter 4, design considerations for LC-tank VCO are discussed. In chapter 5, Three 2.4GHz LC-tank VCOs (VCO1, VCO2, and VCO3) are designed and realized in a 0.25-um CMOS process. VCO1 and VCO2 are realized to investigate the influence of substrate noise coupling to the varactors on the output spectrums. VCO3 adopting complementary topology is designed to compare with VCO1 adopting PMOS-only topology. The phase noise of them is compared. In chapter 6, the conclusions and future works are given.

S21

Duplexer Filter

LNA Band Pass

Filter

Band Pass Filter

Frequency Synthesizer

Channel Selection

Fig. 1.1 Generic transceiver architecture.

PFD CP/LPF VCO

÷M

Channel Selection

fREF f_out

Fig. 1.2 Basic phase-locked frequency synthesizer.

n-well p-well p-well

p-substrate

(a)

p-substrate deep n-well

n-well p-well n-well p-well

n+

p-well

Vb

(b)

Fig. 1.3 (a) Isolation structure for varactors fabricated on n-well and (b) Isolation structure for varactors fabricated on p-well with deep n-well.

Chapter 2 High-Frequency Characteristics of Varactors

2.1 Varactor Structures

2.1.1 General Considerations

Design considerations for varactors are summarized as follows [5]:

(1) A high quality factor.

(2) A control voltage range compatible with the supply voltage, ultimately 1 V for single battery cell operation.

(3) A good tunability over the available control voltage range.

(4) A small silicon area, to reduce cost.

(5) A reasonably uniform capacitance variation over the available control voltage range, to make the phase-locked-loop design easier.

Two classes of devices have to be considered: junction structure and MOS (metal-oxide-semiconductor) structure varactors, the latter tuning the capacitance by changing the operation regions (accumulation region, inversion region, and depletion region). In all cases, the devices should be placed in separated wells in order to use the p-n junction between substrate and n-well to isolate substrate noise. The five types of device are therefore p-n junction varactor, n-type MOS varactor (accumulation mode), p-type MOS varactor with deep n-well (accumulation mode), NMOS varactor with deep n-well, and PMOS varactor. The details are described as follows.

2.1.2 P-N Junction Varactor

The cross section of p-n junction varactor is shown in Fig. 2.1. The p-n junction used as varactor must be operated in reverse-biased region and the capacitance value

is controlled by the reverse voltage.

2.1.3 N-type MOS Varactor

The cross section of n-type MOS varactor (accumulation mode) is shown in Fig.

2.2. This structure is widely used as varactor in standard CMOS processes. The device capacitance is given by C=C₀WL, where C₀ is given by

in which and are, respectively, the oxide capacitance and the capacitance of the depletion layer under the gate, per unit area. By applying a positive voltage between the gate

COX C_d

(

Vgate

)

and the source/drain

(

^V_cont

)

the surface is accumulated and the device capacitance equals the oxide capacitance. If the applied voltage is reversed, the surface layer is depleted and the series capacitance decreases. The maximum capacitance , per unit area, of the device corresponds to a heavily accumulated surface and equals

(

^C_max

)

OX OX ε/t

C = . On the other side, a minimum value is reached when the voltage difference between the electrodes equals the threshold voltage. Beyond this point, an inversion layer is formed under the gate. At low frequency this effect brings the value of the device capacitance close to the gate oxide capacitance. At high frequency, where the varactor is assumed to be operated, this effect is not seen and the device capacitance remains at its minimum value. The ratio between and defines the tuning range [4].

(

Cmin

)

Cmax C_min

2.1.4 P-type MOS Varactor with Deep N-well

The cross section of p-type MOS varactor with deep n-well (accumulation mode) is shown in Fig. 2.3. Deep n-well and n-well surrounding the p-well isolate this device from substrate noise. By applying a negative voltage between the gate

(

Vgate

)

and the source/drain the surface is accumulated and the device capacitance equals the oxide capacitance. If the applied voltage is reversed, the surface layer is depleted and the series capacitance decreases. The maximum capacitance , per unit area, of the device corresponds to a heavily accumulated surface and equals

. On the other side, a minimum value

(

^V_cont

)

voltage difference between the electrodes equals the threshold voltage. Beyond this point, an inversion layer is formed under the gate. At low frequency this effect brings the value of the device capacitance close to the oxide one. At high frequency, where the varactor is assumed to be operated, this effect is not seen and the device capacitance remains at its minimum value.

This device has the advantage of a lower parasitic resistance than n-type MOS varactor mentioned in section 2.1.3.

2.1.5 NMOS Varactor with Deep N-well

The cross section of NMOS varactor with deep n-well is shown in Fig. 2.4.

Deep n-well and n-well surrounding the p-well isolate this device from substrate noise.

This device is a three-terminal device. These three terminals are gate

(

Vgate

)

, source/drain , and bulk respectively. The device capacitance is relative to not only the voltage difference between gate and bulk but also the bias voltage of source/drain. It should be noted that, with floating source/drain terminal and using bulk terminal as control voltage node, this device can work like p-type MOS varactor with deep n-well mentioned in section 2.1.4.

(

V_cont

)

2.1.6 PMOS Varactor

The cross section of PMOS varactor is shown in Fig. 2.5. This device works in the strong, moderate, or weak inversion region only, and never enters the

accumulation region. Since the bulk is connected to the power supply , the device does not enter the accumulation region and remains in the weak inversion region for a very wide range of positive voltage between the gate

VDD

(

V_gate

)

and the source/drain [6]. When the voltage difference between the gate and the source/drain is smaller than the threshold voltage, the device enters the strong inversion region and the device capacitance, per unit area, equals

(

^V_cont

)

OX OX ε/t

C = .

2.1.7 Discussion on Varactors

Since the p-n junction varactor is realized in an n-well isolated from the substrate, both ports can be biased above ground. When the p-n junction varactor is used in a VCO circuit, the p+ contact must be connected to the “signal” electrode and the n+ contact must be connected to the “control voltage” electrode to get rid of the n-well to substrate capacitance.

When MOS structure varactors are used in a VCO circuit, the gate

(

V_gate

)

must be connected to the “signal” electrode and the source/drain must be connected to the “control voltage” electrode to get rid of the effect of the parasitic capacitance seen from the source/drain node to AC ground node. For n-type MOS varactor, the parasitic capacitance is the n-well to substrate capacitance. For NMOS varactor with deep n-well, the parasitic capacitance is the n+ contact to bulk capacitance. For PMOS varactor, the parasitic capacitance is the p+ contact to bulk capacitance. For p-type MOS varactor with deep n-well, the parasitic capacitance is the p-well to deep n-well and surrounding n-well capacitance.

(

^V_cont

)

Since the swings at “signal” electrodes of VCOs are typically large, the capacitance of varactors varies with time. Nonetheless, the “average” value of the capacitance is still a function of the control voltage. However, the capacitance variation over each oscillation period results in harmonic distortion of the oscillator

sine.

For MOS structure varactors, the variable capacitance between the gate

(

Vgate

)

and the source/drain is the series connection of the gate oxide capacitance and the depletion region capacitance. The parasitic capacitances between the gate

(

V_cont

)

(

Vgate

)

and the source/drain are mainly overlap and fringing capacitances.

They are assumed to be constant and parallel to the variable capacitance. Then the capacitance tuning range is given as

(

V_cont

)

It is obvious that the parasitic capacitances of the varactor deteriorate the capacitance tuning range and therefore the frequency tuning range of the VCO. The

ratio can increase by increasing the channel length of MOS structure varactors, if the gate area remains the same (at the expense of a lower Q).

min max/C C

The p-n junction varactor suffers from a drawback: the technology scaling lowers the maximum circuit supply voltage and the maximum usable reverse voltage.

However, for the MOS structure varactors, the oxide thickness is reduced and correspondingly the oxide capacitance is increased with the technology scaling. On the other hand, the value of the depletion capacitance underneath the gate, for a given biasing condition, increases at a lower rate. This means that the tuning range is expected, to a first order, to increase with scaling. Moreover, scaled technologies enable to realize MOS structure varactors with better quality factors because the parasitic resistance scales with the channel length [4].

2.2 Layout Designs

As mentioned in section 2.1.7, the p-n junction varactor suffers from a drawback with the technology scaling. Therefore, the p-n junction varactor is not

taken into consideration in this thesis.

All previously discussed MOS structure varactors are realized in a 0.25-um CMOS process. In order to facilitate the comparison among these MOS structure varactors, they all have the same size: L x W x S x B x G=1um x 5um x 1 x 6 x 6, and thus equal gate area. The layout of test structure of n-type MOS varactor is shown in Fig. 2.6. The layout of test structure of p-type MOS varactor with deep n-well is shown in Fig. 2.7. The layout of test structure of NMOS varactor with deep n-well is shown in Fig. 2.8. The layout of test structure of PMOS varactor is shown in Fig. 2.9.

N-type MOS varactor with the size: L x W x S x B x G=1um x 5um x 1 x 6 x 6, is available in the given 0.25-um CMOS process. Thus, for n-type MOS varactor, the measured results can be compared with ADS simulated results. For n-type MOS varactor, the RF model provided by the given 0.25-um CMOS process is capable of describing the behavior in all regions of operation from 100MHz to 20.1GHz.

2.3 Measurement Setup

The measurement of test devices has been done by microwave wafer probing on a bare silicon die (on-wafer measurement) to avoid bond wire, package, and fixture effects. Before an accurate measurement can be made, the test system must first be calibrated. With the impedance standard substrate (ISS), SOLT calibration method has been done to calibrate the test system errors.

Two-port S-parameter measurements are performed from 100MHz to 10GHz by using probe station and HP8510 network analyzer. The ports are defined by the gate

(

Vgate

)

and the source/drain

(

^V_cont

)

terminals. An additional measurement on the OPEN structure has been carried out to de-embed the pad effects.

2.4 Pad De-Embedding

2.4.1 Pad De-Embedding Procedure

The test structures of these four devices shown in Fig. 2.6~Fig. 2.9 not only consist of the actual device-under-test (DUT), but also of parasitic components that largely influence the electrical behavior of the DUT. The parasitic components mainly originate from the contact pads, which connect the RF measurement probes and the silicon wafer. As shown in Fig. 2.10, the parasitic components originating from the contact pads are capacitors and resistors in parallel with the DUT. In order to model the RF behavior of the DUT accurately, the influence of the parasitic components must be subtracted from the measurements on the test structures. The procedure to get rid of the influence of the on-wafer parasitic components is called pad de-embedding.

Contrary to III-V technologies which are manufactured on isolating substrates, the pad parasitic in silicon-based RF test structures is very difficult to calculate accurately by electromagnetic simulations. Therefore, an on-wafer de-embedding method for silicon-based technologies is essential.

All the MOS structure varactors need respective OPEN structures to de-embed the parasitic components originating from the contact pads. The pad de-embedding steps can be summarized as follows.

(1) Measure the S-parameters of the OPEN structure and convert them to Y-parameters.

(2) Measure the S-parameters of the DUT test structure and convert them to Y-parameters.

(3) Subtract the Y-parameters of the OPEN structure from that of the DUT test structure, and then the result is the de-embedded Y-parameters.

The de-embedded Y-parameters can be used to calculate the value of the components in equivalent circuit model. The details are described in section 2.5.

Conversion between Y-parameters and S-parameters is as follows.

Y is the characteristic admittance. 0

2.4.2 Discussion on Pad De-Embedding Methods

The pad de-embedding method used in this thesis is known as Y-parameter subtraction technique, in which the parasitic components in series with the DUT are assumed negligible. Thus, the parasitic components in series with the DUT are not presented in the equivalent circuit of the test structure shown in Fig. 2.10. The complete equivalent circuit of the test structure is shown in Fig. 2.11. The parasitic components in series with the DUT originate from the metal interconnections between the contact pads and the DUT. Y-parameter subtraction technique can de-embed the parasitic components in parallel with the DUT, but it can’t de-embed the parasitic components in series with the DUT. At low frequency, the total impedance of the parasitic components in series with the DUT (not be de-embedded) is much less than that of the DUT. However, for high frequency measurement, the effects of the parasitic components in series with the DUT (not be de-embedded) become significant.

Fig. 2.12~Fig. 2.15 shows the measured and simulated of n-type MOS varactor at 100MHz, 2.5GHz, 5GHz, and 10GHz respectively. is the equivalent series capacitance as described in section 2.5. Of course, the simulated is dependent of frequency due to the intrinsic parasitic inductive effect of the DUT (Fig.

2.16) [7]. Fig. 2.17 shows the measured and simulated Q of n-type MOS varactor at 2.5GHz. All the simulated results are produced by S-parameter simulation in ADS.

Due to Y-parameter subtraction technique, it should be noted here that the measured and Q contain the effects of the parasitic components in series with the DUT. The difference between the measured results and the simulated results is mainly attributed to the effects of the parasitic components in series with the DUT.

The measured is strongly different from the simulated at 10GHz. However, at 100MHz and 2.5GHz, the difference is much smaller.

CS C_S

An advanced pad de-embedding method called three-step de-embedding method [8] [9] can de-embed both the parasitic components in series with the DUT and the parasitic components in parallel with the DUT. The layout of the test structure with the DUT and the corresponding on-wafer de-embedding structures: open, short1, short2, and through, are shown in Fig. 2.18.

2.5 Equivalent Circuit Model

All these four MOS structure varactors are modeled by equivalent series circuit between port1

S C

R −

(

Vgate

)

and port2

(

^V_cont

)

. Using the de-embedded Y-parameters, the impedance between port1 and port2 can be calculated easily at each operating point and frequency as

Y11

The measured of these four MOS structure varactors at 2.5GHz are shown respectively in Fig. 2.19~Fig. 2.22. As shown in section 2.4.2, at low frequency (100MHz, and 2.5GHz), the effects of the parasitic components in series with the DUT (not be de-embedded) result in small difference between the measured and the real . However, the difference between the measured Q and the real Q is obvious. Therefore, the measured Qs of these four MOS structure varactors don’t make sense and are not shown.

The comparison of the measured characteristics among these MOS structure varactors is shown in Table 2.1. As shown in Table 2.1, PMOS varactor has the largest capacitance tuning range and the best area efficiency.

Since the signal swings in the VCOs are large, the instantaneous value of changes throughout the signal period. The effective capacitance of the varactor is average over each period. It is not sufficient to predict the frequency tuning ranges of the VCOs by considering only the absolute maximum and minimum values of . The frequency tuning curves of the VCOs depend on both the signal swings of the VCOs and the capacitance tuning curves of the varactors. For NMOS varactor with deep n-well, the nonmonotonicity of shown in Fig. 2.21 will impair the tuning capability of the VCOs.

p+ n+

n-well

p-substrate

Fig. 2.1 Cross section of p-n junction varactor.

V

gate

V

_cont

n+ poly

n+ n+

n-well

p-substrate

Fig. 2.2 Cross section of n-type MOS varactor.

p-substrate deep n-well

p-well

n-well n-well

p+ p+

n+ n+

p+ poly

V

gate

V

_cont

V

_DD

Fig. 2.3 Cross section of p-type MOS varactor with deep n-well.

p-substrate deep n-well

p-well

n-well n-well

n+ n+

n+ p+ n+

n+ poly

V

gate

V

_cont

GND

V V

_DD

Fig. 2.4 Cross section of NMOS varactor with deep n-well.

p-substrate n-well

p+ p+ n+

p+ poly

V

gate

V

cont

V

Fig. 2.5 Cross section of PMOS varactor.

(a)

(b) (c)

Vgate

Vcont Branch (B)

Group (G) S: 1 (one side)

S: 2 (two side) W

L Vgate

Vcont

Fig. 2.6 The layouts of (a) test structure of n-type MOS varactor, (b) the corresponding de-embedding OPEN structure, and (c) the device.

(a)

(b) (c)

Vgate

Vcont

VDD Vgate

Vcont

VDD

Fig. 2.7 The layouts of (a) test structure of p-type MOS varactor with deep n-well, (b) the corresponding de-embedding OPEN structure, and (c) the device.

(a)

(b) (c)

Vgate

Vcont

VDD GND

Vgate

Vcont GND VDD

Fig. 2.8 The layouts of (a) test structure of NMOS varactor with deep n-well, (b) the corresponding de-embedding OPEN structure, and (c) the device.

(a)

(b) (c)

Vgate

Vcont

VDD VDD

Vgate

Vcont

Fig. 2.9 The layouts of (a) test structure of PMOS varactor, (b) the corresponding de-embedding OPEN structure, and (c) the device.

DUT

Fig. 2.10 The parasitic components originating from the contact pads.

Fig. 2.11 The complete equivalent circuit of the RF test structure [8][9].

-2. 5 -2.0 -1 .5 -1.0 -0 .5 0 .0 0. 5 1.0 1 .5 2.0 2 .5

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3

Cs [pF]

Vga te [V ] M eas ure me nt

S imulat iom

Fig. 2.12 The measured Cs and the simulated Cs of n-type MOS varactor at 100MHz.

-2. 5 -2.0 -1 .5 -1.0 -0 .5 0 .0 0. 5 1.0 1 .5 2.0 2 .5

Fig. 2.13 The measured Cs and the simulated Cs of n-type MOS varactor at 2.5GHz.

-2. 5 -2.0 -1 .5 -1.0 -0 .5 0 .0 0. 5 1.0 1 .5 2.0 2 .5

Fig. 2.14 The measured Cs and the simulated Cs of n-type MOS varactor at 5GHz.

-2. 5 -2.0 -1 .5 -1.0 -0 .5 0 .0 0. 5 1.0 1 .5 2.0 2 .5

Fig. 2.15 The measured Cs and the simulated Cs of n-type MOS varactor at 10GHz.

- 2. 5 - 2.0 - 1 .5 - 1.0 -0 .5 0 .0 0. 5 1.0 1 .5 2.0 2 .5

Fig. 2.16 The simulated Cs of n-type MOS varactor at 100MHz, 2.5GHz, 5GHz, and 10GHz respectively.

-2.5 -2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 2.0 2.5

Fig. 2.17 The measured Q and the simulated Q of n-type MOS varactor at 2.5GHz.

(a) (b)

Fig. 2.18 (a) The layout of the test structure with the DUT. (b) Magnified view of the layout of the de-embedding structures. The pad layout and interconnection layout are equal to the test structure.

- 2. 5 -2.0 -1 .5 -1.0 -0 .5 0 .0 0. 5 1.0 1 .5 2.0 2 .5

Fig. 2.20 The measured Cs of p-type MOS varactor with deep n-well at 2.5GHz.

-2. 5 -2.0 -1 .5 -1.0 -0 .5 0 .0 0. 5 1.0 1 .5 2.0 2 .5

Fig. 2.21 The measured Cs of NMOS varactor with deep n-well at 2.5GHz.

- 2. 5 -2.0 -1 .5 -1.0 -0 .5 0 .0 0. 5 1.0 1 .5 2.0 2 .5

Table 2.1 The comparison of the measured characteristics of different MOS structure varactors.

min

Cs, (pF) C_s,_max(pF)

min s,

max s,

C well area

(um²) n-type MOS varactor 0.3853 1.156 3 1121.2203 p-type MOS varactor with deep

n-well

0.3403 1.134 3.33 1937.5403 NMOS varactor with deep n-well 0.3206 1.203 3.75 1937.5403 PMOS varactor 0.2914 1.139 3.91 1121.3604

Chapter 3 Substrate Noise Isolation Test

3.1 The Structures of Testkeys

All the MOS structure varactors mentioned in chapter 2 are placed in separate wells to isolate substrate noise. N-type MOS varactor and PMOS varactor fabricated on n-well use the p-n junction between n-well and substrate to isolate substrate noise.

P-type MOS varactor with deep n-well and NMOS varactor with deep n-well are fabricated on p-well and surrounded by deep n-well and n-well in order to isolate substrate noise. An experiment is designed to compare the isolation capability of these two structures. The isolation testkey corresponding to n-type MOS varactor and PMOS varactor is show in Fig. 3.1. The isolation testkey corresponding to NMOS varactor with deep n-well and p-type MOS varactor with deep n-well is show in Fig.

3.2. The source window and the receiver window are 20um x 20um p+ or n+ region connected to GSG pads by metal. The space between the source window and the receiver window is 50um. These two testkeys are realized in a 0.25-um CMOS process.

3.2 Measurement Results

The measured parameters of the testkey shown in Fig. 3.1 are shown in Fig. 3.3. The n-well is biased at 0V, 1.25V, and 2.5V respectively. The measured parameters of the testkey shown in Fig. 3.2 are shown in Fig. 3.4. The deep n-well is biased at 0V, 1.25V, 2.5V, and floating respectively. The isolation capability is determined by the value of the p-n junction capacitance between n-well and substrate.

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