Organization of This Thesis

In chapter 1, general background of flash nonvolatile memory, SONOS nonvolatile memory and nanocrystal nonvolatile memory devices is introduced.

In chapter 2, basics of program and erase operation are introduced.

In chapter 3, sample structure, experimental methods and experimental process flow are stated.

In chapter 4, discuss the SiNx:Ge memory electric characteristics, reliabilities, mechanism of Ge dot formation in SiGeN film and role of steam treatment..

Finally, the conclusion is presented in chapter 5

Fig.1-1 The device structure of conventional nonvolatile semiconductor memory.

Fig.1-2 The device structure of SONOS nonvolatile memory.

Poly-Gate

Nitride

Source Drain

SiO2

SiO₂

Poly-Gate

Floating Gate

Source Drain

SiO₂

SiO2

Figure 1-3 The development of the gate stack of SONOS EEPROM

memory devices. The optimization of nitride and oxide films has been the

Figure 1-4 The energy band diagrams of the write/erase operation for a

SONOS device.

Figure 1-5 The device structure of nanocrystal (nano-dots) nonvolatile memory.

Poly-Gate

Drain Source

SiO2

nanocrystal

Chapter 2

Basics principle of nonvolatile memory

2.1 Introduction

For SONOS NVSM, the basics operating principle of ONO structure is that electrons injected from the channel are trapped in the forbidden gap of the silicon nitride film during the program operation. On the other hand, during the erase operation, holes are injected from the substrate into silicon nitride film. If there are charges stored in the silicon nitride film, the threshold voltage can be modified to switch between two distinct values. [2.1]

The relation between bias and energy band bending is a key to understand basics program and erase mechanisms. Fig 2-1 shows energy band diagram of MONOS. The barrier of SiO₂ is about 3.1 eV for electrons in the conduction band of silicon, and 4.78 eV for holes in valance band. The barrier of Si3N4 is about 1.05 eV for electrons in the conduction band of nitride, and 2.85 eV for holes in valance band, the gap for electron between conduction band and trapping level is 0.7 eV, and, for hole between valance band and trapping level is 0.95 eV.

In this chapter, we will discuss program and erase mechanisms from the relation between bias and energy band bending. Fowler-Nordheim Tunneling, hot electron injection, band to band assisted hole injection, channel hole injection will be discussed briefly.

2.2 Basic program mechanisms 2.2.1 Fowler-Nordheim Tunneling

Fowler-Nordheim tunneling is a field-assisted carrier tunneling mechanism [2.2], when a large positive voltage is applied across a metal-ONO-substrate structure, its band stricture will be influenced as indicated in figure 2-2. Due to high electrical field, electrons in the poly-Si conduction band as triangular energy barrier with a width dependent on applied electric field. At sufficient high fields, the width of barrier becomes small enough to tunnel through the barrier from the poly-Si conduction band into nitride electron trap layer.

2.2.2 Hot electron injection

At large drain bias, the minority carriers that flow in the channel are heated by the large electric fields occurred at the drain side of the channel and their energy distribution is shifted higher. This phenomenon gives rise to impact ionization at the drain, by which both minority and majority carriers are generated. The highly energetic majority carriers are normally collected at the substrate contact and from the so-called substrate current. The minority carriers heating occurs when some of the minority carriers gain enough energy to allow them to surmount the SiO₂ energy barrier. If the oxide field favors injection, these carriers injected over the barrier into the gate insulator and give rise to the so-called hot-carrier injection gate current [2.3-2.4]. Figure 2-3 shows the phenomenon of hot electron injection. This mechanism is schematically represented for the case of an n-channel nonvolatile memory.

In MOS devices, the drain voltage should increase beyond the saturation voltage

Vdsat (Vd > Vdsat), the mode can named hot carrier effect. To distinguish from Fowler-Nordheim tunneling, the definition of hot carrier injection in this study is the only condition that the drain is applied bias.

2.3 Basic erases mechanisms

There are three physical mechanisms that can be potentially responsible of erase method in nonvolatile memory with ONO structure, as indicated in figure 2-4. (1) electron escape from the nitride by tunneling through top and bottom oxides; (2) tunneling of holes generated by band-to-band into the nitride layer; and (3) the injection into the nitride of hot holes [5]. Electron almost can’t escape from the nitride for the nitride deep trap. Holes injection is the dominate mechanism in erase operation. In this study, we’ll discuss erase operation from this view.

2.3.1 Fowler-Nordheim Tunneling

Fowler-Nordheim tunneling is a field-assisted electron tunneling mechanism, when a large negative voltage is applied across a metal-ONO-substrate structure, its band stricture will be influenced as indicated on Figure 2-5. Due to high electrical field, holes in the poly-Si valance band as triangular energy barrier with a width dependent on applied electric field. At sufficient high fields, the width of barrier becomes small enough to tunnel through the barrier from the poly-Si valance band into nitride hole trap layer.

2.3.2 Band to band assisted hole injection

In N-channel, when a negative gate voltage and a positive drain voltage are applied

to the cell, electron-hole pairs are generated by BTBT in the drain region [2.6, 2.7]. The holes are accelerated by a lateral electric field toward the channel region and some of them obtain high energy. The injection of such hot holes [2.8] into nitride through the tunnel oxide is used for a new erase operation in N-channel.

2.3.3 Hot hole injection

The mechanism of hot hole injection in P-channel is like to hot electron injection.

Figure 2-7 shows the phenomenon of hot hole injection. It’s reported that hole injection is a erase operation in P-channel device [2.9].

Figure 2-1 Energy band diagram of MONOS

(a)

Figure 2-2 (a) Positive gate voltage applied when use Fowler-Nordheim tunneling to program (b) Energy band representation of Fowler-Nordheim tunneling. Electron in poly-Si conduction band tunnel through the triangular energy barrier.

(a)

Figure 2-3 (a) Positive gate voltage and Positive drain voltage applied when use hot carrier injection to program (b) Energy band representation of hot carrier injection

Figure 2-4 Schematic diagram sketching the possible MONOS erase mechanisms：

electron tunneling through tunneling oxides (E1), electron emission in the nitride and subsequent tunneling through tunneling oxides (E2), hole tunneling into the nitride (H1),

(a)

Figure 2-5 (a) Negative gate voltage applied when use Fowler-Nordheim tunneling to erase (b) Energy band representation of Fowler-Nordheim tunneling to erase.

(a)

Figure 2-6 (a) Negative gate voltage applied when use band-to-band assisted injection to erase (b) Energy band representation of band to band assisted hole injection to erase.

(a)

Figure 2-7 (a) Negative gate voltage and negative drain voltage applied when use hot hole injection to erase. (b) Energy band representation of hot hole injection to erase.

Chapter 3

Sample Structure and Thermal Process

3.1 Sample Structure

Figure 3-1 (a) and (b) show the two different pre-thermal sample structures, labeled as sample I and sample II, in this experiment. The transmission electron microscope (TEM) diagrams are shown in Fig. 3-2 and Fig. 3-3.

First, a 5-nm thermal oxide was grown on p-type Si substrate by dry oxidation in an atmospheric pressure chemical vapor deposition (APCVD) furnace as a tunnel oxide in both samples. Subsequently, in sample I: a 50-nm PECVD SiGeN was deposited on tunnel oxide; in sample II: a 20-nm PECVD SiGeN was deposited on tunnel oxide as charge-trapping layers, followed by the deposition of 20-nm PECVD a-Si layer.

The deposition of the PECVD SiGeN was kept at 200 ℃ in a low pressure of 6 mTorr with SiH4 : GeH4 : NH3 : N2 = 20 sccm : 5 sccm : 30 sccm : 500 sccm and a RF power of 20 W. The N₂ gas was served as the carrier gas to adjust the chamber pressure and make the process gas can easily transport into the process chamber. The low pressure of 6 mTorr during deposition makes the mean free path of electrons and radicals increase, which will improve the uniformity of the thin film [3.1]. The sequent deposited a-Si was at 200 ℃ with SiH₄ : H₂ = 20 sccm : 980 sccm, and a 20W power.

Then, the samples were oxidized in thermal furnace at 900 ℃ in oxygen ambient to form blocking oxide. Besides, a three minutes steam treatment is performed on some

to form a metal/oxide/nitride/oxide/silicon (MONOS) structure.

In short, the difference between sample I and sample II is the thickness of SiGeN layer (thicker in sample I) and with/without capped amorphous Si layer (with Si cap layer in sample II).

3.2 Thermal Process

Fig. 3-4 and Fig. 3-5 indicate the thermal process flow in sample I and sample II.

In sample I, directly oxidize a thick SiGeN layer (sample I) to form blocking oxide by a dry oxidation process with different time or by a 30 min dry oxidation process followed by a 3 minutes steam treatment in thermal furnace at 900 ℃. In sample II, oxidize the amorphous Si layer capped on the SiGeN layer(sample II) to form blocking oxide by a dry oxidation process with different time or by a 30 min dry oxidation process followed by a 3 minutes steam treatment in thermal furnace at 900 ℃. The steam treatment means let in H2O into thermal furnace, the same as wet oxidation. Owing to its smaller size and lower activation energy than O₂ molecules, H₂O molecules are more permeable through the blocking oxide and can passivate dangling bonds in the blocking oxide. The purpose of steam treatment is to strengthen the blocking oxide and improve its quality.

Figure 3-1 (a) Sample structure of sample I (b) Sample structure of sample II.

Si-substrate Tunnel ox. 50A

SiGeN

(a)

Sample I

Si-substrate Tunnel ox. 50A

SiGeN a-Si

Sample II

(b)

Sample I

(a)

(b)

Figure 3-2 The TEM diagram of sample I before thermal oxidation.

Si Substrate

SiGeN Tunnel Oxide

Tunnel Oxide+ SiGeN

Si Substrate

Sample II

Si Substrate Tunnel Oxide SiGeN

a-Si

Tunnel Oxide

SiGeN Si Substrate

a-Si

Directly Oxidize SiGeN Layer to Form Blocking Oxide

Figure 3-4 The thermal process flow of sample I.

Si-substrate Tunnel ox. 50A

SiGeN

Si-substrate a-Si 200A

Blocking ox.

Ge dot Tunnel ox. 50A

SiON Thermal

Oxidation

• Dry

• Dry + steam treatment

Sample I

Oxidize The Amorphous Si Layer Capped on the SiGeN layer to Form Blocking Oxide

Si-substrate Tunnel ox. 50A

SiGeN a-Si

Si-substrate a-Si 200A

Blocking ox.

Tunnel ox. 50A SiON

Thermal Oxidation

•

Dry

•

Dry + steam treatment

Ge dot

Sample II

Chapter 4

Experiment Results and Discussions

4.1 Electrical Characteristics

In previous section, it has been mentioned that there are two methods used to form blocking oxide. In one method, only a dry oxidation process with different time in thermal furnace at 900 ℃ is adopted. In the other method, a dry oxidation process is followed by a 3 minutes steam treatment. Table 4-1 shows the difference conditions performed on sample I and sample II. The Ge nanocrystals embedded SiON layer (the charge storage layer) of a MOIOS memory device is utilized to capture the injected carriers from the channel. When the device is programmed, electrons directly tunnel from the Si substrate through the tunnel oxide by Fowler-Nordheim (F-N) tunneling.

The tunneling electrons are trapped in the forbidden gap of SiON layer and conduction band of Ge nanocrystals in the SiON layer. For the erasion, the holes may tunnel from the valence band of the Si substrate. The tunneling hole recombine with the electrons trapped in the forbidden gap of SiON layer and conduction band of Ge nanocrystals in the SiON layer. The blocking oxide is utilized to prevent the carriers of gate electrode from injecting into the charge-trapping layer by Fowler-Nordheim (F-N) tunneling. The capture of carriers will causes a variation in the threshold voltage and can serve as a memory device.

The capacitance-voltage (C-V) hysteresis of sample I (without capped Si layer) with three different conditions A, B, C and D are shown in Fig. 4-1 (a), (b) and Fig. 4-2 (a), (b), respectively. In 30 and 45 minutes short term dry oxidation (condition A and B),

because the thickness is not thick enough and the quality is not good enough, the blocking oxide can’t block the carriers (electrons or holes) tunneling from gate to charge storage layer. When the dry oxidation time is extended to 60 minutes (condition C), the blocking oxide is thick enough to block the carriers from gate and therefore the way carrier injection turns from gate injection to substrate injection. In condition C, the memory windows are ~1.1V under ±3V C-V sweeping, ~2.4V under ±5V C-V sweeping and ~4V under ±7V C-V sweeping. In condition D (30 minutes dry oxidation followed by 3 minutes steam treatment), the memory window is 0.9V under ±10V C-V sweeping. The retention character of sample I with condition C (60 minutes dry oxidation) is shown in Fig. 4-3. The program curve and erase curve in Fig. 4-3 shift toward positive voltage at the same time because positive oxide trapped charges are created during the program/erase cycles in tunnel oxide and they will de-trap with the retention time [4-1]. As the de-trapping of the positive oxide trapped charges, the threshold voltage will shift to positive side. The schematic plot and are shown in Figure 4-4. The endurance characteristic of sample I with condition C (60 minutes dry oxidation) is shown in Fig. 4-5. There is almost no shift in the threshold voltage after 10⁶ program/erase cycles under ±3V operation.

The capacitance-voltage (C-V) hysteresis of sample II (with capped Si layer) with four different conditions A, B, C and D are shown in Fig. 4-6 (a), (b), and 4-7 (a), (b), respectively. The C-V properties are of the same trends as sample I. In 30 and 45 minutes short term dry oxidation (condition A and B) a gate injection is observed. Also, substrate injections are observed in 60 minutes dry oxidation (condition C) and 30 minutes dry oxidation plus a 3-minute steam treatment (condition D). In condition C, the threshold-voltage shift (memory window, ∆Vt) under ±7V C-V sweeping is ~1.7 V and in condition D (30 minutes dry oxidation followed by 3 minutes steam treatment),

sweeping and ~4.2V under ±10V C-V sweeping. The retention and endurance character of sample II with condition D are shown in Fig. 4-8 and Fig. 4-9. The Auger Electron Spectroscopy (AES) analysis of sample II with condition D is shown in Fig. 4-33 (b).

There is a rise in oxygen signal after steam treatment in AES analysis. The SiON dielectric is oxidized by steam to form SiOx. As a result, the Ge nanocrystals are not embedded in SiON but in SiOx. The program and erase curves in Fig. 4-9 shift to negative voltage at the same time because positive oxide trapped charges are created during the program/erase cycles in both tunnel oxide and the SiOx oxidized from SiON film by steam treatment [4-1]. The schematic plot is shown in Figure 4-10. The positive trapped charges in SiOx oxidized from SiON film will increase with the P/E cycles because of its worse quality than tunnel oxide’s. Therefore, the threshold voltage in the Fig. 4-9 will shift to negative side.

4.1.1 Comparing to Other Memories

Figure 4-11 shows the C-V hysteresis of Ge nanocrystals embedded in SiO2 (Ge nanocrystal only) nonvolatile memory proposed by T. C. Chang et al. [4.2]. Fig. 4-12 shows the C-V hysteresis of SONOS memory and the SiNx layer in the ONO stack is deposited by the same PECVD used in this study. The memory windows in the Ge nanocrystal only NVSM are ~0.4V under ±5V C-V sweeping and ~2V under ±10V C-V sweeping. The memory windows in SONOS only NVSM are ~0.2V under ±5 C-V sweeping and ~0.6V under ±10V C-V sweeping. In this study, a combination of Ge nanocrystal and SONOS NVSM is proposed. The memory windows of sample I with condition C are ~1.1V under ±3V C-V sweeping, ~2.4V under ±5V C-V sweeping and

~4V under ±7V C-V sweeping, as shown in Fig. 4-2 (a). Moreover, The memory windows of sample II with condition D are ~0.6V under ±3V C-V sweeping, ~1.8 V under ±7V C-V sweeping and ~4.2V under ±10V C-V sweeping, as shown in Fig. 4-7 (b). The memory windows both in sample I and sample II are larger than Ge nanocrystal

only NVSM or SONOS only NVSM (table. 4-4) and even larger than the Ge nanocrystal NVSM plus SONOS NVSM. It’s inferred that besides charge trapping units in the Ge nanocrystal and the SiON dielectric, there are additional charge trapping units at Ge/SiON interface. The band diagrams are shown in Figure 4-13.

4.2 Mechanism of Ge Nanocrystals Formation

Kan et al. adopted a two-step RTA process executed on a Si0.54Ge0.46 film to form Ge nano-dots embedded in SiOx dielectric [4.3-4.4] and the 950 N℃ 2 RTA would reduce the Ge atoms and the nanocrystals grew based on the Ostwald ripening mechanism [4.5]. Besides, a method of Ge nano-dots segregated downward until they reach the tunnel oxide surface by Si0.8Ge0.2 layer being wet oxidized in an APCVD reactor has been proposed [4.6-4.8]. In this work, the formation of Ge nanocrystals is only by one step of oxidation of the silicon-germanium-nitride layer, which is simpler than the previous research [4.9] and high-throughput and low cost potentially for industrial consideration.

A thermal furnace process is introduced to form blocking oxide (SiOx or SiON) and segregate Ge atoms in this study. During 900 dry oxidation process, ℃ Si in the SiGeN film more easily combine with O2 than Ge to form SiOx. Because of the low solid solubility of Ge in silicon oxide, the Ge atoms will be segregated downward until they reach the tunnel oxide surface [4.6-4.8] and nucleate to form Ge nano-dots (or Ge nanocrystal) near the tunnel oxide(or gate oxide). Therefore, the SiGeN film will be oxidized to form SiOx film (as blocking oxide); meanwhile, the Ge in the SiGeN film will be segregated to form Ge nano-dots (or Ge nano-crystal) embedded by SiON dielectric near the tunnel oxide.

4.2.1 Directly Oxidize SiGeN Layer as Blocking Oxide ( Sample I )

The different bonds’ wave numbers of Fourier Transform Infrared Rays (FTIR) spectrum are shown in table 4-2 and 4-3 [4.8]. The FTIR spectra of sample I before and after thermal oxidation process are shown in Figure 4-14. The weak bonds such as Si-H, Ge-H, N-H disappear after 900℃ dry oxidation and the appearance of Si-O after oxidation means the SiGeN layer has been oxidized to form SiOx as blocking oxide.

The transmission electron microscope (TEM) diagrams and Auger Electron Spectroscopy (AES) analysis before oxidation and after oxidation with condition A(dry 30 minutes), C(dry 60minutes) are shown in Fig. 4-15 (a), (b) and Fig. 4-16 (a), (b), respectively. The TEM diagram as shown in Fig. 4-15 (a), there is no Ge nanocrystal present in the as-deposited SiGeN film before oxidation and Fig. 4-15 (b) shows that all of the three elements, Si, Ge and N are present in the as-deposited SiGeN film before oxidation. The Ge nanocrystals appear in the TEM diagram after oxidation as shown in Fig. 4-16 (a) and there is a rise of Ge and N signal between 500 and 1300 second in Fig.

4-16 (b), which reveals that the Ge nanocrystals are imbedded in SiON dielectric.

The Raman spectra of sample I before and after 30 minutes thermal oxidation process in O2 ambiance are shown in Figure 4-17. In the Raman spectrum of SiGeN film in sample I before oxidation, there is a broad distribution signal which means that the as-deposited SiGeN film is amorphous and a signal peak of Ge crystal appears after 30 minutes thermal oxidation. The appearance of the signal peak of crystal Ge represents that the Ge atoms in SiGeN film were segregated and nucleated forming Ge nanocrystal while dry oxidation. The Raman spectra of 30 minutes short term and 60 minutes long term dry oxidation are shown in Fig. 4-18 (a) and (b). In comparison with crystal Si substrate signal peak (~520 cm^-1), the intensity of crystal Ge peak (~300 cm^-1) increase with the extension of dry oxidation time, which reveals that the longer oxidation time makes not only more Ge atoms to be segregated from the thickening

blocking oxide, but also more time for Ge atoms to nucleate. The intensity of crystal Ge after 60 minutes oxidation is even stronger than that of crystal Si substrate.

4.2.2 Oxidize Capped Amorphous Si Layer as Blocking Oxide ( Sample II )

The FTIR spectra of sample II before and after thermal oxidation process are shown in Figure 4-19. The same as sample I, the weak bonds such as Si-H, Ge-H, N-H disappear after 900℃ dry oxidation and the appearance of Si-O after oxidation means the SiGeN layer has been oxidized to form SiOx as blocking oxide. The transmission electron microscope (TEM) diagrams and Auger Electron Spectroscopy (AES) analysis before oxidation and after oxidation with condition A(dry 30 minutes), C(dry 60minutes) are shown in Fig. 4-20 (a), (b), Fig. 4-21 (a), (b), Fig. 4-22 (a), (b), respectively. Also, the TEM diagram as shown in Fig. 4-20 (a), there is no Ge nanocrystal present in the as-deposited SiGeN film before oxidation and Fig. 4-20 (b) shows that all of the three elements, Si, Ge and N are present in the as-deposited SiGeN film before oxidation. In the Raman analysis as shown in Fig. 4-23, there is a Ge crystal peak but in the TEM diagram (Fig. 4-20(a)), there is no Ge nanocrystal present in the oxidized SiGeN film because the oxidation time is not long enough for Ge atoms to be segregated and to nucleate and this phenomenon is also observed by Kan et al. in their study [4.2]. After a longer oxidation period, the Ge nanocrystals appear in the TEM diagram, as shown in Fig. 4-22 (a) and there is a rise of Ge and N signal between 100 and 400 second in Fig.

4-22 (b), which reveals that the Ge nanocrystals are imbedded in SiON dielectric.

The Raman spectra of sample II before and after 30 minutes thermal oxidation process in O2 ambiance are shown in Figure 4-24. In the Raman spectrum of SiGeN

The Raman spectra of sample II before and after 30 minutes thermal oxidation process in O2 ambiance are shown in Figure 4-24. In the Raman spectrum of SiGeN

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