This thesis has been divided into five chapters. Chapter 2 describes the devices used in this work and experimental setup. The channel backscattering experimental flow chart in Fig. 1.1 is used to extract the two parameters. Also the model description will be illustrated in chapter 2.
In Chapter 3, we will report the impacts on device characteristics, as a result of uniaxial and biaxial strain for nMOSFET. Also, we will examine the pMOSFET with various combination of uniaxial and biaxial strained techniques.
In chapter 4, we observe the relationships of those two important parameters with the reliability. In general, the carriers have higher energy which will cause the oxide damage serious. Combining Bsat and Vinj, we can use it to predict how the reliability of the test devices shows.
Finally, a summary and conclusion are given in Chapter 5.
Chapter 2 Device Fabrication and Experimental Measurements
2.1 Introduction
As CMOS devices scale down, new materials or devices structures are required to overcome the scaling barriers and enhance device performance. The SiGe or Ge has been considered to be a potential option due to their high intrinsic mobility. 6-25X hole mobility enhancement over Si have been reported using strained-Ge channels [10] [11] [12] [13]. Moreover, it is well known that hole mobility is more than double at <110> channel direction on (110) surface [14]. In addition, electron shows higher performance on <110>/(100) direction. Hence, the hybrid substrate is a popular technique for high performance logic applications [14]. In Fig. 2.1, the structure of this technique is pMOSFET made on (110) substrate while nMOSFET on (100) substrate.
Therefore, to further enhance the pMOSFET performance for modern VLSI applications, strain technique on (110) substrate will be a compromising choice as shown in Fig 2.2, which is the devices we measured in this work.
As for nMOSFET, uniaxial and biaxial strained devices have been used in this work For uniaxial strained sample is made by silicon nitride capping layer as a stressor to tensile the channel and biaxial strain is generally grown on thick relaxed/graded Si1-xGex buffer virtual substrate. The schematic cross section of the strained-Si nMOSFET used in this chapter is shown in Fig. 2.4
In this chapter, first, we will describe the manufacturing process for strained devices. Then, we will illustrate the experimental setups to characterize the test device, which include the instrumental scheme, various experimental skills, and temperature dependent experiment.
Buried oxide
STI STI
(100) Or (110)Silicon handle wafer
pFET on (100) SOI, nFET on (100) epi-layer nFET on (100) SOI, pFET on (110) epi-layer
Buried oxide
STI STI
(100) Or (110)Silicon handle wafer Buried oxide
STI STI
(100) Or (110)Silicon handle wafer Buried oxide
STI STI
(100) Or (110)Silicon handle wafer
pFET on (100) SOI, nFET on (100) epi-layer nFET on (100) SOI, pFET on (110) epi-layer
Fig. 2.1 The Schematic cross-section of CMOS on a hybrid-substrate with pFET on (110) substrate orientation and nFET on (100) substrate orientation.
Gate
SiGe
SiGe S/D <110>/(100) SiGe
SiGe S/D <110>/(100) SiGe
SiGe S/D <110>/(100) SiGe
SiGe S/D <110>/(100)
SiGe
Poly Si
Gate
n n
Tensile Capping-Layer
Si <110>Cannel Si (100)Substrate
Poly Si
Gate
n n
Tensile Capping-Layer
Si <110>Cannel Si (100)Substrate
Poly Si
Gate
n n
Tensile Capping-Layer
Si <110>Cannel Si (100)Substrate
Poly Si
Gate
n n
Tensile Capping-Layer
Si <110>Cannel Si (100)Substrate
Fig. 2.3 The cross section view of uniaxial strained nMOSFET.
Gate
Source Drain
Si substrate
Strained Si
Relaxed Si 1-x Ge x Graded Si 1-x Ge x buffer
x:0% to 20% Graded Si 1-x Ge x buffer
x:0% to 20% Graded Si 1-x Ge x buffer
x:0% to 20% Graded Si 1-x Ge x buffer
x:0% to 20%
n +
n + n +
n +
Fig. 2.4 The schematic cross section of the biaxial strained-Si nMOSFETs.
2.1 Device Fabrication
The testing devices in this experiment are the best channel/substrate orientations of CMOS. In nMOSFET, <110>/(100) uniaxial tensile strained-Si and biaxial tensile strained-Si channel were fabricated in state-of-art process. On the other hand, for pMOSFET is on <110>/(110) orientation [14].
Table 2.1 shows the summary of the best orientations of n- and p-MOSFET.
2.1.
1 Fabrication of nMOSFET
The biaxial strained nMOSFET devices were fabricated on bulk Si substrate and relaxed SiGe virtual substrate with a tensile strained Si capping layer. The VT shift due to enhanced arsenic diffusion in the SiGe buffer was controlled by a modified halo implant and an optimized dopant anneal process.
A nickel silicide process was adopted to avoid the problem of Ge segregation during silicide formation on SiGe. These test devices were made with the same physical thickness (16Å) of nitrided gate oxide and with different channel lengths. The relaxed Si1-x/Gex is at x=20% and with Si cap layer thickness 100Å. Both technologies used the same processes except for the channel engineering to match the VT
shift.
Uniaxial tensile strain in nMOSFET is using nitrided capping layer which was deposited upon the gate region to introduce tensile strain to the channel. The process flow is the same with the standard nMOSFET, bur the difference is that after gate silicidation we deposit the SiN capping layer on gate.
2.1.2 Fabrication of pMOSFET
For pMOSFET, starting form (110) Si substrate, the 8nm Si0.7Ge0.3 channel with 5nm Si cap were
selectively grown on the active region after isolation and well implant process. The Si cap was used to form high quality nitridated oxide layer. The <110> channel direction was adopted for fabricated devices. After nickel salicidation, 1000A compressive (-2Gpa) or tensile (+1.1Gpa) capping layer was deposited to server as the contact etch stop layer (CESL). That is the process flow of SiGe and SiGe+CESL device.
As for SiGe refill at source and drain region device, also it was fabricated in the state-of-the art process, by inserting a Si recess etch and selective epitaixial Six Ge 1-x(x=0.17) deposition post-spacer formation into a standard logic technology process flow. The mismatch in the Six Ge 1-x to Si lattice causes the p-type MOSFET to be under compressive strain.
2.2 Fundamental Experimental Setup
The experimental setup for the Current-Voltage measurement of n- and p-MOS devices is illustrated in Fig. 2.5. Based on the computer controlled instrument environment, the complicated and long-term characterization procedures for analyzing the intrinsic and degradation behavior in MOSFET can be easily achieved. As shown in Fig. 2.5, the characterization equipments that connected by Co-axial and Tri-axial cable, including the semiconductor parameter analyzer ( HP 4156C ), the low leakage switch mainframe ( HP E5250A ), the cascade guarded thermal probe station, and thermal controller, provide an adequate capability for measuring the low leakage device I-V characteristics.
(100)/<110>
Tab. 2.1 The combination of mobility for hybrid CMOS technology. Group one has the highest mobility and Ion enhancement.
HP 8110A Pulse Generator
Cascade Guarded Thermal
Probe Station Switch Matrix
HP 5250A Parameter Analyzer HP 4156
Probe Station Switch Matrix
HP 5250A Parameter Analyzer HP 4156
Probe Station Switch Matrix
HP 5250A Parameter Analyzer HP 4156
Probe Station Switch Matrix
HP 5250A Parameter Analyzer HP 4156
Probe Station Switch Matrix
HP 5250A Parameter Analyzer HP 4156
Probe Station Switch Matrix
HP 5250A Parameter Analyzer HP 4156
PC Thermal Controller
Fig. 2.5 The experimental setup for the current-voltage measurement of n- and p-MOSFET.
2.3 Charge Pumping Measurement
2.3.1 Basic Experimental Setup
The basic setup of charge pumping measurement is shown in Fig. 2.6. The source, drain and bulk electrodes of tested devices are grounded. A 1MHz (the frequency can be modulated for different devices) square pulse waveform provided by HP8110A with fixed base level (Vgl) is applied to the NMOS gate, or with fixed top level (Vgh) is applied to the PMOS gate. We keep Vgl at –1.0V while increase Vgh from –1.0V to 1.0V by step 0.1V, or keep Vgh at 1.0V while decrease Vgl from 1.0V to –1.0V by step –0.1V. With a smaller voltage step, we get a higher profiling resolution. The parameter analyzer HP4156C is used to measure the charge pumping current (ICP).
2.3.2 Basic Theory
The charging pumping principle for MOSFET has been applied to characterize the fast interface traps in MOSFET. The original charge pumping method was introduced by Brugler and Jespers, and the technique was developed by Heremans [2]. This technique is based on a recombination process at the Si/SiO2 interface involving the surface traps. It consists of applying a constant reverse bias at the source and
Fig. 2.6 The experimental setup and environmental for basic I-V measurement of MOSFET.
drain, while sweeping the base level of the gate pulse train from a low accumulation level to a high inversion level. The frequency and the rise/fall time are kept constant. When the base level is lower than that flat-band voltage while the top level of the pulse is higher than the threshold voltage, the maximum charge pumping current occurs. This means that a net amount of charge is transferred from the source and drain to the substrate via the fast interface traps each time the device is pulsed from inversion toward accumulation. The charge pumping current is caused by the repetitive recombination at interface traps. As a result, the recombination current measured from the bottom (substrate) is the so-called charge pumping current [3]. The CP current can be given by:
ICP = q · f · W · L · NIT. (2.1)
According to this equation, the current is directly proportional to the interface trap density in the channel, the frequency, and the area of the device. However, when the top level of the pulse is lower than the flat-band voltage or the base level is higher than the threshold voltage, the fast interface traps are permanently filled with holes in accumulation or the electrons in inversion in n-MOSFET, which no holes reach the surface at the time, respectively. As a result, there is no recombination current and then the charge pumping current cannot be discovered.
Charge pumping measurements can be performed with several different ways. For our experimental requirement, we perform the charge pumping measurement by applying a gate pulse with the fixed base voltage (Vgl) and increasing the pulse amplitude. While the channel operates between accumulation and inversion as the fixed base voltage lower than flat-band voltage and high voltage above the threshold voltage respectively; this gives rise to the charge pumping current (ICP) from the bulk and reaches saturation situation. If we use another method which changes base voltage with fixed pulse amplitude, the current saturation region is not extensive enough for research because of the limit
that the saturation current happens only when the gate pulse train from a low accumulation level to a high inversion level.
2.3.3 Principle of the Low Leakage IFCP Method
Figures 2.7 (a) and (b) show the schematic of a low leakage IFCP measurement for CMOS developed by our group in [4]. With both S/D grounded and by applying a gate pulse with a fixed base level (Vgl) and a varying high-level voltage (Vgh) for NMOS, the channel will be switched between the accumulation and inversion. This gives rise to the charge pumping current ICP (=IB) measured from the bulk. From Fig. 2.3, when tox >30Å, the leakage current IG of ICP is very small. However, when tox is slow down than 20Å, the leakage current IG is unavoidable. The unexpected leakage current will influence our research. From the measured ICP at two frequencies, ƒ1 and ƒ 2, can be expressed as
ICP,ƒ 1 with-leakage= ICP,ƒ 1 correct + ICP,leakage@ƒ1 (2.1) and
ICP,ƒ 2 with-leakage= ICP,ƒ 2 correct + ICP,leakage@ƒ2. (2.2)
When the frequency is sufficiently high, the leakage components in these two frequencies are almost the same (ICP,leakage@ƒ1 ≈ ICP,leakage@ƒ2 ). We then take the difference of ICP (∆ICP,ƒ 1-ƒ 2) between two frequencies. From equations (2.1) and (2.2), the difference of these two CP curves gives
∆ICP,ƒ 1-ƒ 2 = ICP,ƒ 1 with-leakage － ICP,ƒ 2 with-leakage. (2.3)
Fig. 2.7 The schematic diagram of charge pumping for (a) nMOSFET measurement
(b) pMOSFET measurement ,
Induced leakage current (IG) occurs when tox<20A
Since the correct CP curve is directly proportional to the frequency, it will be equal to the difference of two CP curves. Therefore, in the IFCP method, the correct CP curve at frequency (ƒ1- ƒ2) can be given by
IC P, ƒ 1 - ƒ 2 = ∆IC P, ƒ 1 - ƒ 2. (2.4)
For example, ICP(2MHz) － ICP(1MHz) is regarded as the ICP at their difference frequency, 1MHz. The result of the charge pumping measurement for the strained-Si device is shown in Fig. 2.4 curve (1) and curves (2). From this figure, we can find a huge gate leakage current appears in the charge pumping cure when the voltage of gate pulse is higher than 1V. Because the correct charge pumping current is directly proportional to the frequency of gate pulse and the leakage of current is irrelevant to the frequency, so we can receive the correct charge pumping current by taking the difference of the measured ICP between two frequencies theoretically. To see the result, we finally get a correct curve with commonly known saturation charge pumping current, curve (3), in Fig. 2.4.
-1.0 -0.5 0.0 0.5 1.0
Charge Pumping Current, I CP (pA)
Gate Voltage,V gh (V)
NMOS
Charge Pumping Current, I CP (pA)
Gate Voltage,V gh (V)
NMOS
Charge Pumping Current, I CP (pA)
Gate Voltage,V gh (V)
NMOS
Charge Pumping Current, I CP (pA)
Gate Voltage,V gh (V)
NMOS
Fig. 2.8 Measurment of Icp at two different frequencies. The two leakage IFCP method is achieved by subtracting their respective Icp’s at two successive frequencies
2.4 Model Description and Derivation
2.4.1 Essential Physics of Channel Backscattering
Fig. 2.9 is the schematic diagram of channel backscattering theory in saturation region. Carriers are injected from the thermal source side, across the potential barrier whose height is modulate by the gate voltage and the drain voltage called KbT-layer, into the channel which is populated by carriers injection from thermal equilibrium source. Because of the high electrical field and velocity overshoot near the drain side, carriers transport rapidly through the channel into the drain.
Therefore the device current is controlled by the low field region near the beginning of the channel instead of the drain side. Where l is the length of potential barrier. According to [elementary 0 scattering theory of Si MOSFET], real device operate below ballistic limit because of carrier back-scattering, which leads to:
Where
Fig 2.10 shows the experimental flow chart of this thesis. All of these symbols have their physical meanings: V is the thermal velocity from the source side, inj r is the backscattering coefficient and c B is the ballistic efficiency. The symbol sat Ceff •(Vg V− T sat, ) equals to the inversion charge density which is usually assumed to be proportional to the amount of the gate voltage overdrive between the gate voltage and threshold voltage. In state-of-the-art manufacturing process, the length of potential barrier is comparable to one mean-free-path, which means the transport across this layer is
, ( , )
D sat inj eff sat G T sat
I =W V• •C •B • V −V sat 11 c
c
B r
r
= − +
quasi-ballistic. Note that the above deviations ignore some effect such as quantum confinement and carrier degeneracy.
Gate
r c 1 − r c
l 0
k T B
V inj 1
Gate
r c 1 − r c
l 0
k T B
V inj 11
Gate
r c 1 − r c
l 0
k T B
V inj 1
Gate
r c 1 − r c
l 0
k T B
V inj 11
Fig. 2.9 The schematic diagram of channel backscattering in the saturation region of a device.
0
Fig. 2.10 The experimental flow chart of this thesis.
2.4.2 Principle of the Measurement
First of all, as shown in Fig 2.6 we use temperature dependent method to achieve the experiment, which the temperature is ranged from 25 C to 0 75 C . Determining the threshold in short channel is 0 difficult because of potential uncertainties caused by short channel effect i.e., DIBL (Drain Induced Barrier Lowering). In order to minimize this effect, we need to diminish the extra threshold drop.
Device operates at saturation region where the threshold voltage is not exactly defined by Gm method.
It’s only precisely when drain voltage is very small about 25mv. Thus threshold voltage at saturation region VT,sat equals the threshold voltage at linear region VT,lin minus the DIBL effect:
, , ( @ 2 5
T s a t T l i n V D m v
V = V = − D I B L . Fig. 2.8 is the DIBL effect of the test device. We can see that at high drain voltage, threshold is easily attained [15].So it is necessary to consider. Because of drain voltage and threshold voltage is temperature dependent; there will be some deviation at different temperature. Then, a temperature-dependent analytic is employed to extract the
0 0
λ ι ration by using following analytic expression:
,
So can be derived as follows:
α and ηis the important parameter above this experimental. We can estimate that , 1 , 2
1 2 2
Δ and ΔVT sat, . Lastly, backscattering coefficientr , ballistic efficiencyc B and injection velocity sat
V can be deduced. Notice that the capacitance we measured is long channel, big area device. inj
However the devices we tested are short channel devices, the inversion charge will be underestimated. So we need to correct this mismatch. In [16], we can use the difference of the threshold voltage of long and short channel devices to compensate the inversion charge. Thus the backscattering coefficient r is easily extracted by this temperature dependent method. c
2.5 Summary
In this chapter, we present a simple theory of the MOSFET to explore the physics of the Nano-scaled devices. It emphasizes on the critical importance of the source to channel transition region in these small devices and the need to realize the efficient carrier injectors at the source. The experimental setup and analytical method are described simply. We will use these experimental techniques to discuss control Si and Strained-Si samples transport issues.
Fig. 2.11 The DIBL effect at different drain voltages. We can see that threshold voltage can be easily attained due to DIBL effect.
Chapter 3 Performance and Backscattering Transport of CMOS with
Various Strain techniques
3.1 Introduction
With the scaling of the device size, performance improvement of CMOS devices faces a number of obstacles. Mobility enhancement technology is the way to offer dramatic advances of CMOS devices. In order to realize high-speed scaled CMOS devices, it is necessary to increase the carrier mobility for device gate length down to the sub-100-nm and beyond. Recently, a number of groups have shown that short channel nMOSFET devices incorporating thin strained-Si surface channels can achieve significant drive current enhancement.
In the past four decades, geometric scaling of silicon (Si) complementary metal-oxide semiconductor (CMOS) transistors has enabled not only an exponential increase in circuit integration density (Moore’s law), but also a corresponding enhancement in the transistor performance itself.
Simple metal-oxide semiconductor field effect transistor (MOSFET) geometric scaling has driven the industry to date. But as the transistor gate length drops to 35nm [17]–[19] and the gate oxide thickness drops to 1 nm, physical limitations, such as off-state leakage current and power density, make geometric scaling an increasingly challenging task. To continue CMOS device historical performance improvement, the industry needs a new scaling vector. Starting with the 90-nm technology generation, mobility enhancement through uniaxial process-induced strained Si has emerged as the next possible scaling.
Electron/hole mobility enhanced by uniaxial stress and biaxial stress in tensile/ compressive strain is efficiency. In nMOSFET uniaxial strain, we can use SiN (Thermal CVD) as a contact etch stop
layer (CESL) to tensile the channel. For biaxial strain in nMOSFET, Si on relaxed SiGe virtual substrate is the popular technique. On the other hand, there are two approaches to achieve uniaxial strain in pMOSFET, one is to deposit SiN (PE CVD) on the gate, and the other way is to refill S/D with SiGe, which will cause compressive strain to the channel. The biaxial compressive strain utilizes SiGe on Si substrate. In this chapter, the devices performance and backscattering characteristic of strained-Si MOSFET will be demonstrated.
3.2 The Backscattering Characteristics of Uniaxial and Biaxial Strained-nMOSFET
3.2.1 Device Performance of Uniaxial nMOSFET
Fig. 3.1 shows the Ion/Ioff characteristic of uniaxial strain nMOSFET, which is enhanced about 34% than control sample. Piezoresistance coefficients can be as a guide as to which strain maximizes the mobility enhancement in uniaxial stress. Since uniaxial process-induced strain is generally parallel (longitudinal) or perpendicular to the direction of the MOSFET current flow. The effect of mechanical stress on the mobility can then be expressed as follows: μ π σ π σ
μ ⊥ ⊥
Δ ≈ + where and ⊥refers to
the directions parallel and traverse to the current flow in the plane of the MOSFET, μ μ
Δ is the
fraction change in mobility.σ andσ⊥ are the longitudinal and transverse stresses, and π and π⊥ are the piezoresisitance coefficient express in Pa-1. The longitudinal and transverse piezoresisitance coefficients for the standard layouts are given in Table 3.1. From the table that nMOSFET uniaxial strain on <100> channel direction is efficiency for it has higher π [20], which results on the high strain reduced to high performance.
500 1000 1500 1E-8
1E-7 1E-6
I off (A/um)
Ion(uA/um)
+34%
Uniaxial w/
Tensile-capping layer
Control Si
NMOS FET
500 1000 1500
1E-8 1E-7 1E-6
I off (A/um)
Ion(uA/um)
+34%
Uniaxial w/
Tensile-capping layer
Control Si
NMOS FET
Fig. 3.1 The Ion/Ioff characteristic of uniaxial strain nMOSFET, enhanced about 34% than the control sample.
-66.3 71.8
-1.1 6.6
P-type
-17.6 -31.6
53.4 -102
N-type N or P polarity
<110>
<100>
-66.3 71.8
-1.1 6.6
P-type
-17.6 -31.6
53.4 -102
N-type N or P polarity
<110>
<100>
π π ⊥ π
π
⊥π
π
12( π π π
11+ +
12 44)/2 ( π π π
11+ +
12 44)/2
Tab. 3.1 The longitudinal and transverse piezoresistance coefficient evaluated for standard layout and wafer orientation
3.2.2 Backscattering Characteristic of Uniaxial nMOSFET
Fig. 3.2 shows the λo/lo versus channel lengths, which was extracted form the measured temperature dependent parameters. Fig. 3.3 shows the rc versus channel lengths, is calculated from the
, , and
α η VT as defined in fig. 2.6. Based on extracted o lo
λ ratio, ballistic efficiency Bsat under saturation operation are calculated and plotted in Fig. 3.4.
As gate length shrinks, the departure of rc between control and uniaxial strained-MOSFET becomes more evident. Uniaxial strained-nMOSFET exhibits a smaller rc while control sample exhibits a larger rc. This observation indicates that carriers are injected from source into the channel, the injected electrons suffered less backscattering under uniaxial tensile strain. After extracting the backscattering coefficient, the other parameter: injection velocity also needs to be extracted. In Fig. 3.5 shows the Vinj versus channel lengths: Uniaxial strained sample has higher velocity about 2 times than control sample. From the above results, uniaxial strained nMOSFET has higher transport mechanism than control sample.
3.2.3 Device Performance of Biaxial Strained-nMOSFET
Fig.3.6 shows the Ion/Ioff characteristic of biaxial strained-nMOSFET, which is enhanced about
Fig.3.6 shows the Ion/Ioff characteristic of biaxial strained-nMOSFET, which is enhanced about