Chapter 4 The Relationships Between Reliability and Current Enhancement
4.3 The Reliability of Strained Device Relates to Channel Backscattering Parameters
In the following, we compared the substrate current after impact ionization effect of both devices.
When carrier has great transverse electric field, it will be accelerated and possesses huge energy to collision the lattice to generate the electron-hole pairs. When gate is applied to positive voltage, the
electron will transport to the bulk for coulomb repulsion, and holes will be attracted to the gate oxide to hit the Si/SiO2 interface. So we can measure bulk current to detect how sever the damage is.
Fig. 4.6 exhibits impact ionization current of the strained-Si device of nMOSFET which is operated at Vd= 2V and sweep Vg. It puts the four devices to compare the impact ionization current. In the figure we can see that biaxial strain has higher value than uniaxial strain. Hence, biaxial strained device is severed more degradation than using capping layer uniaxial strained device. In Fig. 4.7 (a) is measured charge pumping current of biaxial strained-nMOSFET, (b) is the measured charge pumping current of uniaxial strained-nMOSFET. In which we can see that strained device exhibits the larger value than control. This implies that strained devices of nMOSFET show larger interface traps. After hot carrier stress under Vg=Vd=2V, we extract the delta charge pumping current of the strained-nMOSFET is shown in the Fig 4.8
In Fig. 4.9 is the impact ionization current of the strained-Si device of pMOSFET which is operated at Vd= -2V and sweep Vg. As shown in the figure, SiGe + CESL has largest bulk current while control device shows the lowest. Then the second rank is the SiGe channel, third is SiGe S/D. In [23] exhibits that SiGe S/D uniaxial compressive strain has better reliability than SiGe channel biaxial compressive strain. So when consider the effect of the plus with uniaxial and biaxial strain, the result shows the worse reliability. The larger bulk current means that the gate is suffering serious damage. In Fig. 4.10 is measured charge pumping current of strained-pMOSFET, also the strained-devices show worse interface quality. Then the measured charge pumping current after the hot carrier stress to the pMOSFET is shown in the Fig. 4.11. Whatever for nMOSFET or pMOSFET, it shows the same result with the impact ionization rate, larger bulk current cause server interface traps.
15 20 25 30 35 0
40 80
Uniaxial Tensile-cap compared to Control Si
NMOSFET
Bsat Enhancement % Vinj Enhancement %
Enhancement %
I D Enhancement, Δ I D /I
D (%)
15 20 25 30 35
0 40 80
Uniaxial Tensile-cap compared to Control Si
NMOSFET
Bsat Enhancement % Vinj Enhancement %
Enhancement %
I D Enhancement, Δ I D /I
D (%)
Fig. 4.1 The current enhancement relates to channel backscattering parameters of uniaxial
strained-nMOSFET. Both Bsat and Vinj are enhanced while Vinj is enhanced about 50%
than the control sample.
4 6 8 10 12 14 20
30 40 50 60
NMOSFET
Biaxial Strained-Si/SiGe compared to Control Si
Enhancement %
I D Enhancement, Δ I D /I
D (%)
B
satenhancement % V inj enhancement %
4 6 8 10 12 14
20 30 40 50 60
NMOSFET
Biaxial Strained-Si/SiGe compared to Control Si
Enhancement %
I D Enhancement, Δ I D /I
D (%)
B
satenhancement % V inj enhancement %
Fig. 4.2 The current enhancement relates to channel backscattering parameters of Biaxial
strained-nMOSFET. Both Bsat and Vinj are enhanced, and Vinj is enhanced much larger than Bsat.
16 20 24 28 -20
0 20 40 60
Vi nj Enhancement (%)
Drain current Enhancement (%)
Vinj Enhancement Bsat Enhancement
SiGe S/D compared to (110)<110>
pMOSFET -20
0 20 40 60
Bsat Enhancement (%)
16 20 24 28
-20 0 20 40 60
Vi nj Enhancement (%)
Drain current Enhancement (%)
Vinj Enhancement Bsat Enhancement
SiGe S/D compared to (110)<110>
pMOSFET -20
0 20 40 60
Bsat Enhancement (%)
Fig. 4 .3 The current enhancement relates to channel backscattering parameters of uniaxial strained-pMOSFET. Bsat is degraded, while Vinj is enhanced.
0 5 10 15 20 25 -20
0 20 40 60
PMOSFET
SiGe Comprared to control Si Bsat enhancenent Vinj enhancement
Enhancement %
I D Enhancement, Δ I D /I
D (%)
0 5 10 15 20 25
-20 0 20 40 60
PMOSFET
SiGe Comprared to control Si Bsat enhancenent Vinj enhancement
Enhancement %
I D Enhancement, Δ I D /I
D (%)
Fig. 4 .4 The current enhancement relates to channel backscattering parameters of biaxial
strained-pMOSFET. Both parameters are enhanced. Vinj is enhanced about 40% and Bsat is enhanced about 9.8% in average.
20 25 30 -10
0 10 20 30 40 50
PMOSFET
SiGe+CESL Comprared to control Si Bsat enhancenent
Vinj enhancement
Enhancement %
I D Enhancement, Δ I D /I
D (%)
Vinj dominates Enhancement
20 25 30
-10 0 10 20 30 40 50
PMOSFET
SiGe+CESL Comprared to control Si Bsat enhancenent
Vinj enhancement
Enhancement %
I D Enhancement, Δ I D /I
D (%)
Vinj dominates Enhancement
Fig. 4.5 The current enhancement relates to channel backscattering parameters of biaxial plus uniaxial (SiGe+CESL) strained-pMOSFET. Both Vinj and Bsat are enhanced.
0.5 1.0 1.5 2.0 0 2 4 6 8
I B /I D x10 -3
Si/SiGe Biaxial Strain Control Si (100)/<110>
Capping Layer
Control Si (100)/<100>
Gate Voltage, V G (V)
Substr at e Cur rent , I
B(A)
NMOS
10
-910
-710
-510
-30.5 1.0 1.5 2.0 0
2 4 6 8
I B /I D x10 -3
Si/SiGe Biaxial Strain Control Si (100)/<110>
Capping Layer
Control Si (100)/<100>
Gate Voltage, V G (V)
Substr at e Cur rent , I
B(A)
NMOS
10
-910
-710
-510
-3Fig. 4.6 The measured impact ionization current of the strained-Si device of pMOSFET. Biaxial strain has largest value while control<100>/(100) is the lowest.
-1.0 -0.5 0.0 0.5
Biaxial Strained
Charge Pumping Current, I cp/L eff (nA/um)
Gate Voltage, V
NMOS Tox=14Å (100)/<110>
Charge Pumping Current, I cp/L eff (uA/um)
Gate Voltage, V
Biaxial Strained
Charge Pumping Current, I cp/L eff (nA/um)
Gate Voltage, V
NMOS Tox=14Å (100)/<110>
Charge Pumping Current, I cp/L eff (uA/um)
Gate Voltage, V
gh
(V) (a)
(b)
Fig. 4.7 The comparison of charge pumping currents in nMOSFET devices, including (a) bulk-Si and biaxial strained-Si/SiGe devices and (b) bulk-Si device and bulk-Si channel with tensile-cap layer.
-1.0 -0.5 0.0 0.5 1.0 0
40 80 120
NMOSFET Tox= 14A (100)/<110>
W /Leff=10/0.06μm
Stress@VG=VD= 2V, 300s
Gate Voltage, V
gh(V)
CP Cu rre nt , Δ I
CP(uA/um)
Uniaxial StrainedBulk-Si
NMOSFET Tox= 16A (100)/<100>
W /Leff=10/0.07μm
Stress@VG=VD= 2V, 300s
Gate Voltage, V
gh( V )
CP Cur ren t, Δ I
CP(uA/um)
Biaxial Strained
NMOSFET Tox= 14A (100)/<110>
W /Leff=10/0.06μm
Stress@VG=VD= 2V, 300s
Gate Voltage, V
gh(V)
CP Cu rre nt , Δ I
CP(uA/um)
Uniaxial StrainedBulk-Si
NMOSFET Tox= 16A (100)/<100>
W /Leff=10/0.07μm
Stress@VG=VD= 2V, 300s
Gate Voltage, V
gh( V )
CP Cur ren t, Δ I
CP(uA/um)
Biaxial Strained
NMOSFET Tox= 16A (100)/<100>
W /Leff=10/0.07μm
Stress@VG=VD= 2V, 300s
Gate Voltage, V
gh( V )
CP Cur ren t, Δ I
CP(uA/um)
Biaxial Strained
Fig. 4.8 The comparison of charge pumping currents in nMOSFET devices after HC stress at 300s including (a) bulk-Si and biaxial strained-Si/SiGe devices and (b) bulk-Si device and bulk-Si channel with tensile-cap layer.
-1.6 -1.2 -0.8 -0.4 0.0
Su bstra te Cu rre nt, IB (A)
10
-510
-410
-310
-2Impact Io niza tion (IB/ID)
-1.6 -1.2 -0.8 -0.4 0.0
Su bstra te Cu rre nt, IB (A)
10
-510
-410
-310
-2Impact Io niza tion (IB/ID)
Fig. 4.9 The measured impact ionization current of the strained-Si device of pMOSFET, in which SiGe+CSEL has the largest impact ionization rate, next is SiGe channel. The lowest is the control sample.
-1.0 -0.5 0.0 0.5 1.0 0
2 4 6 8
SiGe-ch <110>/(110) SiGe S/D <110>/(100) SiGe+CESL<110>/(110) Control Si <110>/(110)
Charge pumping cur rent , I
cp(nA )
Gate Voltage,Vgl (V)
pMOSFET W=10 um, L=0.07um
-1.0 -0.5 0.0 0.5 1.0
0 2 4 6 8
SiGe-ch <110>/(110) SiGe S/D <110>/(100) SiGe+CESL<110>/(110) Control Si <110>/(110)
Charge pumping cur rent , I
cp(nA )
Gate Voltage,Vgl (V)
pMOSFET W=10 um, L=0.07um
Fig. 4.10 The comparison of charge pumping currents in pMOSFET devices, in which control shows lowest value while SiGe+CESL is the largest.
-0.8 -0.4 0.0 0.4 0.8 1.2 0
2 4 6 8 10
SiGe-ch <110>/(110) SiGe S/D <110>/(100) SiGe+CESL <110>/(110) Control Si <110>/(110)
D elta charge pumping current,
ΔI
cp(uA/um )
Gate Voltage,Vgl (V)
pMOSFET
W=10um ,L=0.07 um Stress @ Vg=Vd=-2V
-0.8 -0.4 0.0 0.4 0.8 1.2
0 2 4 6 8 10
SiGe-ch <110>/(110) SiGe S/D <110>/(100) SiGe+CESL <110>/(110) Control Si <110>/(110)
D elta charge pumping current,
ΔI
cp(uA/um )
Gate Voltage,Vgl (V)
pMOSFET
W=10um ,L=0.07 um Stress @ Vg=Vd=-2V
Fig. 4.11 The comparison of charge pumping currents in pMOSFET devices after HC stress at 300s.
The severe degradation is shown in SiGe+CESL device.]
4.4 Summary
In this chapter exhibits the relationships with reliability and current enhancement of CMOS. Form the backscattering theory, Vinj and Bsat are the two important factors to determine the drive current.
Also in the experimental above, we can conclude that injection velocity is the most important parameter to cause the device performance enhance. In every device we measured, we find that ΔVinj is always occupied a huge portion to influence the performance.
The reliability of strained-devices is inevitable an important issue of the practice application. And we can use this simple theory to predict the essential effect of reliability (impact ionization rate). The lower barrier is the more carriers will transport to the drain region, and the larger the injection velocity is the higher the energy the carriers have. Fig. 4.12 illustrates the mechanism, in which the carriers possess higher Vinj and pass through the lower barrier will have more probability to collide the lattice and hence to produce electron-hole pairs.
Table 4.1 is the summary of this thesis, including the average ofΔVinj,ΔBsat and the superposition of these two parameters. The value of superposition of ΔVinjand ΔBsatis proportional to the impaction ionization rate. Hence form the table 4.1, we can see that in nMOSFET biaxial tensile strain will has the reliability issue than uniaxial strainecd-nMOSFET for for its value of ΔVinj+ΔBsat. In pMOSFET, uniaxial strain strained-pMOSFET with SiGe S/D exhibits lowest value of ΔVinj+ΔBsat, hence it will has better reliability than the other strain technique. Although twice-strain technology is applied to the channel to promote the performance to 56% than control (100) device, but also due to the effect to cause the interface face un-uniform. The SiGe+CESL device shows the worst reliability of the testing device. From the result above, we can back to the Fig. 4.5: the rank of impact ionization rate, which demonstrates the same rank of the n-pMOSFET. The value of superposition of ΔVinjand ΔBsat is a
I
BCurrent
H
+e
-High V
InjA lower barrier or high V
inj, more
carriers will be injected into the channel.
H
+e
-e
--h
+pair
Low V
InjI
BCurrent
H
+e
-High V
InjA lower barrier or high V
inj, more
carriers will be injected into the channel.
H
+e
-e
--h
+pair
Low V
InjFig. 4.12 The schematic diagram of bulk current which is related to the barrier and injection velocity of the carriers. Carriers which exhibit higher Vinj and a lower barrier will have more
probability to collide with the lattice and hence produce electron-hole pairs
+ 29%
compared to control Si
+ 3.6%
compared to control Si
+ 3.6%
compared to control Si
+ 3.6%
compared to control Si
+ 3.6%
compared to control Si
+ 3.6%
compared to control Si
+ 3.6%
Tab. 4.1 The summary of this thesis, including the average of, and the superposition effect of the two parameters. For nMOSFET, uniaxial shows better reliability than biaxial strain. For pMOSFET, SiGe S/D device demonstrates the best reliability among the strained sample.
Chapter 5 Summary and Conclusion
In order to realize high-speed scaled CMOS devices for logic applications, short channel CMOS devices incorporating thin strained-Si surface channels, which can enhance mobility, have evolved as a potential candidate for high speed and low power logic CMOS technologies.
First we show the backscattering characteristics of n-pMOSFET, in the transport point of view we exam the device performance. For nMOSFET is better made by uniaxial strain using tensile capping layer. Since its high performance and better transport behavior, it is better made pMOSFET by SiGe+CESL technique than uniaxial strain. In Fig. 5.1 shows the ballistic efficiency as a function of channel lengths. In ballistic limited, it should equal to 1. There are three dash lines in the Fig. 5.1, blue line is the projection line of the measurement of Dr. Lin [22] [25], red dash line is the projection line of the measurement of other bulk Si devices [26]. And in brown dash line is the projection line of this work. Comparing with three lines, we can see that brown line has better transport behavior in longer length to achieve ballistic limited. In Fig. 5.2 is shown the injection velocity versus channel lengths, the value also extracted from the group’s research. To achieve thermal velocity limited, there are still lots of work to be studied.
In real devices, which are usually operated below ballistic and thermal velocity limit, there are constraints for their performance. So, to increase the device Vinj and Bsat characteristic is one way to enhance the performance. Especially Vinj is the dominant factor to determine the drain current, and it still has a huge gap to achieve thermal limit. We can start from here to enhance the device performance.
Also this theory is suitable to predict the device reliability, by detecting the height of the barrier and the injection velocity of the carriers.
In summary, comprehensive studies on the uniaxial and biaxial effects on the current enhancement have been provided for the first time. Two major design criteria for strained nMOSFET and pMOSFET technology for extreme high current enhancement have been provided. For nMOSFET, on <110>/(100), the uniaxial strain is more efficiency by comparing to the biaxial strain. For pMOSFET, a specific strain technique with the combination of SiGe-channel plus CESL on <110>/(110) provides an extremely high current gain. This observation has been the first reported to date. Moreover, a roadmap has also been established for both injection velocity and ballistic efficiency.
10 100 1000 0.4
0.6 0.8 1.0
This work for PMOS [SiGe-ch ]
This work for NMOS
[Uniaxial Tensile Strained-Si]
This work for NMOS
[Biaxial Tensile Strained-Si]
MIT Tech B[EDL 01]
B
satChannel Length, L G (nm)
Chen [IEDM 02] IBM [IEDM 98]
MIT Tech A [IEEE EDL 01]
Bel Lab [IEDM 99] This work for PMOS [SiGe-ch +CESL ]
Lin [IEDM 06;CESL PMOS]
Lin [EDL 05SiGe S/D; PMOS]
Ballistic Region (B
This work for PMOS [SiGe-ch ]
This work for NMOS
[Uniaxial Tensile Strained-Si]
This work for NMOS
[Biaxial Tensile Strained-Si]
MIT Tech B[EDL 01]
B
satChannel Length, L G (nm)
Chen [IEDM 02] IBM [IEDM 98]
MIT Tech A [IEEE EDL 01]
Bel Lab [IEDM 99] This work for PMOS [SiGe-ch +CESL ]
Lin [IEDM 06;CESL PMOS]
Lin [EDL 05SiGe S/D; PMOS]
Ballistic Region (B
This work for PMOS [SiGe-ch ]
This work for NMOS
[Uniaxial Tensile Strained-Si]
This work for NMOS
[Biaxial Tensile Strained-Si]
MIT Tech B[EDL 01]
B
satChannel Length, L G (nm)
Chen [IEDM 02] IBM [IEDM 98]
MIT Tech A [IEEE EDL 01]
Bel Lab [IEDM 99] This work for PMOS [SiGe-ch +CESL ]
Lin [IEDM 06;CESL PMOS]
Lin [EDL 05SiGe S/D; PMOS]
Ballistic Region (B
sat
=1)
Fig. 5.1 The ballistic efficiency roadmap. There are three dashed lines in the Fig. 5.1, blue line is the projection line of the measurement of Dr. Lin [22] [25], red dash line is the projection line of the measurement of other bulk Si devices [26]. And, brown dash line is the projection line of this work
75 90 105 120
Channel Length, L G (nm)
Large room to improve
V
injThermal limited (1.2~2x10
7cm/s)
75 90 105 120
Channel Length, L G (nm)
Large room to improve
V
injThermal limited (1.2~2x10
7cm/s)
75 90 105 120
Channel Length, L G (nm)
Large room to improve
V
injThermal limited (1.2~2x10
7cm/s)
Fig. 5.2 The roadmap of reported injection velocity versus channel lengths. To achieve thermal velocity limit, lots of work still need to be studied.
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