In this thesis, we investigated the molybdenum-based nanocrystal memory to overcome the limitation of conventional floating gate memory. Furthermore, we introduce nanocrystal into resistance switching memory RAM (RRAM) to enhance the memory characteristics.
Chapter 1 introduces the function and characteristic of NOR and NAND flash memory. Furthermore, discrete charge storage type memories including SONOS-type and nanocrystal-type are organized and discussed. The evolvement of the
12
SONOS-type memory and the research of current status on the nanocrystal memory are reviewed.
In chapter 2, we briefly describe the programming/erase operations of the majority of Flash memories described in the literature. Some important mechanisms such as Programming/Erasing mechanisms, basic Physical characteristic, and reliability of nonvolatile memory and Gibbs free energy are reviewed. The programming/Erasing can be performed by different tunneling mechanism.
In chapter 3, we investigate the nonvolatile memory characteristics of Mo silicide nanocrystal memory through annealed electron-gun evaporated Mo silicide layer in different ambience. Mo nanocrystal can be formed after annealed in N2
ambience. However, the retention of the Mo nanocrystal is not ideal. The retention can be improved by introduce oxygen during annealing process due to reduce the Si dangling bonds in surrounding dielectric.
In chapter 4, Mo nanocrystal embedded in silicon oxide (SiOx) and nitride (SiNx) as charge storage layer is studied. Mo nanocrystal can form in the SiOx after annealing oxygen-incorporated Mo silicide layer at a critical temperature without degrading the tunnel oxide. It is found that the memory window and retention are influenced by various annealing temperature. Furthermore, the density of nanocrystal can be increased by annealing nitrogen-incorporated Mo silicide layer. The Mo nanaocrystal in SiNx have larger memory window than Mo nanocrystal in SiOx
because the high density of nanocrystal and high permittivity of nitride can enhance the coupling to the conduction channel.
In chapter 5, we investigate the ammonia plasma treatment influence on Mo nanocrystal memory. It is found that the treatment can improve the quality of surrounding dielectric by nitrogen passivation. After the passivation, the memory characteristic of Mo nanocrystal in dielectric can be improved. In addition, we
13
compare the memory characteristics between Mo in SiOx and Mo in SiNx as charge storage layer. The different characteristics are explained through charging effect.
Resistance switching memory emerges as a new candidate for future nonvolatile memory. The resistance switching memory has a capacitor-like structure composed of insulating or semiconducting materials sandwiched between two metal electrodes.
Because of its simple structure, highly scalable cross-point and multilevel stacking memory structures have been proposed. In chapter 6, the reproducible and stable resistance switching phenomenon in Al2O3 is demonstrated. The Ni silicide nanocrystal is introduced into Al2O3 to enhance the memory characteristics.
14
Figure 1-1 Structure of the conventional floating-gate nonvolatile memory device.
Electronically continuous poly-silicon floating gate is employed as the charge storage media.
Figure 1-2 Tunnel oxide and operation voltage scaling predicted by the 2007 International Technology Roadmap for Semiconductors.
15
Figure 1-3 Development of the gate stack of SONOS EEPROM memory devices. The optimization of nitride and oxide films has been the main focus in recent years.
Figure 1-4 structure of the nanocrystal nonvolatile memory device. The nanocrystals are used as the charge storage element instead of the continuous poly-Si floating gate.
16
Figure 1-5 The band diagram for the (a) Ge, (b) HfO2, (c) Mo nanocrystals. Sub.:
substrate, Tox.: tunnel oxide, Box.: blocking oxide.
Figure 1-6 (a) self-aligned doubly stacked Si nanocrystals device and (b) energy band diagram of the structure
17
Figure 1-7 (a) Schematic diagram of the p-channel memory device using Ge–Si as floating gates. (b) Energy-band structure of the memory.
18
Chapter 2
Basic Principles of Nonvolatile Memory
2.1 Programming/Erasing mechanisms of nonvolatile memory
Charge storage based nonvolatile memories (NVMs), such as nanocrystal memory and polycrystalline silicon/silicon oxide/nitride/silicon oxide/silicon substrate (SONOS) structure memory, are based on the conceptual of floating gate device.
Using various programming mechanism, after charging, the total stored charge Q is equal to integrated injection current. This results in a shift of the threshold voltage by the amount
where Q is the total charge stored in the floating gate, and C is the capacitances FG between the floating-gate (FG) and control gate [2.1-2.3].
Two methods are used to measure the threshold-voltage shift: (1) change in the channel conductance gD of the MOSFET which is measured at small drain voltages.
The channel conductance of an n-channel MOSFET is given by ),
and (2) ID-VG plot as shown in Fig. 2-1. After the programming, the floating-gate of the memory are charged with a number of negative charges and results in threshold-voltage shift to a higher level (Curve B), which is defined as a state of “1”
in binary. On the other hand, the stored charge can be removed after erasing and the threshold-voltage changes from the higher value to a lower one, which is defined as a state of “0” (curve A).
19
There are many mechanisms can be used to programming and erasing the memory cell. In general, the mechanisms can be divided into two categorizes, hot carrier injection and tunnel effect including direct tunneling, Fowler-Nordheim tunneling and band to band tunneling. These mechanisms for programming/erasing of memory cell can result in difference characteristics and we will briefly introduce them at the following.
Models for programming/erasing
2.1.1 Tunneling effectTunneling mechanisms is a quantum mechanical phenomenon. Unlike to classical mechanics, an electron can be represented by its wave function. The function does not terminate on the side wall of a finite potential barrier but can penetrate into the barrier as shown in Fig. 2-2. The tunneling probability can be calculated from the Schrodinger equation. For complicated barrier shapes, simplification of the equation is made by the WKB (Wentzel-Kramers-Brillouin) approximation if the potential U(x) is a slow function of x. The tunneling probability can then be calculated by
} With tunnel probability eqn. (2-3), the tunneling current Jt can be calculated from the production of the number of available carriers in the Region-A, and the number of empty states in the region-B,
∫
− the subscript represents the corresponding regions.For the different profile of potential barrier, the tunneling effect can be classified
20
into four different tunneling mechanisms, direct tunneling (DT), Fowler-Nordheim tunneling (FN), modified Fowler-Nordheim tunneling (MFN) and trap assistant tunneling (TAT). These mechanisms are the main carrier transport mechanisms employed in the floating gate NVM. Fig. 2-3 shows these four tunnel effects.
A. Direct Tunneling effect (DT)
For nanocrystal memories, the control-gate coupling ratio of nanocrystal memory devices is inherently small [2.4]. As a result, FN tunneling cannot serve as an efficient write/erase mechanism when a relatively thin tunnel oxide is used because the strong electric field cannot be confined in one oxide layer. When the thickness of tunnel oxide is below 5 nm, the direct tunneling is employed in nanocrystal memories instead. Furthermore, the direct tunneling is more sensitive to the barrier width than barrier height. However, two to four orders of magnitude reduction in leakage current can still be achieved if the metals with a large work function, such as Au or Pt, which corresponding to high barrier height , [2.5].
B. Fowler–Nordheim Tunneling effect (FN)
One of most important injection mechanism employed in floating gate devices is the Fowler—Nordheim tunneling, which is a field—assisted electron tunneling mechanism. Electrons in the silicon conduction band see a triangular energy barrier with a width dependent on the applied field. The height of the potential barrier is determined by the electrode material and band structure of SiO2. At sufficiently high field, the energy band diagram of the SiO2 is very steep and thin enough to allow that the electrons can tunnel into the conduction band of SiO2. Using a free-electron gas model for the metal and the WKB approximation for the tunneling probability [2.6], one obtains the following expression for current density [2.7]:
21
where ΦB is the barrier height, m* is the effective mass of the electron in the forbidden gap of the dielectric, h and h is the Planck’s constant and the constant divided by 2π, q is the electronic charge, and F is the electric field through the oxide. However, the exponential dependence of tunnel current on the oxide-electrical field causes some critical problems on device process control because, for example, a very small variation of oxide thickness among the cells in a memory array produces a great difference in programming or erasing currents, thus spreading the threshold voltage distribution in both logical states.
C. Modified Fowler-Nordheim tunneling (MFN)
Modified Fowler–Nordheim tunneling (MFN) is frequently observed in SONOS-type memories where the operation is designated to low-voltage (<10V, depending on the Equivalent oxide thickness). A relatively small electric field on tunnel oxide cannot drive charges to inject into the charging trapping layer by DT or FN mechanism. Therefore, the electrons in conduction of the gate should tunnel through the oxide barrier and a triangular nitride barrier, which is MFN tunneling.
D. Trap assistant tunneling effect (TAT)
The charge storage mediums with many traps may cause another tunneling mechanism. For example, the charges tunnel through a thin oxide and arrive to the traps of nitride layer at very low electric field in SONOS systems. During trap assisted injection, the traps are emptied with a smaller time constant and then they are filled. The charge carriers are thus injected at the same distance into the nitride as for MFN injection. Because of the sufficient injection current, trap assistant tunneling
22
may influence in retention [2.8].
2.1.2. Channel Hot-Electron Injection
The physical mechanism of Channel Hot-Electron Injection (CHEI) can be simply understood qualitatively. An electron traveling from the source to the drain gains energy from the lateral electric field and loses energy to the lattice vibrations (acoustic and optical phonons). At low fields, this is a dynamic equilibrium condition, which holds until the field strength reaches approximately 100kV/cm [2.9]. For fields exceeding this value, electrons are no longer in equilibrium with the lattice, and their energy relative to the conduction band edge begins to increase. Electrons are “heated”
by the high lateral electric field, and a small fraction of them have enough energy to surmount the barrier between oxide and silicon conduction band edges. Figure 2-4 shows schematic representation of CHEI in n-MOSFET. On the other hand, the effective mass of hole is heavier than one of electron. It is too hard to obtain enough energy to surmount oxide barrier. Therefore, hot-hole injection is rarely employed in nonvolatile memory operation. For an electron to overcome this potential barrier, three conditions must be held [2.10].
1) Its kinetic energy must be higher than the potential barrier.
2) It must be directed toward the barrier.
3) The field in the oxide should be collecting it.
Nevertheless, a description of the injection conditions can be accomplished with two different approaches. The CHEI current is often explained and simulated following the “lucky electron” model [2.11]. This model is based on the probability of an electron’s being lucky enough to travel ballistically in the field for a distance several times the mean free path without scattering, eventually acquiring enough energy to cross the potential barrier if a collision pushes it toward the Si/SiO2 interface.
23
Consequently, the probability of injection is the lumped probability of the following events, which are depicted in Figure 2-5 [2.12].
1) The carrier has to be “lucky” enough to acquire enough energy from the lateral electric field to overcome the oxide barrier and to retain its energy after the collision that redirects the electron toward the interface (PΦb).
2) The carrier follows a collision-free path from the redirection point to the interface (PED).
3) The carrier can surmount the repulsive oxide field at the injection point, due to the Schottky barrier lowering effect, without suffering an energy-robbing collision in the oxide (Poc).
The current density of CHEI is expressed as
(
b m)
the mean free path associated with the phonon scattering. Em is the lateral electric field at drain.2.1.3. Band to Band Tunneling (BTBT)
Band to band tunneling application to nonvolatile memory was first proposed in 1989. Chen et al. demonstrated a high injection efficiency (~1%) method to programming EPROM devices [2.13]. Band-to-band Tunneling (BTBT) process occurs in the deeply depleted doped surface region under the gate to drain / gate to source overlap region. In this condition, the band-to-band tunneling current density is expressed as
(a) Band to Band Hot Electron Tunneling Injection
24
This injection mechanism is used to nonvolatile memory of PMOS structure.
When band-bending is higher than the energy gap of the semiconductor, the tunneling electron from the valence band to the conduction band becomes significant. The mechanism is at the condition for positive gate voltage and negative drain voltage.
Hence, the hot electrons are injected through the tunnel oxide and then recombine the stored electrons as shown in Fig. 2-6.
(b) Band to Band Hot Hole Tunneling Injection
The injection is applied for NMOS nonvolatile memory device. The mechanism is at the condition for negative gate voltage and positive drain voltage. Hence, the hot holes are injected through the tunnel oxide and then recombine the stored electrons as shown in Fig. 2-7.
The electrons (n-type) / holes (p-type) are accelerated by a lateral electric field toward the channel region and some of the electrons with sufficient energy can surmount the potential barrier of SiO2 [2.14-2.16]. Due to the small oxide field, the electron/hole influence through the oxide can easily reach hundreds of coulombs per square centimeter without failure, it means to the improvement reliability of memory cells.
2.1.4. Channel Initiated Secondary Electron Injection (CHISEI)
The main difference between CHE and CHISEI is that the CHISEI is operation as CHE with a negative bias on body (VB). The CHISEI is highly sensitive to the lateral electrical field and vertical electrical filed. The procedure and the band diagram for the application of CHISEI are as shown in Fig. 2-8. The superior injection of CHISEI operation mode leads to a better program efficiency. The improved program efficiency results from the substrate enhanced gate current component. Under
25
optimized substrate condition, the substrate hot carriers and subsequent injection are expected for the application of low power and high speed.
2.2 Basic Physical Characteristic of Nanocrystal Memory
In the nanocrystal memory, due to the small size of the nanocrystal (3~5 nm), the quantum effect will be obviously. Furthermore, storage carriers in nanocrystal can raise the potential energy due to Coulomb effect. Both quantum effect and Coulomb effect can influence the memory characteristics of the nonvolatile memory.
2.2.1 Quantum Confinement Effect
The quantum dot is a quasi-zero-dimensional nano-scale object and is also composed by small amount of atoms. The quantum confinement energy depended on nanocrystal size has been studied both experimentally and theoretically with the tight-binding model [2.17]. The quantum confinement effect becomes significant when the nanocrystal size shrinks to the nanometer range, which causes the ground state of nanocrystal to shift to higher energy compared with bulk material [2.18]. This result will reduce the barrier high, the difference between work function of the nanocrystal and tunnel oxide. The reduction of the barrier will degrade charge storage ability and programming efficiency for the semiconductor nanocrystals. The theoretical shift of ground state for semiconductor and metal nanocrystals has been proposed by W. Guan et al. at 2007 [2.19]. The ground state shift (∆E) of Ge and Mo nanocrystals are expressed as
688 Where E (∞) is the conduction band minimum for bulk Si and d is the diameter of nanocrystal. For example, a 3 nm Si nanocrystal can have a conduction band shift of 0.1 eV as compared with bulk Si, which is significant enough to affect the electrical
26
performance of the nanocrystal memory cell. Figure 2-9 shows the conduction band minimum up-shift of Si and Ge nanocrystal, and Fermi level up-shift of metal NC as a function of nanocrystal size by W. Guan’s model.
2.2.2 Coulomb Blockade Effect
When an electron is stored in nanocrystal, the potential energy of nanocrystal raised with electrostatic charging energy e2/2Cnc, where Cnc is the nanocrystal capacitance. The Cnc is dependent on nanocrystal size, permittivity and thickness of surrounding dielectric, the tunnel oxide and the blocking oxide. The capacitance is self-consistently calculated using an electrodynamics method [2.20]. The electron charge will raise the nanocrystal potential energy and reduce the electric field across the tunnel oxide, resulting in reduction of the tunneling current density during the write process. It is more dominant at low programming voltages (< 3V). In a flash memory array, device cells often encounter disturbances with low gate voltage soft-programming. The Coulomb blockade effect can effectively inhibit the electron tunneling at low gate voltage and improve the flash memory array immunity to disturbance. However, the Coulomb blockade effect should be reduced by employing large nanocrystal if large tunneling current and fast programming speed were desired.
The Coulomb blockade effect has a detrimental effect on the retention time because the electrons in the nanocrystal are inclined to back into the channel by tunneling if the nanocrystal potential energy is high in retention mode.
2.3 Reliability of Nonvolatile Memory
Unlike to logic IC, nonvolatile memory is more concerned with reliability than performance. The reliability includes two parts, retention and endurance. Both reliability tests are very importance for nonvolatile memory application to the
27
portable electronic productions market and they are norm to define the charge loss ratio in the long-term use. In general, nonvolatile memory must be able to bear 100K-1M program/erase cycles (endurance), and has 10-year retention. Therefore, in this section, the authors will present the operation mechanisms and related non-ideal factors of retention and endurance tests.
A. Retention
For nonvolatile memory, the data information must be conserved over than ten years. This means that the charge loss rate of the stored carriers in the floating gate or discrete trapping centers have to be as low as possible. For example, in modern Flash cells, floating gate capacitance is approximately 1 fF. A loss of only 1 fC can cause a 1V threshold voltage shift. If we consider the constraints on data retention in ten years, the charge loss rate has to less than five electrons per day [2.21].
The possible origins of charge loss are through: 1) tunneling or thermionic emission mechanisms; 2) defects in the tunnel oxide; and 3) de-trapping of charge from insulating layers around the storage medium. Several discharge mechanisms may be responsible for time and temperature dependent on retention behavior of nonvolatile memory devices. Figure 2-11 shows an energy band diagram of SONOS device in the excess electron state [2.22], illustrating trap-to-band tunneling, trap-to-trap tunneling, and band-to-trap tunneling, thermal excitation and Poole-Frenkel emission retention loss mechanisms.
These mechanisms can be classified into two categories. The first category contains tunneling processes that are not temperature sensitive (trap-to-band tunneling, trap-to-trap tunneling and band-to-trap tunneling). The second category contains those mechanisms that are temperature dependent. Trapped electrons may redistribute vertically inside the nitride by Poole–Frenkel emission, which will give rise to a shift
28
in the threshold voltage. Moreover, at elevated temperatures, trapped electrons can also be thermally excited out of the nitride traps and into the conduction band of the nitride (thermal excitation), and drift toward the tunnel oxide, followed by a
in the threshold voltage. Moreover, at elevated temperatures, trapped electrons can also be thermally excited out of the nitride traps and into the conduction band of the nitride (thermal excitation), and drift toward the tunnel oxide, followed by a