奈米點應用於先進非揮發性記憶體之製作與特性研究

國

立

交

通

大

學

電子工程學系 電子研究所

博 士 論 文

奈米點應用於先進非揮發性記憶體之製作與特性研究

Fabrication and Electrical Characterization of Advanced

Nonvolatile Memories Based on Nanocrystals

研 究 生：林昭正

指導教授：曾俊元與張鼎張

奈米點應用於先進非揮發性記憶體之製作與特性研究

Fabrication and Electrical Characterization of Advanced

Nonvolatile Memories Based on Nanocrystals

研 究 生：

林昭正

Student：Chao-Cheng Lin

指導教授：

曾俊元

Advisor：Dr. Tseung-Yuen Tseng

張鼎張

Dr. Ting-Chang Chang

國 立 交 通 大 學

電子工程學系 電子研究所

博 士 論 文

A Dissertation

Submitted to Department of Electronics Engineering and Institute of Electronics

College of Electrical and Computer Engineering National Chiao Tung University

in partial Fulfillment of the Requirements for the Degree of

Doctor of Philosophy in

Electronics Engineering

May 2009

Hsinchu, Taiwan, Republic of China

奈米點應用於先進非揮發性記憶體之製作與特性研究

研究生: 林 昭 正 指導教授: 曾俊元與張鼎張

國 立 交 通 大 學

電子工程學系 電子研究所

中 文 摘 要

近年來，以傳統浮閘(Floating gate)記憶體為基本元件之非揮發性固態半導 體記憶體已被廣泛的應用於各種電子產品。為獲得更高密度、低功率損耗與快速 讀寫的操作驅使目前非揮發性記憶體在元件尺寸上持續的微縮。然而傳統浮閘記 憶體在寫入與抹除的持續操作後，會在穿遂氧化層產生漏電路徑使得原本儲存的 電荷全部流失回到矽基版，而且這個情形隨著尺寸的微縮而更加的嚴重。因此， 在資料保存時間(Retention)和耐操度(Endurance)的考量下，微縮穿遂氧化層的厚 度是非常困難的。具非揮發性的奈米點記憶體被提出並存有希望可取代傳統浮閘 記憶體。由於以空間上與電性上分離的奈米點作為儲存中心，所以可以有效改善 尺寸微縮時，記憶體元件在多次讀寫操作後的資料儲存能力。除了奈米點記憶體 外，電阻式非揮發性記憶體(RRAM)近年來也成為學者與工業界的焦點。主要是由 於其製程簡單且與動態隨機存取記憶體(DRAM)製程相似，可以被整合到半導體的 後段製程。電阻式記憶體擁有高速、非揮發性與低電壓操作的特性等優點。 在本論文中，我們將研究鉬(Mo)與鉬化矽作為奈米點材料來克服傳統非揮 發性記憶體在微縮過程中會遭遇到的困難。相較於其他金屬材料，鉬具有低價 格，高溫熱穩定性，與高功函數等優點。我們首先提出對鉬化矽退火以形成鉬金 屬奈米點，並應用在奈米點非揮發性記憶體上。在室溫環境中，利用雙電子槍(dual electron-gun)同時以一比三的比例蒸鍍矽與鉬(Si and Mo)的方式來形成奈米點自

我形成層，再以退火的方式使奈米點形成。在我們的實驗中，我們發現奈米點的 大小與組成的成分會因退火的氣氛(ambience)不同而有所差異。在氮氣熱退火 下，可以發現所形成的奈米點大約 5-nm 且所組成的成分主要為矽化鉬(MoSi2)， 而在氧氣退火下，會使得所形成的奈米點大小約 20-nm 且組成成分以氧化鉬為 主(Mo oxide)。除此之外，我們發現在氧氣退火前先疊一層氧化矽可阻擋氧化鉬 揮發。此為形成氧化鉬奈米點的一個關鍵步驟。 近年來已經發展了許多方法來形成金屬奈米點記憶體，一般而言，大多數 的方法都需要長時間的熱退火製程在氧氣的環境下，這個步驟會影響現階段半導 體製程中的熱預算和產能且同時造成金屬奈米點過氧化的現像。因此在本論文 中，我們使用一個簡單且快速的製程方法來形成金屬鉬奈米點，並將其應用於非 揮發性記憶體元件上。我們在氬氣和氧氣(Ar/O2)的環境中濺鍍鉬與矽的混合 層，藉由熱退火於氮氣環境下來形成奈米點。利用形成氧化物時不同形成能 (formation energy)的差異，可以在氮氣快速退火的過程中形成金屬奈米點。同 樣的我們也利用此方法濺鍍鉬與矽的混合層在(Ar/N2)的環境中，我們發現，高 密度(6×1012 cm-2)的鉬金屬奈米點可以被形成於氮化矽(SiNx)中，這將有助於解 決奈米點記憶體在元件尺寸微縮時可能造成記憶體元件參數變化的問題。最後我 們製作雙層鉬奈米點記憶體結構並探討其特性。相較於單層奈米點，我們發現發 現多層奈米點不僅在室溫下且在高溫下都擁有較好的電荷儲存能力和保存能力。 由於許多製作奈米點的方法，諸如離子佈植法(ion implantation)、氧化方法 (oxidation)與濺鍍法(sputtering)等都可能在形成奈米點的過程中造成奈米點周遭 的介電質受到損害而影響記憶體的特性。因此，我們提出氨(NH3)電漿處理技術 來改善奈米點周遭介電質的品質，以應用於非揮發性奈米點記憶體。氨電漿技術 被廣泛的應用於半導體工業，由於它的低溫特性，可以降低製程的熱預算。我們 在鉬奈米點嵌入氧化矽與氮化矽的記憶體元件上進行氨電漿的處理，研究中發現 藉由氨電漿的處理可以引入氮鍵結於奈米點周遭的介電質。這些氮鍵結可以有效 的鈍化介電質中的缺陷，並改善金屬奈米點的記憶體特性。 相較於浮閘金屬奈米點非揮發性記憶體，電阻式記憶體被廣泛的研究以期能 整合於後段製程。在論文中，我們研究氧化鋁的電阻式記體特性在不同退火溫度 下的影響。研究中發現，傳統金屬/絕緣層/金屬 (MIM)結構之電阻式記憶體元件

的特性會有很大的變化與不穩定性，這增加了元件在設計與操作上的複雜度。因 此，我們提出金屬/絕緣層/奈米點/絕緣層/金屬的結構來改善電阻式記憶體的特 性。實驗的結果發現，電阻式記憶體的電流不管在開啟(ON-state)或者關閉的狀 態(OFF-state)會因為金屬奈米點的嵌入而穩定下來。除此之外，由關閉狀態至開 啟狀態的起始電壓變化的範圍也會縮小。最後，我們將對我們的研究主題作一總 結。

Fabrication and Electrical Characterization of

Advanced Nonvolatile Memories Based on

Nanocrystals

Student: Chao-Cheng Lin Advisors: Prof. Tseung-Yuen Tseng

Prof. Ting-Chang Chang

Department of Electronics Engineering and Institute of Electronics

National Chiao Tung University, Hsinchu, Taiwan

Abstract

Floating gate composed nonvolatile memories (NVMs) have been widely application in electronic devices in recent years. Requirements of high density, low power consumption and high speed operation drive the memory device scaling down. However, all of the charges stored in the floating gate will leak into the substrate if the tunnel oxide has a leakage path in the conventional NVM during endurance test. Therefore, the tunnel oxide thickness is difficult to scale down without influence of retention and endurance characteristics. Nanocrystals (NCs) NVMs are one of promising candidates to substitute for conventional floating gate memory because the discrete NCs as charge storage centers instead of continuous floating gate can effectively improve data retention for the device scaling down. On the other hand,

resistive switching random access memories (RRAM) have recently received academic and industry’s attention for its benefit of high density, high operation speed and simple structure. Furthermore, the fabrication process of RRAM is similar to that of DRAM, and therefore can be easily integrated into back-end process of memory device.

In this thesis, we propose Mo and Mo silicide as material for fabrication of nanocrystal to overcome the limitation in conventional NVMs during the scaling down process. Compared with other materials, Mo-based material has advantages of low cost, high thermal stability and high work function. Furthermore, Mo has been proposed for the metal gate, and is compatible with the MOSFET fabrication process. Besides, for back-end memory process, we embedded nanocrystal in RRAM to reduce variation of memory characteristics of RRAM.

First, we proposed a Mo silicide serving as NCs self-assembling layer for application in NCs NVMs. Mo silicide layer was deposited by dual electron-gun evaporation of Mo and Si pellets at room temperature, and a post annealing was performed to form NCs. In our results, we found that annealing ambience can influence the size, density and composition of NCs. When Mo silicide layer annealing in N2 ambience, the size of NCs is about 5-nm, and the composition of NCs is

dominated by MoSi2. However, when annealing in O2 ambience, Mo oxide NCs was

formed and its size is about 20-nm. In addition, we found that a pre-annealing-capping oxide layer is a key process to form Mo oxide NCs.

There are many methods have been develop to form nanocrystals for nonvolatile memory application. Most of the methods need long-term annealing in oxygen ambience. This procedure will influence thermal budget and throughput for the current manufacture technology of semiconductor industries. Hence, a simple and fast fabrication technique of Mo NCs was demonstrated for NVM application in this thesis.

The NVM structure of Mo NCs embedded in the SiOx layer was fabricated by

annealing Mo silicate, which was deposited by sputtering Mo and Si target in Ar and O2 ambience. In the formation process, the oxygen plays a critical role for the NCs

formation during sputter process. A high density (~1012cm-2) NCs also can be simply

and uniformly fabricated in our study. We also proposed a formation of Mo NCs embedded in SiNx by replacing O2 by N2 ambience during the sputtering process. A

high density Mo NCs was embedded in the silicon nitride (SiNx) which presented

larger memory effect. Therefore, by using internal competition mechanism in charge trapping layer for these elements (Mo, Si, and O or N), we can obtain a metallic NCs NVM with low thermal budget process. Besides, double-layer NCs NVM structure was fabricated in this work. We found that double-layer NCs structure has better charge storage and retention over than single-layer one under high temperature test because of Coulomb blockade effect can be reduce by sharing the stored carriers into both the first layer and second NCs layer. Furthermore, carriers stored in the first layer can build-up Coulomb expulsion force to reduce the tunneling probability of carriers stored in the secondary NCs layer.

Many proposed methods for fabrication of NCs such as ion implantation, oxidation and sputtering are expect to induce defect in the dielectric around nanocrystals, and influence charge storage ability of memory device. Therefore, we used a post treatment of ammonia (NH3) plasma to improve the quality of the

surrounding dielectric. Ammonia plasma treatment has been widely application in semiconductor industry for its low thermal budget. In this work, ammonia plasma treatment was performed on Mo NCs embedded in oxide or nitride. The results indicate that nitrogen bonding can be introduced into surrounding dielectric to passivate defects, and therefore improve the nonvolatile memory characteristics of the memory device.

In addition to floating gate device, we study the resistive switching random access memories (RRAM) for application in back-end nonvolatile memories. Aluminum oxide was employed as resistive switching layer in this work. We found that the variation of resistive switching characteristics in conventional structure, metal/insulator/metal structure, is large. This increases the complexity of designing and operation of the device. Therefore, we proposed metal/ insulator/nanocrystals/ insulator/metal to reduce variation of memory characteristics in RRAM device. In the final part of this dissertation, the conclusion is presented.

Key words: Nanocrystal, Nonvolatile memory, Mo, double layer, RRAM,

Acknowledgement

歲月如梭，遙想當年進交大時，我仍是個少不經事的研究生，一路以來，碩 士班畢業、念博士班、考資格考、做研究、寫論文與實驗室同仁一起生活的日子 仍歷歷在眼前，如今六年來的研究生活已經告一段落了。回首這些日子來的點點 滴滴，因為有許多人、事、物的幫助與影響下，才得以完成我的博士生涯。 心中滿是說不盡的感激，因為有母校提供我理想與完整的求學環境與研究設 備，讓我得以在研究生活中無所窒礙，盡情發揮。然而身處於這浩瀚無際的知識 宇宙之中，我的指導教授曾俊元老師與張鼎張老師猶如日月般引領著我，邁向學 術研究的光明之路。我要感謝曾俊元老師，老師淵博的知識付予我在研究上的創 造力。在老師身上，學會許多待人處事的道理。老師總能在學生困頓疑惑之際給 予學生正面的鼓勵，讓學生能堅持到底，得以完成今日的學業。我要感謝張鼎張 老師，每當學生在研究上遭遇困難與問題的瓶頸時，老師總能教導學生如何思考 問題以排除困難。總能給予學生一個明確的思考方向，循循善誘，讓學生不會迷 失方向與目標。除此之外，老師平時也很親切的關心學生的生活狀況，造就了實 驗室和諧的氣氛。 感謝志溢、俊豪、世青、致宏、群傑、文俊與沛勳學長們，有你們無私的經 驗傳承，讓我得以順利的步入研究的軌道。感謝鍵賢、俊傑與富凱，有你們的陪 伴，讓我在碩士班的生活多采多姿。感謝述穎與聖錡，這本論文是你們辛苦研究 的結晶。感謝同學緯仁、立偉與志洋，與你們相互討論中讓我的論文更加精彩。 感謝學弟，志瑋、仕承、勝凱、彥廷、睿龍、麗雯、俐婷、貴宇、成能、方方土、 勝杰、侑廷、信淵、耀峰、介銘、陽東、宥豪、杜比、信賢、影帝、冠仲、小油 條、俊興、松蒔、承幼、永昇、奕全與孟漢帶給我許多的歡樂。 在此特別感謝中山的夥伴們，有書瑋、崎峰、原瑞、柏均、佳盛、敏甄、正 杰、冠張、書慶、漢博與志豪等其他學弟妹，有你們大家的幫忙，我才能有順利 的實驗，來完成這本博士論文。

最後，要感謝我最愛的父母，從小到大給予我健全的教育與生活，讓我衣食 無缺，總能在我困頓失意時，提供我最佳的避風港口。有你們的無私的支持，我 才能心無旁騖的完成我的學業，謝謝父親與母親。

昭正 夏 2009 年 7 月於新竹交大

Contents

Chinese Abstract---

I

English Abstract---

IV

Contents---

X

Table Captions---

XIII

Figure Captions---

XIV

Chapter 1 Introduction

1.1 Overview of Nonvolatile Memory---1

1.1.1 SONOS Nonvolatile Memory Devices---3

1.1.2 Nanocrystal Nonvolatile Memory Devices---5

1.1.3 Conclusion---10

1.2 Motivation---10

1.3 Organization of This Thesis---11

Chapter 2 Basic Principles of Nonvolatile Memory

2.1 Programming/Erasing mechanisms of nonvolatile memory---18

2.1.1 Tunneling effect---19

2.1.2 Channel Hot-Electron Injection (CHEI)---22

2.1.3 Band to Band Tunneling (BTBT)---23

2.1.4 Channel Initiated Secondary Electron Injection (CHISEI)---24

2.2 Basic Physical Characteristic of Nanocrystal Memory---25

2.2.1 Quantum Confinement Effect---25

2.2.2 Coulomb Blockade Effect---26

2.3 Reliability of Nonvolatile Memory---26

2.4 Gibbs free energy---29

Chapter 3 Molybdenum-based nanocrystal nonvolatile memories

3.1. Formation and memory characteristics of molybednum silicide nanocrystal---39

3.1.1 Introduction---39

3.1.2 Experiment ---40

3.1.4 Conclusion---43

3.2. Influence of post-annealing ambient on the memory characteristics of molybdenum-based nanocrystal memory---44

3.2.1 Introduction---44

3.2.2 Experiment---44

3.2.3 Results and discussion---45

3.2.4 Conclusion---48

Chapter 4 Memory characteristics of Mo nanocrystal embedded in

silicon oxide and silicon nitride

4.1 Formation and memory characteristics of Mo nanocrystal embedded in silicon oxide---59

4.1.1 Introduction---59

4.1.2 Experiment---60

4.1.3 Results and discussion---61

4.1.4 Conclusion---64

4.2 Formation and memory characteristics of Mo nanocrystal embedded in silicon nitride---64

4.2.1 Introduction ---64

4.2.2 Experiment---65

4.2.3 Results and discussion---66

4.2.4 Conclusion---67

4.3 Enhancement of Charge Storage Ability of Double layer nanocrystal memory structure of Mo embedded in oxide---68

4.3.1 Introduction---68

4.3.2 Experiment---69

4.3.3 Results and discussion---69

4.3.4 Conclusion---71

Chapter 5 Memory characteristics of Mo nanocrystal influenced by

ammonia plasma treatment

5.1. Charge storage characteristics of Mo nanocrystal memory influenced by ammonia plasma treatment---88

5.2.1 Introduction---88

5.1.2 Experiment---89

5.1.3 Results and discussion---90

5.2. Influence of ammonia plasma treatment on the memory characteristics of

Mo nanocrystal embedded in silicon nitride---94

5.2.1 Introduction---94

5.2.2 Experiment---95

5.2.3 Results and discussion---95

5.2.4 Conclusion---98

5.3. Comparison of memory characteristics of Mo nanocrystal embedded in SiOx and SiNx 5.3.1 Introdution---98

5.3.2 Results and discussion---99

5.3.3 Conclusion---100

Chapter 6 Nanocrystal technique application in Resistive Switching

Memory

6.1 Introduction---113

6.2 Experiment---113

6.3 Results and discussion---114

6.4 Conclusion---117

Chapter 7 Conclusion---

130

References---

133

Vita---

148

Table Captions

Table 5-1 Comparison of memory characteristics for Mo nanocrystal in SiOx without

and with plasma treatment---105 Table 5-2 Comparison of memory characteristics for Mo nanocrystal in SiNx without

and with plasma treatment---108 Table 5-3 Comparison of memory characteristics for Mo nanocrystal in SiOx and SiNx

Figure Captions

Chapter 1

Figure1.1 Structure of the conventional floating-gate nonvolatile memory device. Electronically continuous poly-silicon floating gate is employed as the charge storage media. ---14 Figure1.2 Tunnel oxide and operation voltage scaling predicted by the 2007

International Technology Roadmap for Semiconductors.---14 Figure1.3 Development of the gate stack of SONOS EEPROM memory devices. The optimization of nitride and oxide films has been the main focus in recent years. ---15 Figure1.4 Structure of the nanocrystal nonvolatile memory device. The nanocrystals are used as the charge storage element instead of the continuous poly-Si floating gate. ---15 Figure1.5 Energy band diagrams of (a) Ge, (b) HfO2 and (c) Mo nanocrystals

nonvolatile memories. Sub.: Silicon substrate, Box.: Blocking oxide, G: Gate.---16 Figure1.6 (a) self-aligned doubly stacked Si nanocrystals device and (b) energy band diagram of the structure---16 Figure1.7 (a) Schematic diagram of the p-channel memory device using Ge–Si as

floating gates. (b) Energy-band structure of the memory. diagram of the structure---17

Chapter 2

Figure2.1 ID– or gD–V curves of an FG device when there is no charge stored in the

FG (curve A) and when negative charges are stored in the FG (curve B).---31 Figure2.2 Wavefunctions exhibiting electron tunneling through a rectangular barrier. ---31 Figure2.3 Four tunnel mechanisms in the nonvolatile memory described by Hu and White et al. ---32 Figure2.4 Schematic cross section of MOSFET. ---33 Figure2.5 Schematic energy band diagram describing the three processes involved in electron injection. ---33 Figure2.6 Schematic sketch and energy band diagram of Band to Band Hot hole Injection.---34 Figure2.7 Schematic sketch and energy band diagram of Band to Band Hot hole

Injection. ---35 Figure2.8 Schematic sketch and energy band diagram of Channel Initiated Secondary Electron Injection. ---36 Figure2.9 Conduction band minimum up-shift of silicon nanocrystal and Fermi level up-shift of metal NC as a function of nanocrystal size by W. Guan’s model [2.19].---36 Figure2.10 Conduction band minimum up-shift of silicon nanocrystal and Fermi level up-shift of metal NC as a function of nanocrystal size by W. Guan’s model [2.19].---37 Figure2.11 Energy band diagram of a SONOS device in the excess electron state,

trap-to-trap tunneling (T-T), band-to-trap tunneling (B-T), and thermal excitation (TE) and Poole–Frenkel emission (PF) [2.22].---37 Figure2.12 Threshold voltage window closure as a function of program/erase cycles

on a single cell owing to the degradation of tunnel oxide.---38 Figure2.13 Anomalous stress induced leakage current (SILC) modeling. The leakage is caused by a cluster of positive charge generated in the oxide during erase.---38

Chapter 3

Figure3.1 Process of flow and device structure of this study. The annealing process at step 5 is in nitrogen ambience.---49 Figure3.2 The capacitance-voltage (C-V) hysteresis of the MOIOS structure. A

counterclockwise memory window is about 5.1 V at the sweeping voltage of 9 V.---49 Figure3.3 The transmission electron microscopy (TEM) analysis of Mo silicide

nanodots layer.---50 Figure3.4 XPS of Mo 3d spectrum of the Mo silicide layer with and without

annealing.---51 Figure3.5 XPS of Si 2p spectrum of the Mo silicide layer with and without annealing.

---52 Figure3.6 Retention behavior of Mo silicide nanocrystal. ---53 Figure3.7 Process flow and device structure of this study. The annealing was

performed in oxygen ambience.---53 Figure3.8 S e c o n d a r y i o n m a s s s p e c t r a ( S I M S ) o f t h e o x i d e / M o

silicide/oxide/substrate structure. ---54 Figure3.9 The C-V curve of the sample (a) without and (b) with pre-capping oxide layer.---55 Figure3.10 XPS Mo 3d and Si 2p spectra for the Mo silicide layer after annealing in o x y g e n a m b i e n c e . - - - 5 6 Figure3.11 TEM results of Mo silicide annealing in (a) nitrogen ambience and (b)

oxygen ambience.---57 Figure3.12 Retention behavior of Mo silicide annealing in nitrogen and oxygen

Chapter 4

Figure4.1 Process flow and device structure of Mo nanocrystal embedded in silicon oxide.---72 Figure4.2 Secondary ion mass spectra in SiO2/OMoSi/SiO2/Si substrate of

as-deposited and 900°C-annealed samples.---72 Figure4.3 X P S O 1 s s p e c t r a o f O M o S i l a y e r a t v a r i o u s a n n e a l i n g

temperatures.---73 Figure4.4 X P S M o 3 d s p e c t r a o f O M o S i l a y e r a t v a r i o u s a n n e a l i n g

temperatures.---73 Figure4.5 Cross-section TEM of OMoSi layer after annealing at (a) 700°C and (b)

800°C.---74 Figure4.6 C-V curve of (a) 700°C- and (b) 800°C-annealed samples.---75 Figure4.7 A comparison of memory window between 800°C and 900°C -annealed samples.---76 Figure4.8 TEM plane-view of OMoSi layer after annealing at (a) 800°C and (b)

900°C.---77 Figure4.9 Comparison of retention behavior of (a) 800°C- and (b) 900°C-annealed

samples. ---78 Figure4.10 Quantization effect on Si, Ge and Mo nanocrystal [4-16]. ---79 Figure4.11 Figure 4-11 Plane-view TEM of Mo nanocrystal embedded in SiOx and

SiNx---80

Figure4.12 XPS Si 2p (a), and N 1s and Mo 3p (b) of nitrogen incorporated Mo silicide layer after annealing at 900 °C---81 Figure4.13 C - V c u r v e o f M o n a n o c r y s t a l e m b e d d e d i n S i Ox a n d

Figure4.14 Memory window of Mo in SiOx and SiNx at various sweeping

voltages.---83 Figure4.15 A comparison of retention behavior for Mo in SiNx and Mo in

S i Ox. - - - 8 3

Figure4.16 P r o c e s s f l o w a n d m e m o r y s t r u c t u r e o f d o u b l e l a y e r M o nanocrystal.---84 Figure4.17 Cross-section TEM of double layer Mo nanocrystal embedded in silicon oxide.---84 Figure4.18 C-V curve of double layer structure for Mo nanocrystal in SiOx. ---85

Figure4.19 Memory window of single and double layer at various sweeping amplitudes.---85 Figure4.20 Comparison of retention characteristics for single- and double- layer

structures at (a) room temperature (27°C) and (b) 85°C. ---86 Figure4.21 Band diagrams of (a) single- and (b) double-layer structures in retention. ---87

Chapter 5

Figure5.1 Process flow and structure of plasma treated Mo nanocrystal memory.---101 Figure5.2 Plane-view TEM of Mo nanocrystal memory (a) without and (b) with NH3

p l a s ma t r e a t me n t . - - - -- - - 1 0 2 Figure5.3 XPS (a) Si 2p, and (b) Mo 3p and N 1s spectra of oxygen-incorporated Mo silicide layer with and without plasma treatment.---103 Figure5.4 C-V characteristics and band diagram of Mo nanocrystal memory (a)

without and (b) with NH3 plasma treatment. ---103

Figure5.5 Retention characteristics of the NCs memory structure with (a) room temperature, 27°C and (b) 85°C. The dotted line and solid line are the extrapolated value of retention data after 1000s, which this range is a steady state.---104 Figure5.6 Energy bond diagram of multi-layer NiSi NCs embedded in SiNx. The

ground states of first and second layer of multi-layer structure were caused by the energy level quantization effect.---104 Figure5.7 (a) Comparison of endurance characteristics of Mo nanocrystal memory

with and without plasma treatment. (b) Band diagram of Mo nanocrystal memory during programming. ---105 Figure5.8 XPS (a) Mo 3p and N 1s, and (b) Si 2p spectra of nitrogen incorporated M o s i l i c i d e l a y e r. - - - 1 0 6 Figure5.9 C-V characteristics at various sweeping voltage for Mo nanocrystal

m e m o r y ( a ) w i t h o u t a n d ( b ) w i t h p l a s m a t r e a t m e n t . ---109 Figure5.10 Comparison of retention behavior between the Mo nanocrystal memory

Figure5.11 C-V hysteresis characteristic of (a) Mo in SiOx and (b) Mo in SiNx after

N H3 p l a s m a t r e a t m e n t . - - - 1 0 9

Figure5.12 Retention behavior of Mo nanocrystal in (a) SiOx and (b) SiNx before and

after 106 program/erase (P/E) cycles. ---110

Figure5.13 Simulation structure and electrical field distribution of Mo nanocrystal embedded in (a) SiOx and (b) SiNx. ---111

Figure5.14 Electrical field distribution along Y-axis crossing the Mo nanocrystal in SiOx and in SiNx. ---112

Chapter 6

Figure6.1 Process flow and structure of RRAM embedded with Ni silicide nanocrystals ---119 Figure6.2 Cross-section TEM analyses of Ti/ Al2O3/Ni silicide/ Al2O3/Pt structure

for (a) as-deposited, and after annealing at (b) 300°C, (c) 550°C and (d) 700°C---121 Figure6.3 plane-view TEM analyses for Al2O3/Ni silicide/Al2O3 structure after

annealing at 500°C. ---122 Figure6.4 XPS Al 2p spectra at various annealing temperature (a) and binding energy

s h i f t ( b ) - - - 1 2 3 Figure6.5 conducting current-sweeping voltage characteristics of (a) as-deposited sample with Ni-O-Si layer, (b) annealing at 300°C, and annealing at 500°C (c) without and (d) with Ni-O-Si layer.---125 Figure6.6 linear-linear plot of I-V characteristic for the memory device embedded

with Ni silicide nanocrystals.---126 Figure6.7 Double-logarithmic scale plots of the I-V curves for both positive and

negative sweeping region in the Ti/Al2O3/Ni NCs/Al2O3/Pt device. --127 Figure6.8 Simple band diagram at ON-state of negative bias in the Ti/Al2O3/Ni

NCs/Al2O3/Pt device.---128 Figure6.9 Electrical field simulation in the Ti/Al2O3/Ni silicide NCs/Al2O3/Pt

device.---128 Figure6.10 Formation of high-conducting path in the memory device (a) without and (b) with nanocrystal.---129 Figure6.11 Retention characteristics of Ti/Al2O3/Ni silicide NCs/Al2O3/Pt device. - - - 1 2 9

1

Chapter 1

Introduction

1.1 Overview of Flash Memory

In recently years, flash memory has been widely used in the portable productions, such as MP3 player, PDA, Notebook, flash driver and so on. Flash memory is nonvolatile, which is that no power is needed to maintain the data storage in the chip. The flash memory can be classified into two types, NOR and NAND flash memories, according to their functions and advantages [1.1]. NOR Flash offers faster read speed and random access capabilities, making it suitable for code storage in devices such as PDA and cell phone. In contrast to NOR flash, the NAND memory, which offers faster write/erase capability and higher density is typically used for storing large quantities of data. Flash memory has several advantages such as fast read access time and better kinetic shock resistance than hard disk. The fabrication process of flash memory is compatible with the current complementary-metal-oxide-semiconductor (CMOS) process and is a suitable solution for embedded memory application. It has become the mainstream nonvolatile memory device in last few decades.

The flash memory is based on the floating gate device, which was invited by Kahng and Sze at Bell Labs in 1967 [1.2]. The floating device, as shown in figure 1-1, is constructed by the MOSFET device with a modified gate stack (tunnel oxide/floating gate/blocking oxide/gate electrode). In the floating device, charges are injected from the silicon substrate across the tunneling oxide and stored in the floating gate. The stored charges can cause a threshold-voltage shift, and the device is at a high-threshold state (programmed). For a well-designed memory device, the stored

2

charge can maintain in floating gate over 100 years without external power [1.2]. After a suitable erase voltage is applied, the stored charges can be extracted from floating gate, and the device returns to a neutral state (no charges in the floating gate).

To achieve the high density array, low power consumption, high speed operation, and enough reliability on commercial applications, the cell size of floating gate device must be scaling down. However, conventional poly-silicon floating device has a limitation on scaling down of the tunnel oxide. According to the 2007 International Technology Roadmap for Semiconductors (ITRS) flash memory [1.3], tunnel oxide thickness must be more than 6-nm to assure enough retention time, as shown in Fig. 1-2. This basic limitation on tunnel oxide leads to a high programming/erasing voltage and low operation speed for the device. If tunnel oxide were scaling to below 2-nm, the programming/erasing voltage could be reduced to smaller than 4V. Although the thin tunnel oxide can effectively enhance the programming/erasing speed and reduce operation voltage, the thick oxide is required to guarantee the ten years retention time. Furthermore, after endurance test, traps can generate in tunnel oxide, which might induce a leak path in the tunnel oxide and results in the stored charge loss. These difficult trade-off problems hinder the scaling.

To overcome the trade-off problems, discrete trapping center instead of electrically continuous poly-silicon floating gate have been received much attention in recent years [1.4-1.6]. Unlike to the poly-silicon gate, charges stored in the distributed centers can suppress their lateral migration. Therefore, even if an intrinsic defect or extrinsic defect chain exists in the tunnel oxide, they can only influence a few trapping centers allowing aggressive scaling of tunnel oxide. The main realize of discrete trapping center is poly-silicon/oxide/nitride/oxide/Si (SONOS) memory and nanocrystal memory. Both structures have been proposed to reduce the tunnel oxide without sacrificing the retention time.

3

1.1.1 SONOS Nonvolatile Memory Devices

Since the first nitride based device was proposed by Wegener et al. in 1967s, the device structure has been evolution to SONOS structure. The evolution is shown in Fig. 1-3. Early nitride based device was constituted by metal/nitride/oxide/silicon (MNOS) device in 1967s. It is well known that silicon nitride film have a large number of trapping centers. Therefore, employing the silicon nitride as the charge trapping layer can cause an enough threshold voltage shift for circuit to identify logic “0” and “1”. The silicon nitride trap-based devices are widely studied for charge storage device in early 1970s. Initial device structure, MNOS, was constructed by aluminum gate electrode, 45nm-thick silicon nitride layer, silicon oxide and p-channel device. Write/erase voltage of device is as high as 25-30 V. In the late 1970s and early 1980s, the nitride based device move to the n-channel SNOS device with improved write/erase voltages of 14-18 V. In the late 1980s and early 1990s, n- and p-channel SONOS device emerged with low write/erase voltages of 5-12 V. Compared with SNOS device, the SONOS device has some advantages: (a) the device reduces write voltage because the blocking action of the top oxide removes any limitation on the reduction of the nitride thickness; (2) charge transport between gate electrode and nitride trap layer is minimized for both gate polarities, particularly for hole injection; (3) retention is improved because there is a minimal loss of charge for the gate electrode.

In recent years, there has been a dramatic proliferation of research concerned with SONOS memory because its advantages over the conventional floating gate device. These include reduction of operation voltage, increase of operation speed, enhancement of reliability and elimination of drain-induced turn-on [1.7, 1.8]. Unlike to the conventional floating device, charges are stored in distributed trap in nitride layer of SONOS device. Typical traps density is in the order of 1018-1019 cm-3

4

according to the Yang et al.’s calculation [1.9]. The charges stored in the distributed traps can prevent charges from being moving in nitride floating gate layer, and therefore the SONOS device has better endurance than the conventional floating gate memory.

Even though the SONOS memory device has a lot of advantages over the conventional floating gate memory, the SONOS is still face the challenge on the future nonvolatile memory application, which demand for low operation voltage (<5 V), low power consumption, long-term retention, and excellent endurance. Various approaches have been proposed for improving the SONOS performance and reliability, such as nitride bandgap engineering, device structure engineering and high-k material as the charge storage layer [1.10]. Chen et al. proposed a Si3N4 bandgap engineering

method to improve the endurance and retention characteristics. A nitride layer with different Si/N ratio throughout the layer can significantly increased the charge trapping efficiency [1.11].

T. Sugizaki et al. proposed HfO2 and Al2O3 as the charge trapping layer to

replace the silicon nitride. They found that employing HfO2 or Al2O3 as the charge

trapping layer can improve the program/erase speed. The Al2O3 with high valence

band shift to Si substrate can prevent the memory from being over-erase. Tan et al. showed that over-erase phenomenon in SONOS memory can also be minimized by replacing silicon nitride with mixed HfO2 and Al2O3 as the charge storage layer. The

charge retention and endurance performance was improved by the addition of 10% Al2O3 in HfO2 to form HfAlO thin film as the charge trapping layer [1.12]. M. She et

al. demonstrated that high quality nitride instead of SiO2 as the tunnel dielectric for

SONOS structure memory can improve the programming speed and retention time under a low programming voltage [1.13]. C. H. Lee et al. proposed a nitride based device structure of SiO2/SiN/Al2O3/TaN metal gate (SANOS) [1.14]. The charges in

5

the SiN layer can be erased efficiently by Fowler-Nordheim tunneling mechanism of holes even at thicker tunnel oxide where the holes direct tunneling is suppressed. The effect of TaN gate with higher work function than poly-silicon gate can improve the program/erase characteristics of the SANOS devices. The use of TaN metal gate can block electron current through the Al2O3 more efficiently than a conventional

poly-silicon gate, which results in faster program/erase speed, and significant decrease of the saturation level of the erase VTH.

S. C. Chen et al. studied a polycrystalline silicon thin film transistor with oxide/nitride/oxide stack gate structure and multiple nanowire channels for nonvolatile SONOS memory application [1.15]. The proposed structure can improve electrical characteristics including increase of drain current, a steep subthreshold slop and excellent program/erase efficiency due to the tri-gate structure and channel corner effect. Such structure is thereby highly promising to application on future system-on-panel display application.

Novel device structures are also indispensable to make the floating gate nonvolatile memory more scalable. SONOS memory device can make tunnel oxide decreased, and a FinFET structure has the better controlling capability on short channel effect than the conventional MOSFET structure. FinFET embedded with nitride layer as the floating gate (FinFET SONOS memory) has been demonstrated with a small cell size to provide excellent performance and reliability. Hence, FinFET SONOS memory is also a potential candidate for next generation floating gate nonvolatile memory [1.16, 1.17].

1.1.2 Nanocrystal Nonvolatile Memory Devices

The nanocrystal memory is a direct descendant of conventional floating gate memory [1.4]. The biggest difference between nanocrystal and conventional floating

6

gate memory is the manner of charge storage. In conventional floating gate memory, charges are stored in electrically continuous polycrystalline silicon floating gate. However, charges are stored in the separated nanocrystals for the nanocrystal memory. Fig. 1-4 illustrates a typical nanocrystal memory device. As shown in the Fig., the nanocrystals are separated by their surrounding dielectric. When programming voltage is applied on gate electrode, carriers can inject from conduction channel to the nanocrystals. The injected carriers can store in the lateral isolated nanocrystals. Each nanocrystal will typically store only a handful of electrons and the charges stored in these nanocrystals collectively control the channel conductivity. The first nanocrystal memory device was proposed in 1995 by S. Tiwari et al, who demonstrated the nonvolatile memory device with a Si nanocrystals floating gate [1.18]. They showed that a large bistability with a significant threshold voltage shift can be obtained at low bias voltages with built-in Coulomb blockade of additional carrier injection.

Using the nanocrystals as charge storage media instead of poly-Si floating gate has several advantages. First, memory with discrete charge storage elements allow more aggressive scaling of the tunnel oxide and exhibit superior characteristics compared to Flash memories in terms of operation voltage and write/erase speed. The main reason for the improvement is because charges stored in electrically isolated nanocrystals are more immunity to local defect chain. Due to the absence of drain with floating gate coupling, nanocrystal memory suffers from less drain-induced-barrier-lowering (DIBL) effect than conventional floating gate device. This advantage allows the use of a high drain bias in read operation mode, and therefore improves the memory access time. Furthermore, Nanocrystal memories are characterized by excellent immunity to stress induced leakage current (SILC) and oxide defect due to the distributed nature of charge storage. Research in the nanocrystal memories have focused on the development of fabrication processes,

7

nanocrystal materials and integration of nanocrystal based storage layer in real memory devices.

The process for fabrication nanocrystal memory requires well control on four important parameters: (1) Tunnel oxide thickness. The oxide thickness must be well controlled and uniformity must be good enough to prevent the variation from cell to cell. (2) The quality of blocking oxide. The quality of the oxide must ensure that the carrier cannot tunnel from gate electrode to nanocrystal layer. (3) The density of nanocrystal and (4) the size of nanocrystal. Considering the nanocrystal size, larger nanocrystal size provides high program/erase efficiency because the larger size of nanocrystal suffers from smaller quantum confinement and coulomb blockade effects. However, it is desirable to reduce the nanocrystal size to achieve a high density of nanocrystal on the channel for a uniform devices array. Therefore, there is a trade-off in the nanocrystal size. A typical target is a density of 1012 cm-2, and this require nanocrystal size of about 5-nm.

The ideal goal in optimizing the nanocrystals memory device is to achieve both the fast write/erase of DRAM and the long retention time of Flash memories. For this purpose it is needed to produce an asymmetry in charge transport through the gate dielectric to maximize the ratio of IG,write/erase / IG,retention.

So far, there are many materials have been proposed for nanocrystal nonvolatile memory application such as Si, Ge, HfO2, CeO2, Co, Ni, Pt and Mo. These materials

can be classified into three categories: semiconductor, high-k dielectric and metallic nanocrystals. Fig. 1-5 shows the band diagram for the (a) Ge, (b) HfO2 and (c) Mo.

A. Semiconductor Nanocrystal Memories

Since S. Tiwari et al. proposed the first Si nanocrystal memory device, there is much research on improving the retention and endurance characteristics of the device.

8

R. Ohba et al. proposed that self-aligned doubly stacked Si nanocrystals as the floating gate to enhance the memory characteristics [1.18]. Their structure is shown in Fig. 1-6(a). The mechanism for improving the memory characteristics is originated from the quantization effect on the lower nanocrystal. As indicated in Fig. 1-6(b), the smaller nanocrystal at the bottom has larger quantum confinement effect over than that for the larger nanocrystal. Therefore, after the charge inject into the upper nanocrystal, the charge is blocked by lower nanocrystal, which improves the retention of the memory. However, this method needs a well control on size of nanocrystal and the oxide layer between the upper and lower nanocrystals.

King and Hu demonstrated that the superior properties of Ge nanocrystal memory over those based on Si in terms of writing/erasing and retention time because smaller band gap of Ge. Recently, the simulation results indicated that the Ge/ Si heteronanocrystal improves the retention characteristics dramatically without influencing the writing/erasing speed. J. Lu et al. demonstrated the Charge storage characteristics in the metal-oxide-semiconductor memory structure based on gradual Ge1−xSix/Si heteronanocrystals. Their results show that the retention of hole was

improved. The main reason for improved retention of hole is due to additional Si barrier to block the hole, as shown in Fig. 1-7.

Although various methods has been proposed to improve the reliability of semiconductor nanocrystal memories, the nanocrystal suffer from a severe quantum confinement effect. The quantum confinement effect can widen the band gap as the decrease of the nanocrystal size. Theoretical calculation shows that Ge nanocrystal will experience a serious conduction band shift when its size is smaller than 5-nm. This effect limits the ultimate size of nanocrystal and impedes the device scaling down.

9

B. High-k dielectrical Nanocrystal Memories

Two bits operation through charge storage in nitride layer upon drain or source side have been widely investigated. The crucial issue for two bits operation is migration of the stored charge, which degrades the threshold voltage shift (or memory window). To alleviate the issue, Chen et al. proposed the high-k dielectric nanocrystal nonvolatile memories in 2004 [1.19, 1.20]. They fabrication the nanocrystal by using co-sputtering Hf and Si in oxygen followed with high-temperature annealing to form the high-k dielectric nanocrystal for SONOS-type memory devices. These devices are not only like SONOS-type nonvolatile memory but also can restrain the stored charge lateral migration effect. Therefore, the performance of high-k dielectric nanocrystal for 2-bits operation is better than SONOS-type memory device.

C. Metallic Nanocrystal Memories

In optimizing nonvolatile memory device, the ideal goal is to achieve the fast write/erase of DRAM and long retention time of Flash memories simultaneously. For this purpose we need to create an asymmetry in charge transport through the gate dielectric to maximize the IG, Write/Erase/IG, Retention ratio. One approach to achieve this

goal is to engineer the depth of the potential well at the storage nodes, thus creating an asymmetrical barrier between the substrate and the storage nodes, i.e., a small barrier for writing and a large barrier for retention. This can be achieved if the storage nodes are made of metal nanocrystals. Then by engineering the metal work function, the barrier height can be adjusted by about 2 eV, giving much freedom for device optimization.

Compared with semiconductor or high-k dielectric nanocrystal memories, the metal nanocrystals memories have several advantages include higher density of states around the Fermi level, stronger coupling with the conduction channel, a wide range

10

of available work functions, and smaller energy perturbation due to carrier confinement [1.21]. Furthermore, electrostatic modeling from both analytical formulation and numerical simulation is demonstrated that the metal nanocrystals can significantly enhance the electric field between the nanocrystal and the conduction channel, and hence can achieve much higher efficiency in low-voltage operation [1.22].

In the future, the driving force behind the development of nanocrystal memory is its potential on scaling device structure without sacrificing reliability and improving operation speed. Nevertheless, there are still challenges await nanocrystal memories in the long road to commercialization.

1.1.3 Conclusion

Nanocrystal memories have been presented in the mid-nineties as a possible alternative to conventional floating-gate nonvolatile memory, by allowing a further decrease in the thickness of tunnel oxide. Research in this area has focused on the development of nanocrystal materials and fabrication processes, and on the integration of nanocrystal-based storage layers in actual memory devices. Although, various methods have been investigated to improve nanocrystal memory characteristics, it is also a rigorous challenge on nanocrystal memory for next generation nonvolatile memory in term of uniformity of nanocrystal size and its reliability.

1.2

Motivation

According to the Semiconductor Industry Association (SIA) International Technology Roadmap for Semiconductors (ITRS) report, it can be realize that the severe challenges of floating gate flash are to achieve reliable, low-power, and high

11

program/erase speed [1.3]. The challenges are originated from: (1) the limitation on the thickness of tunnel oxide, and (2) reliability of the memory device. For the tunnel oxide thickness, the ITRS report indicated that the oxide thickness of floating gate device is restricted to 6-nm to guarantee enough retention time for memory applications. However, high speed and low power operation require the thinner tunnel oxide. In order to get balance between program/erase speed and retention time, there is a trade-off between the speed and the retention to get the optimal tunnel oxide thickness. On the other hand, the limitation on reliability is due to the stress induced formation of leakage path in tunnel oxide. As the memory device suffer from a large number of program/erase cycles, the carrier transport through tunnel oxide can generate the leakage path, which results in total stored charge leak out of the floating gate through the generated leakage path. Therefore, the conceptual of discrete charge storage media instead of continuous poly-Si floating gate was proposed to surmount the limitations and realized through charge trapping layer (such as nitride layer with traps) and discrete nanocrystals. Unlike to the floating gate, the charge stored in discrete centers can alleviate the trade-off between the high speed operation and long term retention, allowing further scaling down of the memory devices.

1.3

Organization of This Thesis

In this thesis, we investigated the molybdenum-based nanocrystal memory to overcome the limitation of conventional floating gate memory. Furthermore, we introduce nanocrystal into resistance switching memory RAM (RRAM) to enhance the memory characteristics.

Chapter 1 introduces the function and characteristic of NOR and NAND flash memory. Furthermore, discrete charge storage type memories including SONOS-type and nanocrystal-type are organized and discussed. The evolvement of the

12

SONOS-type memory and the research of current status on the nanocrystal memory are reviewed.

In chapter 2, we briefly describe the programming/erase operations of the majority of Flash memories described in the literature. Some important mechanisms such as Programming/Erasing mechanisms, basic Physical characteristic, and reliability of nonvolatile memory and Gibbs free energy are reviewed. The programming/Erasing can be performed by different tunneling mechanism.

In chapter 3, we investigate the nonvolatile memory characteristics of Mo silicide nanocrystal memory through annealed electron-gun evaporated Mo silicide layer in different ambience. Mo nanocrystal can be formed after annealed in N2

ambience. However, the retention of the Mo nanocrystal is not ideal. The retention can be improved by introduce oxygen during annealing process due to reduce the Si dangling bonds in surrounding dielectric.

In chapter 4, Mo nanocrystal embedded in silicon oxide (SiOx) and nitride (SiNx)

as charge storage layer is studied. Mo nanocrystal can form in the SiOx after

annealing oxygen-incorporated Mo silicide layer at a critical temperature without degrading the tunnel oxide. It is found that the memory window and retention are influenced by various annealing temperature. Furthermore, the density of nanocrystal can be increased by annealing nitrogen-incorporated Mo silicide layer. The Mo nanaocrystal in SiNx have larger memory window than Mo nanocrystal in SiOx

because the high density of nanocrystal and high permittivity of nitride can enhance the coupling to the conduction channel.

In chapter 5, we investigate the ammonia plasma treatment influence on Mo nanocrystal memory. It is found that the treatment can improve the quality of surrounding dielectric by nitrogen passivation. After the passivation, the memory characteristic of Mo nanocrystal in dielectric can be improved. In addition, we

13

compare the memory characteristics between Mo in SiOx and Mo in SiNx as charge

storage layer. The different characteristics are explained through charging effect. Resistance switching memory emerges as a new candidate for future nonvolatile memory. The resistance switching memory has a capacitor-like structure composed of insulating or semiconducting materials sandwiched between two metal electrodes. Because of its simple structure, highly scalable cross-point and multilevel stacking memory structures have been proposed. In chapter 6, the reproducible and stable resistance switching phenomenon in Al2O3 is demonstrated. The Ni silicide

14

Figure 1-1 Structure of the conventional floating-gate nonvolatile memory device. Electronically continuous poly-silicon floating gate is employed as the charge storage media.

Figure 1-2 Tunnel oxide and operation voltage scaling predicted by the 2007 International Technology Roadmap for Semiconductors.

15

Si Substrate

2 nm SiO

2

45 nm

Si

3

N

4

Al gate

Si Substrate

2 nm SiO

2

Al gate

2 nm SiO

2

25 nm Si

3

N

4

Si Substrate

2 nm SiO

2

Al gate

4 nm SiO

2

5 nm Si

3

N

4

MNOS

1960s~1970s

_1970s~1980s

SNOS

SONOS

_1980s~

Figure 1-3 Development of the gate stack of SONOS EEPROM memory devices. The optimization of nitride and oxide films has been the main focus in recent years.

Figure 1-4 structure of the nanocrystal nonvolatile memory device. The nanocrystals are used as the charge storage element instead of the continuous poly-Si floating gate.

16

Figure 1-5 The band diagram for the (a) Ge, (b) HfO2, (c) Mo nanocrystals. Sub.:

substrate, Tox.: tunnel oxide, Box.: blocking oxide.

Figure 1-6 (a) self-aligned doubly stacked Si nanocrystals device and (b) energy band diagram of the structure

17

Figure 1-7 (a) Schematic diagram of the p-channel memory device using Ge–Si as floating gates. (b) Energy-band structure of the memory.

18 

Chapter 2

Basic Principles of Nonvolatile Memory

2.1 Programming/Erasing mechanisms of nonvolatile memory

Charge storage based nonvolatile memories (NVMs), such as nanocrystal memory and polycrystalline silicon/silicon oxide/nitride/silicon oxide/silicon substrate (SONOS) structure memory, are based on the conceptual of floating gate device. Using various programming mechanism, after charging, the total stored charge Q is equal to integrated injection current. This results in a shift of the threshold voltage by the amount 2 2 ε Q d V_T =− Δ (2-1)

where Q is the total charge stored in the floating gate, and C is the capacitances _FG between the floating-gate (FG) and control gate [2.1-2.3].

Two methods are used to measure the threshold-voltage shift: (1) change in the channel conductance gD of the MOSFET which is measured at small drain voltages.

The channel conductance of an n-channel MOSFET is given by ), ( _{G T} ox D D D C V V L Z V I g = = μ − VG > VT, (2-2)

and (2) ID-VG plot as shown in Fig. 2-1. After the programming, the floating-gate of

the memory are charged with a number of negative charges and results in threshold-voltage shift to a higher level (Curve B), which is defined as a state of “1” in binary. On the other hand, the stored charge can be removed after erasing and the threshold-voltage changes from the higher value to a lower one, which is defined as a state of “0” (curve A).

19 

There are many mechanisms can be used to programming and erasing the memory cell. In general, the mechanisms can be divided into two categorizes, hot carrier injection and tunnel effect including direct tunneling, Fowler-Nordheim tunneling and band to band tunneling. These mechanisms for programming/erasing of memory cell can result in difference characteristics and we will briefly introduce them at the following.

Models for programming/erasing

2.1.1 Tunneling effect

Tunneling mechanisms is a quantum mechanical phenomenon. Unlike to classical mechanics, an electron can be represented by its wave function. The function does not terminate on the side wall of a finite potential barrier but can penetrate into the barrier as shown in Fig. 2-2. The tunneling probability can be calculated from the Schrodinger equation. For complicated barrier shapes, simplification of the equation is made by the WKB (Wentzel-Kramers-Brillouin) approximation if the potential U(x) is a slow function of x. The tunneling probability can then be calculated by

} ] ) ( [ 2 2 2 exp{ 2 1 * 2 2 dx E x U m T x x A B t = ≈ −

∫

− h ψ ψ . (2-3) With tunnel probability eqn. (2-3), the tunneling current Jt can be calculated from

the production of the number of available carriers in the Region-A, and the number of empty states in the region-B,

∫

− = qm F N T F N dE J_{t A A t}(1 _B) _B 2 2 3 * h π (2-4)

where FA, FB, NA, and NB are the Fermi-Dirac distributions and densities of states and

the subscript represents the corresponding regions.

20 

into four different tunneling mechanisms, direct tunneling (DT), Fowler-Nordheim tunneling (FN), modified Fowler-Nordheim tunneling (MFN) and trap assistant tunneling (TAT). These mechanisms are the main carrier transport mechanisms employed in the floating gate NVM. Fig. 2-3 shows these four tunnel effects.

A. Direct Tunneling effect (DT)

For nanocrystal memories, the control-gate coupling ratio of nanocrystal memory devices is inherently small [2.4]. As a result, FN tunneling cannot serve as an efficient write/erase mechanism when a relatively thin tunnel oxide is used because the strong electric field cannot be confined in one oxide layer. When the thickness of tunnel oxide is below 5 nm, the direct tunneling is employed in nanocrystal memories instead. Furthermore, the direct tunneling is more sensitive to the barrier width than barrier height. However, two to four orders of magnitude reduction in leakage current can still be achieved if the metals with a large work function, such as Au or Pt, which corresponding to high barrier height , [2.5].

B. Fowler–Nordheim Tunneling effect (FN)

One of most important injection mechanism employed in floating gate devices is the Fowler—Nordheim tunneling, which is a field—assisted electron tunneling mechanism. Electrons in the silicon conduction band see a triangular energy barrier with a width dependent on the applied field. The height of the potential barrier is determined by the electrode material and band structure of SiO2. At sufficiently high

field, the energy band diagram of the SiO2 is very steep and thin enough to allow that

the electrons can tunnel into the conduction band of SiO2. Using a free-electron gas

model for the metal and the WKB approximation for the tunneling probability [2.6], one obtains the following expression for current density [2.7]:

21  ⎥ ⎥ ⎦ ⎤ ⎢ ⎢ ⎣ ⎡_{− Φ} Φ = ∗ qF m h F q J OX B B 3h ) 2 ( 4 exp 16 2 3 2 1 2 2 2 3 π (2-3)

where ΦB is the barrier height, m* is the effective mass of the electron in the forbidden

gap of the dielectric, h and h is the Planck’s constant and the constant divided by 2π, q is the electronic charge, and F is the electric field through the oxide. However, the exponential dependence of tunnel current on the oxide-electrical field causes some critical problems on device process control because, for example, a very small variation of oxide thickness among the cells in a memory array produces a great difference in programming or erasing currents, thus spreading the threshold voltage distribution in both logical states.

C. Modified Fowler-Nordheim tunneling (MFN)

Modified Fowler–Nordheim tunneling (MFN) is frequently observed in SONOS-type memories where the operation is designated to low-voltage (<10V, depending on the Equivalent oxide thickness). A relatively small electric field on tunnel oxide cannot drive charges to inject into the charging trapping layer by DT or FN mechanism. Therefore, the electrons in conduction of the gate should tunnel through the oxide barrier and a triangular nitride barrier, which is MFN tunneling.

D. Trap assistant tunneling effect (TAT)

The charge storage mediums with many traps may cause another tunneling mechanism. For example, the charges tunnel through a thin oxide and arrive to the traps of nitride layer at very low electric field in SONOS systems. During trap assisted injection, the traps are emptied with a smaller time constant and then they are filled. The charge carriers are thus injected at the same distance into the nitride as for MFN injection. Because of the sufficient injection current, trap assistant tunneling

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may influence in retention [2.8].

2.1.2. Channel Hot-Electron Injection

The physical mechanism of Channel Hot-Electron Injection (CHEI) can be simply understood qualitatively. An electron traveling from the source to the drain gains energy from the lateral electric field and loses energy to the lattice vibrations (acoustic and optical phonons). At low fields, this is a dynamic equilibrium condition, which holds until the field strength reaches approximately 100kV/cm [2.9]. For fields exceeding this value, electrons are no longer in equilibrium with the lattice, and their energy relative to the conduction band edge begins to increase. Electrons are “heated” by the high lateral electric field, and a small fraction of them have enough energy to surmount the barrier between oxide and silicon conduction band edges. Figure 2-4 shows schematic representation of CHEI in n-MOSFET. On the other hand, the effective mass of hole is heavier than one of electron. It is too hard to obtain enough energy to surmount oxide barrier. Therefore, hot-hole injection is rarely employed in nonvolatile memory operation. For an electron to overcome this potential barrier, three conditions must be held [2.10].

1) Its kinetic energy must be higher than the potential barrier. 2) It must be directed toward the barrier.

3) The field in the oxide should be collecting it.

Nevertheless, a description of the injection conditions can be accomplished with two different approaches. The CHEI current is often explained and simulated following the “lucky electron” model [2.11]. This model is based on the probability of an electron’s being lucky enough to travel ballistically in the field for a distance several times the mean free path without scattering, eventually acquiring enough energy to cross the potential barrier if a collision pushes it toward the Si/SiO2 interface.

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Consequently, the probability of injection is the lumped probability of the following events, which are depicted in Figure 2-5 [2.12].

1) The carrier has to be “lucky” enough to acquire enough energy from the lateral electric field to overcome the oxide barrier and to retain its energy after the collision that redirects the electron toward the interface (PΦb).

2) The carrier follows a collision-free path from the redirection point to the interface (PED).

3) The carrier can surmount the repulsive oxide field at the injection point, due to the Schottky barrier lowering effect, without suffering an energy-robbing collision in the oxide (Poc).

The current density of CHEI is expressed as

(

_{b m}

)

b m ds d inj E E I A I ϕ λ ϕ λ ₋ = ( )2exp _(2-4) Here Ids is the channel current and Ad is a constant. φb is the injection barrier and λ is

the mean free path associated with the phonon scattering. Em is the lateral electric

field at drain.

2.1.3. Band to Band Tunneling (BTBT)

Band to band tunneling application to nonvolatile memory was first proposed in 1989. Chen et al. demonstrated a high injection efficiency (~1%) method to programming EPROM devices [2.13]. Band-to-band Tunneling (BTBT) process occurs in the deeply depleted doped surface region under the gate to drain / gate to source overlap region. In this condition, the band-to-band tunneling current density is expressed as

(

b m

)

b m ds d inj E E I A I ϕ λ ϕ λ − = ( )2exp _(2-5)

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This injection mechanism is used to nonvolatile memory of PMOS structure. When band-bending is higher than the energy gap of the semiconductor, the tunneling electron from the valence band to the conduction band becomes significant. The mechanism is at the condition for positive gate voltage and negative drain voltage. Hence, the hot electrons are injected through the tunnel oxide and then recombine the stored electrons as shown in Fig. 2-6.

(b) Band to Band Hot Hole Tunneling Injection

The injection is applied for NMOS nonvolatile memory device. The mechanism is at the condition for negative gate voltage and positive drain voltage. Hence, the hot holes are injected through the tunnel oxide and then recombine the stored electrons as shown in Fig. 2-7.

The electrons (n-type) / holes (p-type) are accelerated by a lateral electric field toward the channel region and some of the electrons with sufficient energy can surmount the potential barrier of SiO2 [2.14-2.16]. Due to the small oxide field, the

electron/hole influence through the oxide can easily reach hundreds of coulombs per square centimeter without failure, it means to the improvement reliability of memory cells.

2.1.4. Channel Initiated Secondary Electron Injection (CHISEI)

The main difference between CHE and CHISEI is that the CHISEI is operation as CHE with a negative bias on body (VB). The CHISEI is highly sensitive to the

lateral electrical field and vertical electrical filed. The procedure and the band diagram for the application of CHISEI are as shown in Fig. 2-8. The superior injection of CHISEI operation mode leads to a better program efficiency. The improved program efficiency results from the substrate enhanced gate current component. Under

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optimized substrate condition, the substrate hot carriers and subsequent injection are expected for the application of low power and high speed.

2.2 Basic Physical Characteristic of Nanocrystal Memory

In the nanocrystal memory, due to the small size of the nanocrystal (3~5 nm), the quantum effect will be obviously. Furthermore, storage carriers in nanocrystal can raise the potential energy due to Coulomb effect. Both quantum effect and Coulomb effect can influence the memory characteristics of the nonvolatile memory.

2.2.1 Quantum Confinement Effect

The quantum dot is a quasi-zero-dimensional nano-scale object and is also composed by small amount of atoms. The quantum confinement energy depended on nanocrystal size has been studied both experimentally and theoretically with the tight-binding model [2.17]. The quantum confinement effect becomes significant when the nanocrystal size shrinks to the nanometer range, which causes the ground state of nanocrystal to shift to higher energy compared with bulk material [2.18]. This result will reduce the barrier high, the difference between work function of the nanocrystal and tunnel oxide. The reduction of the barrier will degrade charge storage ability and programming efficiency for the semiconductor nanocrystals. The theoretical shift of ground state for semiconductor and metal nanocrystals has been proposed by W. Guan et al. at 2007 [2.19]. The ground state shift (∆E) of Ge and Mo nanocrystals are expressed as

688 . 0 788 . 1 39 . 1 ) ( E ₂ + + + ∞ = Δ Si Si Si d d E and 0.231₃ Mo Mo d E = Δ (2-6) Where E (∞) is the conduction band minimum for bulk Si and d is the diameter of nanocrystal. For example, a 3 nm Si nanocrystal can have a conduction band shift of 0.1 eV as compared with bulk Si, which is significant enough to affect the electrical

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performance of the nanocrystal memory cell. Figure 2-9 shows the conduction band minimum up-shift of Si and Ge nanocrystal, and Fermi level up-shift of metal NC as a function of nanocrystal size by W. Guan’s model.

2.2.2 Coulomb Blockade Effect

When an electron is stored in nanocrystal, the potential energy of nanocrystal raised with electrostatic charging energy e2/2Cnc, where Cnc is the nanocrystal

capacitance. The Cnc is dependent on nanocrystal size, permittivity and thickness of

surrounding dielectric, the tunnel oxide and the blocking oxide. The capacitance is self-consistently calculated using an electrodynamics method [2.20]. The electron charge will raise the nanocrystal potential energy and reduce the electric field across the tunnel oxide, resulting in reduction of the tunneling current density during the write process. It is more dominant at low programming voltages (< 3V). In a flash memory array, device cells often encounter disturbances with low gate voltage soft-programming. The Coulomb blockade effect can effectively inhibit the electron tunneling at low gate voltage and improve the flash memory array immunity to disturbance. However, the Coulomb blockade effect should be reduced by employing large nanocrystal if large tunneling current and fast programming speed were desired. The Coulomb blockade effect has a detrimental effect on the retention time because the electrons in the nanocrystal are inclined to back into the channel by tunneling if the nanocrystal potential energy is high in retention mode.

2.3 Reliability of Nonvolatile Memory

Unlike to logic IC, nonvolatile memory is more concerned with reliability than performance. The reliability includes two parts, retention and endurance. Both reliability tests are very importance for nonvolatile memory application to the