Chapter 1 Introduction
1.3. Organization of the Dissertation
The rests of the dissertation are organized as follows. Section II reviews the backgrounds of this dissertation. First, several effects of the nano-scaled devices are introduced. Challenges in low-voltage circuit design are discussed as well. Moreover, some reported low-voltage techniques are reviewed. Section III introduces the repeated-RC on-chip interconnect architecture. A bootstrapped inverter applied to a 0.2V clock network is developed. It also features an active leakage current reduction technique to save leakage power. Section IV introduces a low-voltage on-chip bus with an ISI-suppressed bootstrapped repeater. In order to achieve high energy-efficiency, Section V introduces high-boosting bootstrapped repeaters. In Section VI, we present a near-threshold ADPLL using a bootstrapped digitally-controlled oscillator (DCO). Finally, Section VII draws conclusions and future works.
Chapter 2
Background Review
In the past few decades, the scaling of CMOS technologies has been the major driving force of the trend of Moore’s Law. As scaling to nanometer technology, the process parameters are no longer scaled to a single scaling factor because the saturation of carrier velocity and the increasing sub-threshold leakage current become serious. With the continuing shrinking of the channel length and the gate-oxide thickness, some non-ideal effects appear to affect circuits.
Additionally, lowering the supply of nano-scaled designs to the near-threshold region has several detrimental impacts. In this chapter, the effects in nano-scaled near-threshold design are briefly reviewed. Subsequently, popular low-voltage design techniques shall be introduced as well.
2.1. Effects in Nano-scaled Process [6]
2.1.1. Short-Channel Effect
The short-channel effect (SCE) is occurred on a MOSFET device in which channel length is as the same order of magnitude as the depletion-layer widths of the source and drain junction.
The SCE is often modeled of charge sharing, where the source and drain depletion regions store the charge under the gate. The threshold voltage Vth of a MOSFET can be represented using depletion approximation as
2 B
th fb f
OX
V V Q
= + Φ +C (2.1)
where V is the flat-band voltage; fb Φ is the Fermi potential; f Q is the charge of channel ; and B COX is the oxide capacitance. While channel length is shrunk, the stored charges are reduced significantly in the doped area. As a result, threshold voltage is increased due to increasing channel length.
Fig. 2-1. Threshold voltage with change in channel length due to SCE [6].
Halo doping, which is a non-uniform channel doping in modern processes to adjust threshold voltage is so-called reverse short-channel effect (RSCE). The increasing of threshold voltage comes from extra doping charges near the source and drain regions. As the device's length is reduced, the threshold voltage of the device increases. The behavior is the opposite of what is expected from the SCE [7-8].
2.1.2. Narrow-Width Effect
The narrow-width effect (NWE) occurs when the threshold voltage Vth of a nano-scaled MOSFET is modulated by the gate width. Hence the device width modulates the drain current.
According to the Eq.(2.1), there are two main reasons to cause NWE. First, the charge in the gate-induced depletion region results an increase of threshold voltage. The second on is that channel doping is higher along the width dimension. Because dopants trespass under the gate, higher voltage is necessary to incur the channel inversion. Fig. 2-2 shows the NWE as a function of channel width.
Width
300n 500n 700n 900n
ID(nA)
Vth(mV) 290
270 20 30 40
Fig. 2-2. Threshold voltage with change in channel width due to NWE.
2.1.3. Sub-threshold Leakage [6, 9]
In a nano-scaled device, the sub-threshold (or weak inversion conduction) current Isub is happened with gate-source voltage below the threshold voltage Vth. Itcan be expressed as in Eq.(2.2).
2exp( GS th ) 1 exp( DS )
sub dep T
T T
V V V
I C WV
L nV V
μ − ⎛ − ⎞
= ⎜ − ⎟
⎝ ⎠. (2.2)
Where μ is the effective mobility; Cdep is the depletion capacitance; W and L are the width and length of the device; VT is the thermal voltage; VGS is the gate-to-source voltage; n is the sub-threshold slope factor, and VDS is the drain-to-source voltage.
As compared to the strong inversion region, the sub-threshold current is dominated by the diffusion current instead. The movement by the diffusion is likely to charge flowing in BJTs.
However, sub-threshold current is affected by other phenomenon, such as drain-induced barrier lowering (DIBL) and gate-induced drain leakage (GIDL). They are introduced in the following sections.
2.1.4. Drain-Induced Barrier Lowering [6]
-0.4 -0.2 0.0 0.2 0.4 0.6
10p 100p 1n 10n 100n 1μ 10μ 100μ
Drain current (Amp)
Gate voltage (Volt)
VDS = 0.1 V VDS = 0.2 V VDS = 0.3 V Conventional Ioff
@ VG= 0 V
VD↑
VD= VDD VG= - VDD
@25 C,TT Corner°
(DIBL)
(GIDL)
Fig. 2-3. Drain current of a NMOS device vs. VG in the near-threshold region.
In micron-scaled devices, the source and drain are separated far enough that no effect is incurred on the depletion regions. In such a case, the drain current is nearly independent of the channel length and drain bias. At the off conditions, the potential barrier between the source and
drain prevents electrons from flowing to the drain. In a short-channel device, the Vth varies with channel length according to the SCE. In addition, DIBL effect induces energy barrier lowering with increasing drain voltage [6]. When a short-channel device uses a higher drain voltage, the energy barrier decreases lower, resulting in further increasing the drain current. Fig. 2-3 depicts ID as a function of VG, which illustrates DIBL effect as the drain voltage increases. As shown in Fig. 2-1, DIBL effect lowers the threshold voltage, but remains the slope in the near-threshold region.
2.1.5. Gate-Induced Drain Leakage [6, 10]
Gate-induced drain leakage (GIDL) occurs in the drain junction owing to high field effect in the drain junction of an MOSFET. It usually happens when the electric field in or around the gated PN junction becomes more substantial with the applied gate voltage. The high-field effects, like avalanche multiplication and band-to-band tunneling (BTBT), become severely. Thus, the leakage current of a reverse-biased gated diode may increase dramatically when the negative gate voltage begins to cause field crowding and peak field. In order to suppress GIDL, thicker oxide and lower electric field might be used. Besides, very high drain doping is considerable for minimizing GIDL as well. Figure 2-3 also shows the GIDL according to drain current characters of a NMOS device with different drain voltage.
2.1.6. Gate Leakage [11]
In nanometer technology, the process parameters as the gate oxide layer thickness TOX has been scaled to the values in the range of 12–22Å. As mentioned, DIBL also incurs in the presence of large gate tunneling leakage current Igate. Igate increases due to the finite probability of an electron tunneling through the SiO2 layer directly. The probability is a strong exponential function of TOX. Only a difference of 2Å TOX thinner may increase an order of magnitude.
Therefore, it becomes the most sensitive parameter with respect to any physical dimensions.
Typically, Igate is much smaller than sub-threshold leakage current Isub, while TOX is large than 20Å. In simulation level, BSIM4 model (level =54) includes nano-scaled effects such as GIDL and DIBL. In addition, Igate has taken into account as well. For fast simulation and reliable purposes some models of gate leakage current are reported.
2.2. Challenges in Ultra Low-voltage Designs 2.2.1. Degradation of Driving Capability
When a MOSFET device is operated in the super-Vth region, the drain current operated in the saturation region is a function of the gate voltage. It can be represented as Eq.(2.3).
( )
2
, ( ) 1
D Sat ox GS th DS
I C W V V V
μ L λ
= − + . (2.3)
Where Cox is the gate oxide capacitance per unit area; and λ is the factor for channel-length modulation. According to Eq.(2.3), drain current ID,Sat decreases quadratically when the gate voltage goes lowering. When the gate voltage keeps going lower into the sub-threshold region, the drain current starts to decrease exponentially, as shown in Eq.(2.2). That is to say, when our design is operated in near-threshold region, poor driving is the first design issue. In normal 1V designs, sizing is a way that we often use to increasing driving. However, gate capacitance of a MOS device drops very slightly when the gate drive lowers to nearly threshold voltage. As a result, enlarging device size to enhance driving capability seems not a good idea in the near-threshold region.
2.2.2. Leakage Power and I
on-to-I
offRatio [8, 12]
Ion-to-Ioff ratio becomes a critical factor in near-threshold digital circuits and near-threshold circuits. The inherently small Ion-to-Ioff ratio dominates how many transistors can be connected per node. As reported in [12], the degradation in Ion-to-Ioff is from approximately 107 to 104 and it implies that there is a strong interaction between the ON and the OFF devices in sub-threshold region when it comes to setting the voltage level of critical signals. Unfortunately, this causes a relevant failure mechanism in circuit operation. As illustrated in Fig. 2-4, an inverter is served as a driver with a capacitive load of 200 fF while VDD is being swept from 0.1–0.3V. The circuit is operated to the limit of the speed. Obviously, the leakage power becomes a greater portion of the total power consumption while VDD keeps going lower.
0.10 0.15 0.20 0.25 0.30 0.0
3.0n 6.0n 9.0n 12.0n 15.0n
Supply voltage (Volt)
Conventional Conventional
0 10 20 30 40 50
Pleakage/ PT(%) Pleakage(Watt)
@25 C,TT Corner°
Pleakage Pleakage/ PT(%) 0.2pF
; ;
W 320nm W 460nm m=50
L n 60nm L p 60nm
⎛ ⎞ = ⎛ ⎞ =
⎜ ⎟ ⎜ ⎟
⎝ ⎠ ⎝ ⎠
Fig. 2-4. Leakage power on a repeater at subthreshold supply.
2.2.3. Process, Voltage and Temperature Variation
Process, voltage and temperature (PVT) corners induced performance variation makes the circuits design in near-threshold region tremendously challenging. First of all, process variability affects current due to some process parameters, such as mobility and threshold voltage. Even a small variation may lead to exponentially mismatch. The process variation is divided into two major categories [13]. Besides, it is classified into more specific categories, according to their physical range on a wafer or on a die [14]. Fig. 2-5 depicts ID as a function of gate voltage in the near-threshold region, which illustrates process and voltage effect at room temperature. It shows that the variation of ID becomes worse due to the process and voltage fluctuation as the supply voltage goes lower.
Apart from the static term of the process variation after a fabricated die, voltage supply variation is related to the fluctuations during the circuits operations. Real-time fluctuations caused by a voltage drop or inductance effect in wire may result in function failure [14-15]. The impact of temperature is another important factor to the variation and reliability in a nano-scaled chip, especially the supply voltage down to the near-threshold region. The sub-threshold current is highly depending on the temperature owing to the parameter VT. In contrast to the current in the super-threshold region, ID increases as the temperature is raised. The measured temperature sensitivity of the threshold voltage is about 0.8 mV/°C [6].
-0.4 -0.2 0.0 0.2 0.4 0.6 0.8 1.0 1p
10p 100p 1n 10n 100n 1μ 10μ 100μ
Drain current (Amp)
Gate voltage (Volt) FF
TT SS
IDmin, SS IDmin, TT IDmin, FF
°
@25 C
Fig. 2-5. Drain current in different corners in the near-threshold region.
2.3. Low-voltage Design Techniques
As mentioned, circuit design in the near-threshold region has many challenges. Several techniques have been reported to solve the problems or improve energy efficiency. They are briefly reviewed in the following sections.
2.3.1. Bootstrap Techniques
Bootstrapping is an effective means of enhancing the speed in order to raise the driving efficiency. Therefore, a previous work has developed a bootstrapped CMOS driver for large capacitive loads, shown if Fig. 2-6 [16]. According to [16], the bootstrapped driver consists of a pull-up and pull-down control pair to drive the PMOS and NMOS transistors, respectively. The gate voltages of PMOS and NMOS driver transistors are kept VDD and 0 in the cut-off phase. In the driving phase, the gate voltages are fed -VDD and 2VDD to increase the current density. When the input Vin is at 0 V, the Va is at VDD and the output of the inverter is at VDD. Moreover, MN2
and MN1b are off; MP2 and MP1b are on. Therefore, V2P is pre-charge to 0 V by MN2b, and bootstrap capacitor Cbp stores a potential of VDD. When the Vin transits from 0 V to VDD (from L to H), V2P is boosted from 0 V to -VDD. Then, the potential of a -VDD is passed from V2P to V1P. Consequently, the potential of a -VDD is at the gate of the driver MP2, which drives Vout by VSG
=2VDD. As Vin transits from H to L, a similar mechanism pushes V1N to –VDD.
Fig.2-6 Reported bootstrapped driver in [16].
The driver in [16] successful enhances the driving capability by boosting the gate voltage, which is suitable using in the near-threshold supply as well. However, there are several drawbacks such as reverse leakage current or non-ideal transient edge. Some researchers have proposed some improvements based on [16]. Among them, Kil et al. proposed a sub-threshold bootstrapped repeater in a 9MHz distributed clock network at 0.4V [17]. The sub-threshold bootstrapped repeater is depicted in Fig. 2-7, which is composed of two bootstrap circuits. One is for pre-boosting, and the other is for driving. The circuit of per-boosting enhances the pre-charge current to increase the speed. In addition, MPS2 and MNS2 are switches that can feed the boosted signal back to eliminate the reverse current. However, while this approach is applied to a data link, the kick-back disturbance through the boosting capacitors causes a large timing jitter.
Furthermore, it consumes large static power and is associated with high capacitor costs.
Fig. 2-7 Reported bootstrapped driver in [17].
2.3.2. Dynamic Voltage and Frequency Scaling
Dynamic Voltage and Frequency Scaling (DVFS) is a popular power saving scheme since it is broadly used in microprocessor and DSP ASICs [18]. Since different functions need different execution times, supply voltage or the data rate can be dynamically changed to meet the specification requirements in DVFS system; hence, the power consumption can be optimized for the computational tasks conditionally.
On the other hand, DVFS scheme also applied to lower the operating frequency in portable products when battery goes low. DVFS is able to keep system working on basic functions in order to extend the battery lifetime or stand-by time. DVFS scheme is applied to adjust PVT variation as well [19]. In fact, such designs often remain large redundant margin in particle chip.
DVFS determines the supply voltage or the frequency for the task appropriately and dynamically and therefore exceeds most power efficient.
Critical Path Monitors (CPMs) [18, 20-21] a sub-module of these worst-case margins by using a delay-chain which is replica of the critical path of the actual design. The propagation delay through this replica-path is monitored and voltage and frequency are scaled until the replica-path just meets timing. The replica-path tracks the critical-path delay across inter-die
process variations and global fluctuations on supply voltage and temperature, thereby eliminating margins due to global PVT variations.
2.3.3. Multi-threshold MOS Control
Since the circuits operate in the near-threshold region, lowering the supply voltage decreases ID according to equations (2.2) and (2.3). It results in a drastic rising in gate delay time.
In order to overcome the speed degradation problem, one way is to reduce the Vth of a MOSFET device [22-23]. As Vth is reduced, however, another significant problem incurs. A rapid increase in stand-by current due to changes in the sub-threshold leakage current damages the power performance. To save stand-by power during the sleeping mode, a power management scheme combined small embedded processor and multi-threshold sleep control is reported in [24]. It utilizes high Vth MOSFET devices, resulting in low standby and dynamic power.
2.3.4. Bulk-driven Technique
Similar to multi-threshold MOS control, the bulk-driven technique is using circuit techniques to shift Vth lower or higher by biasing bulk voltage. Sometime, the bulk-driven technique is called “adaptive body-biasing” as well [25]. Some contributed works based on the bulk-driven technique are reported in [26-27]. The threshold voltage can be expressed as in Eq.(2.4) [28].
0 2 2
th th F SB F
V =V −γ ⎡⎣ φ −V − φ ⎤⎦ . (2.4)
It is the well-known equation relating how the body voltage affects the threshold voltage, where γ is the body effect coefficient. The bulk-driven technique has several important features. To enhance the driving capability by modulate the Vth is the obvious one. The most important feature is that it can allow zero, negative, and even small positive bias voltages to achieve the desired DC currents such that it has a good alternative to increase the input common-mode voltage range. In normal circuit design, the bulk terminals of PMOS (NMOS) is always connected to the highest (lowest) potential to avoid the latch-up problem from junction forward biasing of the bulk–source.
2.4. Summary
In this chapter, several backgrounds of the dissertation have been briefly reviewed. Since some non-ideal effects owing to the shrinking of the channel length and the gate-oxide thickness,
current variation caused by environment makes circuit designs more challenging. Additionally, nano-scaled circuits design using near-threshold supply has several detrimental impacts.
Trade-off between performance and energy efficiency should be carefully dealt with. Last part of this chapter, some popular low-voltage design techniques have been introduced as well. Based on the concept of the bootstrap technique, we will develop several bootstrap circuits in the following chapters.
Chapter 3
Near-threshold Clock Network
A driver with strong driving current and little skew is needed in a clock network. According to Fig. 3-1(a), the conventional bootstrapped driver consists of a pull-up and pull-down control pair to drive the PMOS and NMOS transistors, respectively. As mentioned in chapter 2, the gate voltages of PMOS and NMOS driver transistors are kept VDD and 0 in the cut-off phase; they are fed -VDD and 2VDD to increase the current density in the driving phase. Despite a previous effort [35] to increase the boosting efficiency by rearranging the timing of the switching and boosting signals, reverse leakage current remains the main drawback of conventional bootstrapped drivers.
Among other bootstrapped circuits, single capacitor ones reduce the costs of hardware overhead [36-37]. However, their complex circuitry design seriously degrades charge sharing at the capacitor node. Moreover, the leakage current is problematic as well.
(a) (b)
Fig. 3-1.(a) Conventional bootstrapped circuit (b) Proposed bootstrapped circuit.
In this chapter, we present a sub-threshold clock network with a bootstrapped CMOS inverter operated at sub-threshold power supply. The bootstrapped CMOS inverter is introduced to achieve high boosting efficiency and improve the speed. It is applicable in both increasing driving ability by boosting signals into super-threshold region and reducing the leakage current as well. Fig. 3-1(b) illustrates the circuit diagram. Theoretically, the PN bootstrap circuit produces an output swing of -VDD to 2VDD. 2VDD (-VDD) enhances the driving capability of NMOS (PMOS) driver and suppresses the leakage for the PMOS (NMOS). The PN bootstrap circuit provides VSG (VGS) = 2VDD and turns on the PMOS (NMOS) driver. In contrast, a
negative VSG (VGS) = -VDD suppresses leakage current while the PMOS (NMOS) driver is turned off. Moreover, as compared to other previous works, the proposed design scheme has fewer devices in the sub-threshold region. Consequently, that explain why the process variation affects the proposed design scheme to a lesser extent.
3.1. Overview of On-chip Interconnect
Before introducing the proposed bootstrapped CMOS inverter, the fundamental of interconnect is briefly reviewed. First of all, interconnect and repeater linear model is adopted according to VLSI parameters scaling in this section. In addition, the definitions of speed and power consumption of the on-chip interconnect circuits are described. All these parameters introduced from linear models to define figure of merit (FoM), the index for optimal global on-chip interconnect design.
3.1.1. RC-Interconnect with Repeater Insertion
Top Metal
Bottom Metal
Fig. 3-2. Cross section of interconnect configurations.
In general, a global interconnect is assumed to be placed between two adjacent orthogonal metal layers and two coplanar wires, as shown in Fig. 3-2, where W and S are the interconnect
In general, a global interconnect is assumed to be placed between two adjacent orthogonal metal layers and two coplanar wires, as shown in Fig. 3-2, where W and S are the interconnect