Chapter 2 Background Review
2.1. Effects in Nano-scaled Process [6]
2.1.1. Short-Channel Effect
The short-channel effect (SCE) is occurred on a MOSFET device in which channel length is as the same order of magnitude as the depletion-layer widths of the source and drain junction.
The SCE is often modeled of charge sharing, where the source and drain depletion regions store the charge under the gate. The threshold voltage Vth of a MOSFET can be represented using depletion approximation as
2 B
th fb f
OX
V V Q
= + Φ +C (2.1)
where V is the flat-band voltage; fb Φ is the Fermi potential; f Q is the charge of channel ; and B COX is the oxide capacitance. While channel length is shrunk, the stored charges are reduced significantly in the doped area. As a result, threshold voltage is increased due to increasing channel length.
Fig. 2-1. Threshold voltage with change in channel length due to SCE [6].
Halo doping, which is a non-uniform channel doping in modern processes to adjust threshold voltage is so-called reverse short-channel effect (RSCE). The increasing of threshold voltage comes from extra doping charges near the source and drain regions. As the device's length is reduced, the threshold voltage of the device increases. The behavior is the opposite of what is expected from the SCE [7-8].
2.1.2. Narrow-Width Effect
The narrow-width effect (NWE) occurs when the threshold voltage Vth of a nano-scaled MOSFET is modulated by the gate width. Hence the device width modulates the drain current.
According to the Eq.(2.1), there are two main reasons to cause NWE. First, the charge in the gate-induced depletion region results an increase of threshold voltage. The second on is that channel doping is higher along the width dimension. Because dopants trespass under the gate, higher voltage is necessary to incur the channel inversion. Fig. 2-2 shows the NWE as a function of channel width.
Width
300n 500n 700n 900n
ID(nA)
Vth(mV) 290
270 20 30 40
Fig. 2-2. Threshold voltage with change in channel width due to NWE.
2.1.3. Sub-threshold Leakage [6, 9]
In a nano-scaled device, the sub-threshold (or weak inversion conduction) current Isub is happened with gate-source voltage below the threshold voltage Vth. Itcan be expressed as in Eq.(2.2).
2exp( GS th ) 1 exp( DS )
sub dep T
T T
V V V
I C WV
L nV V
μ − ⎛ − ⎞
= ⎜ − ⎟
⎝ ⎠. (2.2)
Where μ is the effective mobility; Cdep is the depletion capacitance; W and L are the width and length of the device; VT is the thermal voltage; VGS is the gate-to-source voltage; n is the sub-threshold slope factor, and VDS is the drain-to-source voltage.
As compared to the strong inversion region, the sub-threshold current is dominated by the diffusion current instead. The movement by the diffusion is likely to charge flowing in BJTs.
However, sub-threshold current is affected by other phenomenon, such as drain-induced barrier lowering (DIBL) and gate-induced drain leakage (GIDL). They are introduced in the following sections.
2.1.4. Drain-Induced Barrier Lowering [6]
-0.4 -0.2 0.0 0.2 0.4 0.6
10p 100p 1n 10n 100n 1μ 10μ 100μ
Drain current (Amp)
Gate voltage (Volt)
VDS = 0.1 V VDS = 0.2 V VDS = 0.3 V Conventional Ioff
@ VG= 0 V
VD↑
VD= VDD VG= - VDD
@25 C,TT Corner°
(DIBL)
(GIDL)
Fig. 2-3. Drain current of a NMOS device vs. VG in the near-threshold region.
In micron-scaled devices, the source and drain are separated far enough that no effect is incurred on the depletion regions. In such a case, the drain current is nearly independent of the channel length and drain bias. At the off conditions, the potential barrier between the source and
drain prevents electrons from flowing to the drain. In a short-channel device, the Vth varies with channel length according to the SCE. In addition, DIBL effect induces energy barrier lowering with increasing drain voltage [6]. When a short-channel device uses a higher drain voltage, the energy barrier decreases lower, resulting in further increasing the drain current. Fig. 2-3 depicts ID as a function of VG, which illustrates DIBL effect as the drain voltage increases. As shown in Fig. 2-1, DIBL effect lowers the threshold voltage, but remains the slope in the near-threshold region.
2.1.5. Gate-Induced Drain Leakage [6, 10]
Gate-induced drain leakage (GIDL) occurs in the drain junction owing to high field effect in the drain junction of an MOSFET. It usually happens when the electric field in or around the gated PN junction becomes more substantial with the applied gate voltage. The high-field effects, like avalanche multiplication and band-to-band tunneling (BTBT), become severely. Thus, the leakage current of a reverse-biased gated diode may increase dramatically when the negative gate voltage begins to cause field crowding and peak field. In order to suppress GIDL, thicker oxide and lower electric field might be used. Besides, very high drain doping is considerable for minimizing GIDL as well. Figure 2-3 also shows the GIDL according to drain current characters of a NMOS device with different drain voltage.
2.1.6. Gate Leakage [11]
In nanometer technology, the process parameters as the gate oxide layer thickness TOX has been scaled to the values in the range of 12–22Å. As mentioned, DIBL also incurs in the presence of large gate tunneling leakage current Igate. Igate increases due to the finite probability of an electron tunneling through the SiO2 layer directly. The probability is a strong exponential function of TOX. Only a difference of 2Å TOX thinner may increase an order of magnitude.
Therefore, it becomes the most sensitive parameter with respect to any physical dimensions.
Typically, Igate is much smaller than sub-threshold leakage current Isub, while TOX is large than 20Å. In simulation level, BSIM4 model (level =54) includes nano-scaled effects such as GIDL and DIBL. In addition, Igate has taken into account as well. For fast simulation and reliable purposes some models of gate leakage current are reported.