Organization of the Thesis - 三維積體電路關鍵技術於先進背照式感光元件應用之研究

Chapter 1 Introduction

1.3 Organization of the Thesis

In Chapter 2, the major characteristics of all instruments which are used in this thesis will be literally introduced.

In Chapter 3, we measure the Cu/Sn to Cu/Sn bump bonding electrical characteristics including Kelvin structure and daisy chain. In addition, we also work on the reliability tests about current stressing and thermal cycling test.

In Chapter 4, we develop the procedure to do Cu/Ni/Sn bonding and wafer thinning.

In Chapter 5, after the studies of Cu/Ni/Sn bonding and wafer thinning, we investigate the polymer bonding. The property of polyimide, various bonding conditions and bonding mechanism are included in this thesis.

In Chapter 6, we will give a conclusion for this thesis and some suggestions.

The future work for this study will be mentioned as well.

(Fairchild) Figure 1-1 Roadmap of Semiconductor

Figure 1-2 Concept and Fabrication of 3DIC [2]

(Zycube, MNCN) Figure 1-3 3D-IC Technology Integrate Different Function Chips by

Heterogeneous Stack

(Yole Développement, 2007) Figure 1-4 Development of 3D IC Scheme

(Sony, 2008) Figure 1-5 Comparison between FSI-CIS and BSI-CIS

Figure 1-6 Comparison between (a) C4 Solder Interconnect and (b) Low-Volume Lead-Free Solder Interconnect [4]

Figure 1-7 Hybrid Bonding Chip

Table 1-1 Classification of 3D IC Processes and Integration Techniques

Category Detail terms

Stacking approaches

Chapter 2 Experimental Instruments

2.1 Introduction

In this chapter, some of the equipment instruments are been described. They play an important role in our research. It is divided into three parts: process instruments, material analysis instruments and reliability test instrument.

All the samples studied in this work are prepared in Nano Facility Center (NFC), Center for Nanotechnology, Materials Science, and Microsystems (CNMM) and National Nano Device Laboratories (NDL).

The material analysis conducts in Material Analysis Technology (MA-tek), Integrated Service Technology (iST) and Center of Nanoscience and Technology in NCTU. Material analysis and microscope instruments are used to let us understand the related and the corresponding properties of the process condition.

Scanning electron microscopy (SEM), scanning acoustic tomography (SAT) and the Fourier-transform infrared spectrometer (FTIR) are used. All the instruments will be introduced as follows.

2.2 Process Instruments

2.2.1 Oxford Plasma Enhanced Chemical Vapor Deposition

System

Plasma enhanced chemical vapor deposition (PECVD) is usually used for the thin film deposition, and make material source change from gas state into plasma state to accelerate chemical reactions. The outlook of PECVD shows at Figure 2-1.

The plasma is filled by process gases and generated by two electrodes which are biased with RF signal or DC signal. Processing plasmas are usually operated at the pressures of a few mTorr to a few Torr, so the atoms and ions can reach enough mean free path. Ionized atoms or molecules are accelerated towards or leave the neighboring surface in sheath region (depends on their charges); therefore, all surfaces exposed to the plasma receive ion bombardment. The potential across the sheath layer is typically 10–20 V. The sheath layer is naturally generated because those electrons move faster than atoms or molecules, and can produce much higher sheath potential by modified reactor geometry. Ion bombardment leads to increases in density of the film and removes contaminants that cover the sample surface to improve the film quality. Ion bombardment density can be high enough to do thin film planarization. Silicon dioxide can be deposited by using different

silicon precursor gasses like dichlorosilane or silane and oxygen precursors.

Silicon nitride can be formed by using silane and nitrogen or ammonia. Silicon dioxide can also be deposited from a tetra-ethyl-ortho-silicate (TEOS) silicon precursor in oxygen or oxygen-argon plasma. Silicon dioxide deposited by high-density plasma can create a nearly hydrogen-free film with good conformity.

2.2.2 Sputter

Ion Tech Microvac 450CB was used for depositing metal materials. The outlook of sputter shows at Figure 2-2.The sputtering system is composed of: (1) Sputtering chamber (2) vacuum pumps, consisting of one cryo pump and

mechanical pump (3) DC power (4) 4-inch magnetron gun (5) gas flow meter (6) pressure gauges (7) film thickness monitor. The 4-inch or 6-inch Si substrates are placed in the spin holder driven by a motor. The targets (metals such as Cu, Ti, Fe, etc.) are 4-inch. The DC source can provide power up to 200 W. Normally the base pressure is around 3.0 × 10^-6 torr and the working pressure is around 7.6 mtorr. The flow rate of Ar is around 24 sccm. The sputtering DC source is kept at 160W for our experiments.

Its basic principle is physical vapor deposition. PVD is driven by

momentum exchange between the ions and atoms in the materials. The incident ions set off collision cascades in the target. When such cascades recoil and reach

the target surface with energy higher than the surface binding energy, an atom can be ejected out of the target surface.

2.2.3 Flip Chip Bonder

This multipurpose bonding platform FINEPLACER Pico MA for advanced assembly can process bonding step with 5 μm accuracy shown at Figure 2-3. And it has high magnification to do alignment procedure. Advanced device packaging like assembly of MEMS, sensors, RFID, embedded components and surface mount photonics can be completed with this bonder. Also, it can execute precise die attach, flip chip bonding, LED bonding and chip to wafer (6”) bonding. Some high technologies have been adopted on this instrument such as thermo compression, thermo sonic, ultrasonic bonding, soldering (AuSn, C4, Indium), face-up/face-down assembly, flip chip on flex, chip on glass (CoG) and adhesive technologies (ACF/ACP/NCP). Some features are spotlighted like vision alignment system ensures placement accuracy within 5μm, larger field of view and working area (6”), shifting module for bigger chip sizes, quick and easy setup of new applications, manual & motorized configuration available, hands-off operation in motorized configuration, high resolution video optics with fiber optic lighting, process observation and monitoring and independent substrate handling without tool change. Its software “WinFlipChip” can do advanced process

recording and reporting functions, control of all connected process modules, advanced force control, drag & drop function to adjust profiles, options to capture pictures and graphical user interface. The picture and schematic of the bonder are shown in Figure 2-3 and Figure 2-4 [9].

The alignment method of this bonder is type 3 inter-substrate microscopes, with two set of microscopes capturing the image of top and bottom bonding samples.

The spec of the bonder is as follows:

 Placement accuracy 5 μm

 Components from 0.125 mm × 0.125 mm to 100 mm × 100 mm

 Working area up to 450 mm × 234 mm

 Supporting wafer/substrate sizes up to 8"

 Supporting bonding force up to 100 N

 Can be configured as a hot air rework system

 Manual and semi-automatic configurations

2.2.4 EVG520HE

The EVG520HE is a thermo-compression bonding tool shown at Figure 2-5;

the theory of thermo-compress bonding is using pressure and heat to make the contact area between these two wafers distort slightly to increase contact area. At a certain temperature that is high enough at the wafer surface, these wafers will

diffuse between each other to make the bonding process complete. This method does not require strict surface cleaning and high vacuum condition.

Because thermo-compression bonding process is simpler and less cost, it is more attractive to industry and academic circle. The most important parameter in this method is temperature. Wafer level bonding is used at 3D-IC device and application, so the bonding temperature should be compatible with BEOL (back-end-of-line) to avoid influencing device performance and reliability.

EVG520HE is a single chamber tool that the maximum size of processed wafer is 4 inch. Besides, it can handle 2 × 2 cm² chip. It is a semi-automatic tool that can heat or cool upper and bottom wafer at the same time. And EVG520HE has individual ramp system to provide different process temperature to upper and bottom wafer. The maximum process temperature is 350℃, besides, it can provide compression force up to 12000Nt for 4 inch wafer to enhance bonding and does not require vacuum environment to do bonding process.

2.3 Material Analysis Instruments

2.3.1 Scanning Electron Microscopy Hitachi S-4700I

SEM provides a convenient way to inspect the surface morphology and the cross section image of the critical layer. The outlook of SEM shows at Figure 2-6.

We need to coat a thin Pt layer on the samples to enhance conductivity and get a high quality image before sending the samples into the chamber. The accelerated electron beam is emitted from a cold-cathode electron gun with the extract voltage ranging from 0.5 kV to 30 kV. The electron will collide with DUT, and the secondary electrons originate within a few nanometers from the surface of the DTU. The electrons are detected and rendered into a bright SEM image.

2.3.2 Scanning Acoustic Tomography

SAT is the abbreviation of Scanning Acoustic Tomography and it is also called SAM (Scanning Acoustic Microscope) shown at Figure 2-7. The SAT examinations were performed at frequency above 20 kHz, with a point to point resolution of 10 nm. The principle of detection of SAT is transmitting the ultrasonic to the sample, and analyzing the reflection and transmission of ultrasonic with software. By the software, we can check the line and layer inside the chip that cannot be seen by naked eye. In the SAT image, the dark region indicates good bonding interface without voids, whereas the white region represents the bonding interface with voids. During the SAT examination, the sample was placed in the water because the ultrasonic is very sensitive to air.

2.3.3 Fourier-Transform Infrared Spectrometer

When the molecular vibration occurs in the atoms, it will absorb a specific

energy, which will form IR spectrum. Unlike the ultraviolet or visible light, the IR cannot cause electronic transitions. The absorption of IR radiation would be limited in the molecule generally (Figure 2-8) [10]. Since each vibration or rotation of molecules has special energy, the specific wavelength will be absorbed. So we can understand the molecular structure by the IR spectrum.

We can use the interferometer to produce interference wave irradiated the samples, and then we can get the interference spectrum by Fourier transform.

The advantage is the measurement speed and sensitivity are more accurate and higher resolution. The FTIR can detect the wafer, film, liquid and solid sample and the FTIR spectrum can be divided into three types including reflection, transmission and absorption. In the three types of spectrum, the reflection spectrum can be divided into attenuated total reflection (ATR), diffuse reflection (DRIFT), 75° grazing incident angle reflectance and specular reflection (SR).

The FTIR consists of five units: optics module, electronic unit, water cooling unit, vacuum system and PC data station. The picture and schematic of the FTIR are shown in Figure 2-9

The spec of the FTIR is as follows:

 Range of measurement: 500~700 1/cm (1.43~20.00 μm)

 Sample size: 8 mm × 8 mm~20 mm × 20 mm

 Sample thickness: < 10 mm

At first, we need to measure the background sample before we measure the sample and let the spectrum of sample divided by the spectrum of background sample, and then we can get the spectrum. The FTIR can only detect the relative intensity, which it is not the quantity analysis.

2.4 Electrical Analysis Instrument

2.4.1 4156C

Agilent 4156C precision semiconductor analyzer is used to measure the electrical properties of the bonded structure. The 4156C provides highly accurate laboratory bench top parameter analyzers for advanced device characterization.

The superior low-current and low-voltage resolution and built-in quasi-static CV measurement capability of the 4156C provide a firm foundation for future expansion with other measurement instruments, as shown in Figure 2-10.

The 4284A precision LCR meter is a cost-effective solution for component and material measurement. The wide 20 Hz to 1 MHz test frequency range and superior test-signal performance allow the 4284A to test components to the most commonly-used test standards, such as IEC/MIL standards, and under conditions that simulate the intended application. Whether in research and development, production, quality assurance, or incoming inspection, the 4284A will meet all of your LCR meter test and measurement requirements.

2.5 Reliability Test Instrument

2.5.1 Pulling Force Tester 1220S

The Pulling Force Tester 1220S are used to measure the tensile. In this work, it is used to measure the bonding strength. Before the tensile test, the sample was stick to screw by thermosetting resin adhesive at 150℃ for 2 h as shown in Figure 2-11.

After the curing, the sample was set in the auto inserting pulling force tester. The picture and schematic of the pulling force tester are in Figure 2-12

The spec of the pulling force tester is as follows:

 Maximum measurement: 175 kgf

 Sample size: 1.5 cm × 1.5 cm

(National Nano Device Laboratories) Figure 2-1 Outlook of Plasma Enhanced Chemical Vapor Deposition

(Nano Facility Center) Figure 2-2 Outlook of Sputter

(Fine Tech) Figure 2-3Outlook of Flip Chip Bonder

Figure 2-4 Illustration of Different Alignment Methods [9]

(Center for Nanotechnology, Materials Science, and Microsystems) Figure 2-5 Outlook of EVG 520

(The University of California Riverside) Figure 2-6 Outlook of Scanning Electron Microscopy

(Hitachi FS300II, Japen) Figure 2-7 Outlook of Scanning Acoustic Tomography (SAT)

Figure 2-8 Range of FTIR Measurement [10]

(Center of Nanoscience and Technology) Figure 2-9 Outlook of Fourier-Transform Infrared Spectrometer

Figure 2-10 Four-probe measurement system

Figure 2-11 Setup before the Tensile Test and Samples after the Curing in the Tester before the Tensile Test

(SE TESTSYSTEMS CO, Taiwan) Figure 2-12 Outlook of Pulling Force Tester 1220S

Chapter 3 Reliability Investigation on Cu/Sn to Cu/Sn Bump Bonding

3.1 Introduction

Cu/Sn to Cu/Sn bump bonded interconnect is an important technology [13], which can be used in flip chip packaging process. It plays the role of connecting the image sensor and substrate, so the reliability is very important. In order to verify the capability of Cu/Sn to Cu/Sn bump bonded interconnect for commercial use and mass production, reliability investigation on Cu/Sn to Cu/Sn is strongly required.

In this chapter, the daisy chain and Kelvin structure of the Cu/Sn to Cu/Sn bump bonded interconnect was designed to verify electrical characterization and reliability assessment including: contact resistance measurement, AC current stressing test and thermal cycling test. Four-probe Agilent 4156C analyzer was adopted for electrical measurement. The electrical characteristics of the 3D integration scheme were evaluated through the bond chain structures, where a series of Cu/Sn bumps was included.

3.2 Experimental Procedure

In the integration scheme, daisy chain and Kelvin structures were designed in the test vehicle for investigation. Kelvin structure is a design to investigate the electrical property of contact resistance. Figure 3-1 (a) shows the cross section of Kelvin structure. Figure 3-1 (b) shows the measurement of Kelvin structure. Figure 3-1 (c) is the Kelvin structure. Daisy chain is a design to evaluate the stability of series number of bumps. Figure 3-2 (a) shows the cross section of daisy chain.

Figure 3-2 (b) shows the measurement of daisy chain. Figure 3-2 (c) is the daisy chain. To avoid loading effect on SMU and cable line, the method was modified and measured in four-probe SMU system. One current injection and outflow another SMU and then we measure delta V between two pads.

To evaluate the stability of bonded structure and electrical performance, the current cycling test was performed and the current sweeping range was -0.1 A to 0.1 A. To evaluate the thermal reliability of bonded structures, a temperature cycling test ranging from -55 °C to 125 °C was conducted and the demonstrations of the test were based on the JEDEC standard.

The resistance values of the samples were measured by 4-point measurement with Kelvin structure. The current stressing tests and thermal cycling tests were conducted on the Cu/Sn to Cu/Sn samples.

3.3 Results and Discussion

3.3.1 Contact Resistance Measurements

The contact resistance of Cu/Sn bump bonded interconnect was evaluated by

fabricating and measuring a Kelvin structure of a bonding area subjected to 1960 μm². We calculate the specific contact resistance of the bonded structure with the

following equation:

ρ

= R

× A

⁽¹⁾

In the equation (1),

ρ

^c is specific contact resistance,

R

cis contact resistance and

A

cis contact area. In this work, the specific contact resistance

ρ

^cis 1.24 × 10^-8Ω-cm², the result is shown in Figure 3-3.

3.3.2 Daisy Chain Measurements

Daisy chain is used for evaluating the stability of series number of bumps.

We measured the number of bumps: 0, 12 and 20. The resistance without bumps shows the resistance of the metal line, which can be used to remove the loading effect. As the Figure 3-4 illustrated, the resistance without bumps is Rs. In the Table 3-1, the Rs is 1.78 Ω, the resistance with 12 bumps is 0.44 Ω, and the resistance with 20 bumps is 0.7 Ω. So we can know the resistance of a bump is about 0.35 Ω. The result of measurement is shown in Figure 3-5.

3.3.3 Current Cycling Test

The stability of the bonding is significant for 3D integration applications, especially its electrical performance after multiple operations. Therefore, the current cycling tests of Cu/Sn bump bonded interconnect were evaluated. The AC current stressing test for 1000 cycle was applied to the Cu/Sn bump, with each cycling consisting of a current sweeping from -0.1 A to 0.1 A. The result of daisy chain is shown in Figure 3-6, and the result of Kelvin structure is shown in Figure 3-7. The result implies that the bonded structure is stable and it can also endure a long term electrical current.

3.3.4 Thermal Cycling Test

To evaluate the thermal reliability of bonded structures, a temperature cycling test for 1000 cycles and 2000 cycles was conducted. The test condition are ranging from -55 °C to 125 °C and ramp rate is 15 °C/min. The results of Kelvin structure were shown in Figure 3-8, and the specific contact resistances were shown in Figure 3-9. The resistance after thermal cycling test is more stable than initial. The results of daisy chain are shown in Figure 3-10, the resistance decreases from 2.48 Ω to 2.38 Ω. It may come from the improvement of bonded interface, like the grain growth and removal of defects.

Figure 3-1 (a) Cross Section (b) Measurement of Kelvin Structure (c) Structure of Kelvin Structure

Figure 3-2 (a) Cross Section (b) Measurement of Daisy Chain (c) Structure of Daisy Chain

Figure 3-3 Specific Contact Resistance of Kelvin Structure with Cu/Sn Bump Bonded

Figure 3-4 Equivalent Circuit in Our Structure

Figure 3-5 Resistance of Daisy Chain

Table 3-1 Resistance of the Daisy Chain

Number of bumps 0 12 20

Resistance (ohm) 1.78 2.22 2.48

Figure 3-6 AC Current Stressing of Daisy Chain (-0.1 A to 0.1 A)

Figure 3-7 AC Current Stressing of Kelvin Strucutre (-0.1 A to 0.1 A)

Figure 3-8 Contact Resistance after Thermal Cycling Test

Figure 3-9 Specific Contact Resistance of Thermal Cycling Test

Figure 3-10 Resistance of Daisy Chain of Thermal Cycling Test with 20 Bumps

Chapter 4 Investigation on Cu/Ni/Sn Bonding and Wafer Thinning Applied on Fabrication of BSI-CIS

4.1 Introduction

The BSI-CIS is the next generation image sensor since it has many advantages compare to front side illumination CMOS image sensor (FSI-CIS) [11-12], like reducing the noise signal beyond low illumination to lighten color distortion, enhancing the sensor current, lowering the effect of Young's

interference so that the sensor can further scale down and so on. However, process proposed by ITRI has to use the Cu/Sn bump, handling wafer and under-fill, which is shown in Figure 4-1. In addition, the Cu/Sn to Cu/Sn bump bonded interconnect has been widely used in package process. It needs a larger spacing between bumps. The spacing between bumps limits the scaling of the whole chip. To reach the application of sub-micron scale, reducing the Cu/Sn thickness

is necessary and important.

In this chapter, we design a new process flow of BSI-CIS. We use Cu/Ni/Sn to Cu/Ni/Sn bonding to accomplish the BSI-CIS testing structure with metal bonding and wafer thinning. In addition, we don’t use handling wafer in the whole process, the bonded substrate can be served as a support to avoid wafer bow, warpage and so on. Scanning electron microscope (SEM) was applied for the image and the Scanning Acoustic Tomography was used to inspect the bonding area uniformity.

4.2 Fabrication of BSI-CIS Testing Structure

P-type (100) 4-inch Si wafers were adopted in the study. The silicon dioxide with 3000 Å were deposited on bare silicon wafers after RCA clean (SPM + SC1 + SC2 + DHF) by furnace. The wafers would be divided into two parts.

One part of the wafers deposited poly-silicon with thickness of 1μm on silicon dioxide as device layer by LPCVD, and then deposited silicon dioxide with 3000 Å as isolation layer by PECVD. The Ti 100 Å, Cu 3000 Å, Ni 100 Å and Sn

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