Organization of the Thesis

There are five parts in this thesis. Chapter 1 is the introduction. We describe the motivation and organization of this thesis. In Chapter 2, we show the device preparation and equipment setup used in the experiments. In Chapter 3, we will examine the methods

Chapter 2

Device Preparation, Equipment Setup, and Measurement Methods

2.1 Device Preparation

The structure of RRAM is the TiN / TiO_x / HfO_x / TiN stack, which was deposited on the Ti / SiO2 / Si substrate. The HfO2 thin film was deposited by atomic layer deposition (ALD), while all the other thin films were deposited by sputtering methods.

Owing to the well-known ability of Ti to absorb oxygen atom [2.1], oxygen atoms diffuse from the HfO2 layer to the Ti, resulting in the formation of HfOx (x ~ 1.4) with a large amount of oxygen deficiency and the oxidation of Ti. The corresponding XTEM image, made by the XPS examination, is presented in Fig. 2.1 [2.2].

2.2 Equipment Setup

The whole experimental setup for the I-V and pulse characteristics measurement of RRAM is illustrated in Fig. 2.2. Based on the PC controlled instrument environment by HP-IB (GP-IB, IEEE-488 Standard) interface, the complicated and long-term characterization procedures to analyze the behaviors in RRAM cells can be easily achieved.

As shown in Fig. 2.2, the equipment, including the semiconductor parameter analyzer (Agilent 4156C), low leakage switch mainframe (HP 5250A Switching Matrix), pulse

devices. Programs written by HT-Basic were used to execute the measurement via HP-IB interface.

The Agilent 4156C provides a high current resolution up to pico-ampere range, and is equipped with four programmable source/monitor units. Two source units, and two monitor units for supplying or monitoring the voltage and the current. The pulse generator Agilent 81110A with high timing resolution provides for P/E cycling endurance. The HP 5250A switching matrix equipped with an 8-input x 12-output switching matrix switches the signals from the Agilent 4156C and Agilent 81110A to device under test in the probe station automatically.

2.3 Measurement Methods

2.3.1 Introduction

There are four measurement techniques used in this thesis. First, a forming process is required for every fresh device before normal operation. Second, normal operation using bipolar voltage sweep is necessary for basic device characterization. Third, the pulse with both positive and negative pulses causes the changes of RRAM devices to high/low resistance state. The last one is the sampling mode which helps us to read the RRAM devices resistance and sensing the Random Telegraph Noise (RTN) signal.

Before we start to operate the RRAM correctly, performing the so-called “forming”

procedure in the beginning is required, as shown in Fig. 2.3. We add a ramping voltage on the top TiN electrode which is near the Ti buffer layer, and measure the corresponding current by Agilent 4156C semiconductor parameter analyzer. When the accumulated energy exceeds a certain limit determined by the device material and thickness [2.3], the current reaches at the value of compliance current, and the forming step is accomplished, as shown in Fig. 2.4. The compliance current is usually set to be a little less than the compliance used in normal SET process.

2.3.3 Sweep Operation

After the “forming” process, this device switches to LRS (Low Resistance State).

The following step is to turn it off, i.e., to switch the RRAM from LRS to HRS (High Resistance State). There are two operation modes to identify the switching type of RRAM devices [2.4]. As shown in Fig. 2.5, one is unipolar, and the other one is bipolar. Unipolar means that the turn on voltage and turn off voltage are at the same polarity, where the turn on voltage is usually larger than turn off voltage. On the other hand, the bi-polar means that the turn on voltage and turn off voltage are in opposite polarities. Usually the bi-polar switching device is more suitable for future CMOS technology owing to less operation voltage and power consumption. The basic characteristic of a typical device is shown in Fig. 2.6, which is obviously a bipolar device. The illustrations of voltage sweep operations in this work are shown in Fig. 2.7 and Fig. 2.8.

2.3.4 Pulse Operation

In order to control the pulse timing of Agilent 81110A during transient and P/E cycling endurance characteristics precisely, we select the triggered pattern mode to achieve this goal. Fig. 2.9 (a) and Fig. 2.9 (b) show the program and erase schemes on the RRAM devices respectively. For example, by taking the programming timing pattern as shown in Fig. 2.9, the triggered pattern mode can be explained as follows. In Fig. 2.9 (a), the VSU1

of Agilent 4156C generated a voltage signal which is equal to the low voltage level of Agilent 81110A. This triggered pattern mode method can provide a substrate bias during programming, and prevent additional stress to device during P/E cycling endurance operation. The pattern mode defined as 01000 in Fig. 2.9 (a) from Agilent 81110A is then sent and the program or erase operation is performed.

2.3.5 Sampling

After the sweep and the pulse operation, we have to check whether the RRAM device is switched successfully. So, we have to sense the currents by Agilent 4156C under a read voltage for a period of time and then average them to get the resistance. Fig. 2.10 illustrates the concept of this measurement method. This sampling procedure reads RRAM by applying 0.1 V to evaluate current and resistance. The 0.1 V is chosen to be less than RRAM switching threshold to avoid disturbance.

The Random Telegraph Noise (RTN) signal is extracted by the same method; we can say that is the long time read operation. RRAM current is about 100 nA ~ 100 µA. The

2.3.6 Statistics of Random Telegraph Noise

The target of RTN measurement is to extract mean capture and emission time and then further profile traps properties. Therefore, the switching of trap captures and electrons emitting must be distinguished. We can determine using naked eye and it’s also the most precise method to obtain mean capture and emission time. Nevertheless it wastes time and not efficient for large amount of data. In our work, we wrote a program and used a current level that lies in the middle of the high and low current state to differentiate trap holding or releasing an electron automatically. Sequentially, every period of time was added and divided by numbers of events. As a consequence, we extracted more accurate mean capture and emission time which can handle much larger amount of data.

Fig. 2.1 XPS depth profile of TiN/Ti/HfO2/TiN stack layers after alloying.

01000

Probe Station Personal Computer

HP 81110A Pulse Generator

Parameter Analyzer HP 4156C

Switch Matrix HP 5250 A

Fig. 2.2 The experimental setup of the current-voltage and the P/E cycling endurance characteristics measurement in RRAM. Automatic controlled

characterization system is setup based on the PC controlled instrument environment.

Fig. 2.3 The cross section of transition metal oxide based resistive switching memory during forming process.

Fig. 2.4 Forming: the predominant step before resistive switching operation.

(a)

(b)

Fig. 2.5 Two operation modes of RRAM. (a) unipolar and (b) bipolar.

Fig. 2.6 Basic characteristics of the test RRAM cells in this thesis.

Fig. 2.7 Illustration of positive sweep operation in RRAM.

Fig. 2.8 Illustration for negative sweep operation in RRAM.

Fig. 2.9 The timing diagram of the triggered pattern mode method during (a) program and (b) erase operations.

Fig. 2.10 Illustration of sampling operation.

Chapter 3

Multi-Level Storage and Reliability Issues of RRAM

3.1 Introduction

In this chapter, we will show the operation methods of resistive random access memory to achieve multi-level storage and the associated definitions. One method is sweep operation, the other one is pulse operation. Also, we will discuss the reliability issues after different operating methods. Regarding the reliability, we measure the resistance loss at 100 ^oC after these operations, to observe the data retention characteristic of these devices.

After that, we will compare the program/erase cycling endurance between sweep and pulse operation methods. From different operation methods, we discuss the advantages and shortcomings for distinct use of the device.

3.2 The Sweep Operation of RRAM

3.2.1 The Switching Parameter Definitions of RRAM

The main parameters used in this thesis are shown in Fig. 3.1. When RRAM is switched to LRS, we define Vset as the turn on voltage, and Iset as the corresponding current. For the memory device, we limit the RRAM current during the set and forming

we define the maximum negative voltage as V_stop.

3.2.2 Compliance Current

The objective for setting the compliance current is to prevent the dielectric hard breakdown of the RRAM device [3.1]. During the “forming operation” and the “set operation,” we must have to set the compliance current to ensure not to destroy the function of the RRAM device. In this case, the compliance current is achieved by Agilent 4156C via the HT-BASIC language.

3.2.3 SET Operation by Different Compliance Currents

As shown in Fig. 3.2, for the low resistance state (LRS), we can achieve multi-level storage by using different compliance currents. When the top voltage ramped up, the soft breakdown paths were generated. The voltage step is set very small to ensure that these soft breakdown paths are formed slowly and concentrated [3.2]. Then, we setup the compliance current during the positive sweep; the compliance current level will be able to control these soft breakdown paths’ number or cross-section. When the RRAM current reaches the compliance current that we set, this current will be fixed by Agilent 4156C. In other words, the soft breakdown paths stop growing. Different sizes of soft breakdown paths correspond to different RRAM resistances. In the meantime, the soft breakdown paths’ size increased, the current increased under same read voltage. So, we can achieve multi-level storage in the low resistance state by changing different compliance currents.

For the high resistance state (HRS), RRAM device after a negative voltage sweep now changes the resistance state. During this process, some soft breakdown paths are rupture which can be caused by reoxidation of a narrow filament tip adjacent to the electrode [3.3]. So the number of these conductive paths is decreased obviously. All of these soft breakdown paths will be eliminated when the absolute value of the stop voltage is large enough. In other words, the RRAM current must be a tunneling current because the soft breakdown paths are separated from the electrode [3.4]. Also as mentioned above, the multi-level storage can be achieved by changing different stop voltage V_stop, which is shown in Fig. 3.3. The absolute value of stop voltage increases, the RRAM resistance increases as well, as shown in Fig. 3.4.

3.2.5 Discussion

The current is a key performance metric for the operation of RRAM devices as it governs the power needed for switching operation [3.5]. For the low power operation of the memory devices, we should reduce reset current. As shown in Fig. 3.5, RESET current (Ireset) and set current (compliance current) are interrelated. The order of these two currents is the same. So, we can lower the compliance current of forming and set process to achieve a low power operation.

When the RRAM device is switched to low resistance state, i.e., set process, if the compliance current we setup is too small, the soft breakdown paths are not completely

compliance current level, i.e., the maximal resistance at low resistance state (LRS).

For the data retention characteristics, we achieve the different resistance levels by the sweep operation. The LRS data writing for five resistance levels has been demonstrated by varying the compliance currents of sweep process. In Fig. 3.7, the LRS multi-level resistance is achieved by five compliance currents (200 µA ~ 650 µA) at 100 ^oC, and we check the prediction of the retention time for 10 years. Furthermore, the HRS multi-level storage is achieved by different stop voltages. We vary four different stop voltages (-1.0 V

~ -1.5 V), and it shows good data retention characteristics. Here, we can obtain nine different levels on one cell, while it still maintains distinct levels after 10,000 seconds.

The program/erase cycling endurance characteristics of sweep operation are shown in Fig. 3.8. L1 and L2 are the LRS with 650 µA and 200 µA compliance currents respectively. L3 and L4 are the HRS where the stop voltages are -1.0 V and -1.5 V. We can see that the resistance fluctuation is larger. The larger resistance state shows larger resistance variation. For the purpose of the data retention use, we can control the device with nine levels and even more. But if we consider this device for cycling endurance objective, the level number should be reduced. Otherwise, the neighboring states will be overlapped. It will result in errors in the read-out during multi-level operation.

3.3 The Pulse Operation of RRAM

3.3.1 SET Operation by Different Pulse Amplitudes

RRAM device. The same as sweep operation, we add a positive bias to RRAM top electrode to accomplish the set process. There are some differences between these two operation methods. First, the voltage changing rate from 0 V to Vhigh of pulse is larger than the sweep operation. Second, the pulse voltage (V_high) is always higher than the turn on voltage of the sweep operation.

The multi-level operation is achieved by changing the pulse amplitudes. The pulse width is 1x10^-8 sec, by changing the pulse amplitudes from 1.5 V to 2.5 V. Then, we will get different resistance levels, as shown in Fig. 3.9. The resistance decreases as the pulse voltage increases. So, the RRAM resistances at the low resistance state can be controlled by different pulse voltages to achieve multi-level storage.

3.3.2 RESET Operation by Different Pulse Widths

Different from the set operation, to achieve multi-level storage of high resistance state (HRS), we control the width of the negative pulse. The pulse amplitude should be selected appropriately. If the pulse amplitude is too large, the RRAM device will reverse breakdown and this device will be failed in the switching. In this case, we fix the pulse voltages where V_low is 0 V and V_high is -2 V; and then, we change the pulse widths from 5x10^-8 to 1x10^-6 sec. As shown in Fig. 3.10, the multi-level storage is achieved by changing the pulse widths.

3.3.3 Discussion

breakdown paths is different between the moderate sweep operation and the heavy pulse operation. We know that the metal oxide is composed of many grains after the deposition process. The grain boundaries (GBs) constitute a preferential leakage current path, which then get transformed into the soft breakdown path during the forming or set process [3.6].

For the sweep operation with slowly voltage ramping step, the soft breakdown paths are generated and centralized at the weakest point first. Then, the other soft breakdown paths increase near that point. For the pulse operation with severe voltage jump, there are many weaker points which will be transferred to soft breakdown paths under the higher pulse voltage (Vhigh). Therefore, the soft breakdown paths during the pulse operation are more disperse than those of the sweep operation.

For the data retention characteristics, we achieve the different resistance levels by pulse operation. For the low resistance state (LRS), there are six levels which are operated by different pulse amplitudes. And, for the high resistance state (HRS), we setup four levels which are achieved by different pulse widths. As shown in Fig. 3.11, the high and low resistance states are separated more than one order difference, but some levels are overlapped. We have no problem to control the high and low resistance states in the beginning. But after 200 seconds baking (100 ^oC), the high resistance state becomes unstable. Here, we can see that L2 and L3 overlap around 1k seconds. For another case, the high resistance states overlap more serious, as shown in Fig. 3.12 (a). By sensing the current, we found the random telegraph noise (RTN) phenomena, as shown in Fig.3.12 (b).

The ∆I/I is larger than 30 % and it might cause the resistance unstable. The random telegraph noise phenomena will be investigated in more detail in the next chapter.

For the program/erase cycling endurance characteristics of pulse operation, shown in Fig. 3.13, during the set step, the pulse amplitude is 2.5 V and the pulse width is 1x10^-8 sec.

Also, for the reset step, the pulse high is -2.0 V and the pulse width is 1x10^-6 sec. There is no multi-level window for the pulse operation, because the cycling endurance characteristics are not good. The resistance fluctuation is serious; we speculate that the reason is attributed to the voltage ramping rate during forming and set process. The soft breakdown paths generation after each switching may not be identical, and the instantaneous voltage jump causes their distribution more dissimilar after every set/reset cycle because there are many weaker grain boundaries. So, the soft breakdown paths will be randomly distributed, leading to more severe RRAM resistance fluctuations.

For the low resistance state operated by pulse method, we compare ∆R_max/R versus different device area during 1000 times set/reset cycle. As shown in Fig. 3.14, the resistance variation becomes larger as the area of device increasing. The large device size will damage endurance characteristics.

To solve these problems, controlling the soft breakdown paths is important. By using a slower voltage ramping rate, the improving of the oxide quality, or shrinking the memory area will help us to ameliorate the RRAM reliability which include data retention and program/erase cycling endurance characteristics.

-1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 10^-6

10^-5 10^-4 10^-3

Cu rr en t ( A)

Top Voltage (V)

V_reset, I_reset,max C.C.

V_stop

V_set

Fig. 3.1 Typical current-voltage characteristics of RRAM. C.C. represents the compliance current. Vstop is the maximum negative sweep voltage. Vreset or Ireset,max are the voltage or current at which reset takes place. Vset is the voltage at which set takes place.

0.0 0.2 0.4 0.6 0.8 1.0 0

100 200 300 400 500 600 700

Top Voltage ( V )

C ur re nt

(

µA

)

C.C.=200uA C.C.=250uA C.C.=350uA C.C.=500uA C.C.=650uA

Fig. 3.2 The multi-level characteristics of R_low in TiN/TiO_x/HfO_x/TiN device by controlling the compliance current (C.C.).

-1.6 -1.4 -1.2 -1.0 -0.8 -0.6 -0.4 -0.2 0.0 10

100 1000

Vstop=1.00V Vstop=1.10V Vstop=1.25V Vstop=1.50V

|C u rr en t| ( µA )

Top Voltage ( V )

Fig. 3.3 The multi-level characteristics of Rlow in TiN/TiOx/HfOx/TiN device by controlling stop voltage (Vstop).

-1.5 -1.4 -1.3 -1.2 -1.1 -1.0 8

10 12 14 16 18

re si st an ce ( k Ω )

Stop Voltage ( V )

Fig. 3.4 The stop voltage dependence of the resistance on TiN/TiO_x/HfO_x/TiN device.

0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 10

^-6

10

^-5

10

^-4

10

^-3

SET RESET

| C u rren t | ( A )

| Top Voltage | ( V )

Fig. 3.5 Ireset, max during sweep is kept at the same current order as the previous set process.

0.0 0.2 0.4 0.6 0.8 1.0

50 100 150 200

250 C.C.=100uA

C.C.=200uA C.C.=250uA

C ur re nt (µ A )

Top Voltage ( V )

Semi-on state

(a)

(b)

Fig. 3.6 Illustration for the partially-on state. (a) The state we pick off which is not conducted enough. (b) The current is dominant by tunneling component since

1 10 100 1k 10k 100k 1M 10M 100M 10³

10⁴

RESET_1.5V RESET_1.25V RESET_1.1V RESET_1.0V

SET_200uA SET_250uA SET_350uA SET_500uA SET_650uA

re si st a n ce ( Ω )

Time (sec)

10 years

Fig. 3.7 Data retention properties of various states by sweep operation. The result predicts 10 years lifetime of each state.

10⁰ 10¹ 10² 10³ 1k

10k 100k 1M

re si st a n ce ( Ω )

Cyc_times

L4 : V

^stop

= -1.5V

L3 : V

stop

= -1.0V

L2 : C.C. = 200µA L1 : C.C. = 650µA

Fig. 3.8 The program/erase cycling endurance characteristics of sweep operation. L1 and L2 are the LRS with 650 µA and 200 µA compliance currents respectively. L3 and L4

1.4 1.5 1.6 1.7 1.8 1.9 2.0 2.1 2.2 2.3 2.4 2.5 2.6 0.8

1.0 1.2

res is ta n ce (k Ω )

V

_SET

(V)

pulse width : 1x10

^-8

sec

V_SET

Fig. 3.9 The pulse voltage dependence of the resistance at low resistance state in TiN/TiOx/HfOx/TiN device. The positive pulse width is 1x10^-8 sec.

10^-7 10^-6 20

40 60 80 100

res is ta n ce ( k Ω )

t

_RESET

( sec )

t

_RESET

0V

-2V

Fig. 3.10 The pulse width dependence of the resistance at high resistance state in TiN/TiOx/HfOx/TiN device. The negative pulse amplitude is -2 V.

Fig. 3.11 Data retention properties of various states by pulse operation. The result predicts 10 years lifetime of each LRS, but not HRS.

(a)

2 3 4

1.6 1.8 2.0 2.2

C u rr en t (µ A )

Time ( sec )

∆I/I = 37%

(b)

Fig. 3.12 (a) The high resistance states overlap after 10 sec. (b) By sensing the current, the random telegraph noise (RTN) phenomena is observed. The ∆I/I

1 10 100 1000 1k

10k 100k

resi st an ce ( Ω )

Cyc_times

Fig. 3.13 The program/erase cycling endurance characteristics of pulse operation.

The resistance fluctuation is serious after each switching.

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 2

3 4 5 6 7

res ist a n ce v ari a ti on ∆ R

max

/R

Cell Size ( µm

²

)

0.0 0.5 1.0 1.5 2.0

Sweep Pulse

Fig. 3.14 Cell size dependence of the resistance variation (∆Rmax/R) after 1000 times set/reset cycles.

Chapter 4

Random Telegraph Noise Behavior of RRAM

4.1 Introduction

In this chapter, we will discuss the random telegraph noise of RRAM. The amplitude, capture and emission time are the critical parameters of the random telegraph noise (RTN) behavior and they depend on the trap properties, such as trap depth into dielectrics, and

In this chapter, we will discuss the random telegraph noise of RRAM. The amplitude, capture and emission time are the critical parameters of the random telegraph noise (RTN) behavior and they depend on the trap properties, such as trap depth into dielectrics, and

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