Chapter 1 Introduction
1.3 Organization of the Thesis
In floating gate device, there are some problems in the scaling down. The floating gate device should use thick tunneling oxide, which is required to guarantee long charge retention time. Thus, they need high voltage operation for program and erase.
Recently, silicon-oxide-nitride-oxide-silicon (SONOS) structure of charging device become attractive because they do not have planar scaling problem for floating gate isolation and they show good retention characteristic due to the discrete and deep traps in the nitride trapping layer. Therefore, low voltage operation by application of thin tunneling oxide is practicable [17]. Besides, the localized carrier trapping in the trapping layer makes a 2-bits operation possible.
From all of above, we want to fabricate a high performance nonvolatile memory with a high-k charge-trapping layer. The high-k dielectric material are La2O3 and Pr2O3. These high-k layer replace the silicon nitride layer in the SONOS structure.
These materials provide high trapping state densities and deep trapping levels, therefore they can enhance the retention of nonvolatile memories. The charge-trapping efficiency can be improved, and larger operation window can be achieved. The application of high-k materials can further reduce the operation voltage and potentially can help memory device scaling.
1.3 Organization of the Thesis
In the following section, we will show our research efforts.
In chapter 2, the electrical characteristics and fabrication process of 55nm tri-gate flash memory with HfO2 nanocrystal trapping layer will be proposed. The Experiment results reveal that the program/erase speed and endurance of our device have good performance.
In chapter 3, the electrical characteristics and fabrication process of Characteristics of SONOS-type Memories by Using Lanthanum Oxide Trapping Layers will be proposed. The Experiment results reveal that the program/erase speed and endurance of our device have good performance.
In chapter 4, the electrical characteristics and fabrication process of Characteristics of SONOS-type Memories by Using Praseodymium Oxide Trapping Layers will be proposed. The Experiment results reveal that the program/erase speed and endurance of our device have good performance.
At the end of this thesis, we will make a conclusion in chapter 4.
References:
[1] D. Kahng and S. M Sze, Bell Syst. Tech,J.,46,1288 (1967).
[2] A.THean, and J.-p. Leburton, “Flash memory: toward single-electronics,”IEEE Potentials, pp.35-41, OCT./Nov.,2002
[3] Fujio Masuoka, Masamichi Asano, Hiroshi Iwahashi, Teisuke komuro, Norriyoshi Tozawa, and shinichi Tanaka “A 256-kbit Flash E2PROM Using Triple-Polysilicon Technology,” IEEE Journal of Solid-State Circuit vol.sc-22, no.4, AUG., 1987.
[4] M. H. White and D. Adams, “Low-Votage SONOS Nonvolatile Semiconductor Memory (NVSMs),” GOMAC 2000.
[5] A.fernandes, B. DeSalvo, P. Masson, G. Pananakakis, G. Ghibuado, T. Baron, N.Buffet, D.Mariolle, B. Gullaumot, “Electrical Characteristic of Memory-cell Structure Emploting Ultra-thin Al2O3 Film as Storage Node”, Proc.ESSDERC 2001, pp. 139-142
[6].Yan-Ny Tan, Wai-kin Chim, Byung jin Cho, and Wee-Kiong Choi, “Ovre-Erase Phenomenon in SONOS-Type Flash Memory and its Minimization Using a Hafnium Oxide Charge Storage Layer,” IEEE Electron Device, vol. 51, no. 7.July 2004.
[7] Vladimir A. Gritsenko,” Design of SONOS Memory Transistor for Terabit Scale EEPROM,” Electron Devices and Solid-State Circuits, 2003 IEEE Conference on 16-18 Dec. 2003 Page(s):345 - 348
[8] T. Sugizaki, M. Kobayashi, M. Ishidao, H. Minaka, /m. /yamaguchi, Y. Tamura, Y.
Sugiyama, T. Nakanishi, and H. Tanaka, “Novel multi-bit SONOS type flash memory using a High-k charge trapping layer,” in Proc. VLSI Symp. Technology Dig. Technical Paper, 2003, pp.27-28.
[9] M. L. Ostraat, J. W. De Blauwe, M. L. Green, L.D. Bell, M. L. Brongersma, J.
Casperson, R. C. Flagan, and H. A. Atwater, “Synthesis and characterization of aerosol silicon nanocrystal nonvolatile floating-gate memory device,” Appl. Phys.
Lett., vol 79, pp. 433-435, 2001.
[10] P. W. Li, W. M. Liao, S.W. Lin, P.S.Chen, S.c. Lu, and M.-J. Tasi, “Formation of atomic scale germanium quantum dots by selective oxidation of SiGe/Si-on-insulator,” Appl. Phys. Lett., vol.83, pp.4628-4630, 2003.
[11] Yu-Hsien Lin, Chao-Hsin Chien, Ching-Tzung Lin, Chun-Yen Chang, and Tan-Fu Lei, “High-performance nonvolatile HfO nanocrystal memory,” IEEE 2
Electron Device Letters, vol.26, Page:154 - 156 Issue 3, March 2005.
[12] Z. Liu, C. Lee, V. Narayanan, G. Pei, and E. C. Kan, “Metal nanocrystal memory, part I: Device design and fabrication,” IEEE Electron Device, vol. 49, pp.
1606-1613, Sept. 2002.
[13] Z. Liu, C. Lee, V. Narayanan, G. Pei, and E. C. Kan, “Metal nanocrystal memory, part II: Device characteristics,” IEEE Electron Device, vol. 49, pp. 1614-1622, Sept. 2002.
[14] Peiqi Xuan, Min she, Bruce Harteneck, Alex Liddle, Jeffery Bokor and Tsu-Jae King, “FinFET SONOS flash memory for embedded application,” in IEDM Tech.
Dig., 2003, pp.609-6013.
[15] M. specht, R. Kommling, L. Dreeskornfeld, W. Weber, F. Hofmann, D. Alvarez, J.
Kretz, R. J. Luyken, W. Rosner, H. Reisinger, E. Landgraf, T. Schulz, J. Hartwich, M. Stadele,V. Klandievski, E.Hartmann, and L. Risch, ”Sub-40nm tri-gate charge trapping nonvolatile memory cells for high-density application,“ VLSI Symp.
Technology Dig. Technical Paper, 2004, pp.244-245
[16] Yu-Hsien Lin, Chao-Hsin Chien, Ching-Tzung Lin, Chun-Yen Chang, and Tan-Fu Lei, “High-performance nonvolatile HfO nanocrystal memory,” IEEE 2
Electron Device Lett, vol.26, Page:154 - 156 Issue 3, March 2005.
[17] H. Wann and C. Hu, ”High–endurance ultra thin tunnel oxide in MONOS device structure for dynamic memory application,” IEEE Electron Device Lett., vol.16, pp.491-493, Nov.1995.
Package
UV light No need Electrically Electrically
Double
UV light No need Electrically Electrically
Double
Table.1-1 The comparison of the flash memory with PROM, EPROM, and EEROM
Si substrate
Fig. 1-1 The basic concept of Floating-gate (FG) non-volatile memory
Id
Si substrate
Fig. 1-3 The basic concept of SONOS-type non-volatile memory
Si substrate
Fig. 1-4 The basic concept of nanocrystal non-volatile memory
Chapter 2
Characteristic of tri-gate Flash Memory with HfO
2nanocrystal Trapping Layer
2.1 Introduction
With the development of semiconductor industry, high density flash memories for stand-alone data storage application require device with minimum feature smaller and smaller, such as 50nm. However, the conventional floating gate (FG) nonvolatile memory (NVM) devices use a poly-Si film as charge storage layer in which the information is stored by injecting charges from the inversion or accumulation layer of a MOSFET. Improvements of their performance are based on the shrinkage of the technology and, such as the reduction of the gate length and the thickness of the tunnel oxide. However, further scaling of the floating gate nonvolatile memories is facing severe reliability issues such as the difficulty to maintain long data retention times.
In order to overcome the scaling limit, the idea of the discrete-trap mechanism has been proposed. It means that we can replace the floating gate of nonvolatile memories by many discrete trapping centers, which can be made by natural traps in an appropriate insulator such as a nitride layer in SONOS [1][2] memories or by nanocrystals. And it also has been shown that tri gate structure [3] can suppress short channel effects and drain-induced barrier lowering (DIBL) due to the improved electrostatic control of the channeling region.
And Lee et al. [4] has reported that a high-k nanocrystal charge-trapping layer can be fabricated by annealing high-k silicate materials, such as HfSixOy. After applying a
rapid thermal anneal to the silicates, phase-separation happens. HfO2 nanocrystals []
are formed and surrounded by SiO2. Hence with the nanocrystals charge trapping layer, the stored charges will be trapped in or around the nanocrystals and isolated by silicon dioxides. Hence, less opportunity of charge loss is expected and a local defect of tunnel oxide won’t cause a severe charge loss. With such a nanocrystal structure as the charge-trapping layer, the retention of nonvolatile memories can be further improved.
In this work, an ONO sandwich structure gate-dielectric stack with HfO2
nanocrystals trapping layer is form on Si in order to fabricate a tri-gate memory device. And the device show that it has large memory window, good program /erase speed, good retention, and good endurance.
2-2 Experimental
Figure 2-1 schematically depicts the process flow of the proposed flash memory.
First, the active region was patterned by E-beam lithography and etching system.
Then, a 2-nm tunneling oxide was grown at 1000°C in vertical furnace system. The trapping layer of amorphous HfSiOx silicate layer was deposited by co-sputtering method with pure Silicon (99.9999% pure) and pure Hafnium (99.9% pure) in the oxygen and argon gas ambient. Then, a blocking oxide of about 85nm was then deposited by plasma-enhanced chemical vapor deposition (PECVD) system.
Subsequently, 50-nm amorphous silicon (a-Si) gate and 50-nm SiN3 were deposited by LPCVD. The a-Si gate layer was divided into in-situ n doped gate+ . The dopant of in-situ n+ doped a-Si gate was phosphorus. After gate patterning, the remaining oxide on source/drain regions was removed by diluted HF. Then, a self-aligned implantation was used to perform the n+ source/drain with As+ to dose 5 × 1015 cm-2
and energy 20 keV, tilt 30o.After implantation, and a 50-nm TEOS oxide sidewall spacer was formed by deposition and etching of TEOS oxide. After that the dopants were activated by RTA at 950°C for 10s and at the same time, HfSiOx silicate layer was converted into the separate HfO2 and SiO2 phase. Finally, the nitride layer was etched by H3PO4 solution.
2-3 Results and Discussion
2.3.1 Material Analysis of HfO
2Nanocrystals
Figure 2-2 shows the scanning electron microscopy (SEM) image and Figure 2-3 shows cross-section-view high-resolution transmission microscopy (HRTEM) image of the HfO2 nanocrystals tri-gate device. Clearly, the gate length is about 55nm from the HRTEM image and the thicknesses of the tunnel oxide and blocking oxide layer are 2.2nm, 8nm, respectively. The trapping layer thicknesses are 7.9nm and the nanocrystals were separated in two dimensions within the SiO2; in which the average distance is >5 nm. This isolation of the nanocrystals prevents the formation of effective conductive paths between adjacent nodes. The mechanism responsible for the formation of HfO2 nanocrystal is through the phase separation of hafnium silicate into a crystallized structure [5]. For the Hf-silicate layer, the compositions within metastable extensions of the spinodal are unstable and HfO2 nanocrystal will be formed and enclosed by SiO2 after cooling down from RTA processing. All devices described in this paper had dimensions of L = 50nm.
2.3.2 Characteristics of Fresh Devices
Figure 2-4 shows the Ids-Vgs curves of the tri-gate HfO2 nanocrystal tri-gate memory devices with programming time of 0.3. Fowler-Nordheim tunneling injection was employed for programming and erasing. A memory window of about 1.5V can be
achieved at the Vg=8V program operation. Program characteristics of different pulse width for different operation conditions are shown in Figure. 2-5. We employed channel hot-electron injection and Fowler-Nordheim tunneling injection in Figure 2-5(a) and Figure 2-5(b). The “Vt shift” is defined as the threshold voltage change of a device between the written and the erased states. For channel hot-electron injection with Vg=11V Vd=4V, relatively high speed (0.1ms) programming performance can be achieved with a memory window of about 1.8V. For Fowler-Nordheim tunneling injection with Vg=11V, a memory window of about 1.8V can be achieved with 1ms pulse width. Hence, the speed of channel hot-electron injection is faster that of Fowler-Nordheim tunneling injection Meanwhile, Figure 2-6 displays the erase characteristics as a function of various operation voltages. Again, excellent erase speed of around 1 ms can be obtained with Vg=-3V Vd=4V for band to band hot hole injection.
The retention characteristics of the HfO2 nanocrystal tri-gate memory devices at room temperature (T=25°C) and higher temperature (T=85°C, 125°C) are illustrated in Figure 2-7. The retention time can be up to 108 seconds for 17% charge loss at room temperature and 40% charge loss and 65% charge loss for the 85°C and 125°C s conditions. We ascribe these results to the combining effects of the tight embrace of HfO2 nanocrystals by SiO2-rich matrix and the sufficiently deep trap energy level [6,7]. As a result, superior retention characteristic of the charge storage can be procured[8-11].
The endurance characteristics after 104 P/E cycles are also shown in Figure 2-8.
The programming and erasing conditions are Vg=11V Vd=4V for 1ms and Vg=-3V, Vd=4V for 1ms, respectively. Slight memory window narrowing has been displaye and the individual threshold voltage shifts in program and erase states become visible after 103 cycles.. This trend indicates the formation of operation-induced trapped
electrons. Certainly, this is intimately related to the use of ultra-thin tunnel oxide and very minute amount of residual charges in the HfO2 nanocrystals after cycling.
The cycling retention is an important issue for flash memory. Therefore, we studied the retention loss behavior of the device before and after 10K cycling. Figure 2-9 show the cycling retention behavior of the cell at room temperature (25oC).As we can see in Figure 2-9, the charge loss behavior of the device with 10K cycling is more serious than the device without 10K cycling under room temperature condition. The retention time can be up to 108 seconds with 70% charge for cycling device. We ascribe these results to that the tunneling oxide was damage after10K P/E cycling.
Hence, the capability of charge storage was decreased.
2.3.3 Characteristics of 2-bit operation
Figure 2-10 demonstrates the feasibility of performing two-bit operation with our HfO2 nanocrystal tri-gate memories through forward and reverse read scheme in a single cell. From the Ids–Vgs curves, it is clear that we could employ forward and reverse reads to detect the information stored in the programmed bit1 and bit2, respectively. Table 2-1 summarizes the bias conditions for two-bit operation. Figure 2-11 shows the 2-bit retention characteristics of the HfO2 nanocrystal tri-gate memories. The retention time can be up to 108 seconds with 0.8V memory window between programmed bit-1 and erased bit-2. We can see that charge loss occurred for programmed bit-1 and charge gain for erased bit-2. This suggests that there is lateral migration of trapped electron.[12]
2.3.4 Disturbance
Figure 2-12 demonstrates the read disturbance induced erase-state threshold voltage instability in a localized HfO2 nanocrystal tri-gate Flash memory cell under several operation conditions. For two-bit operation, the applied bitline voltage in a
reverse-read scheme must be sufficiently large (>1.5 V) to be able to “read through”
the trapped charge in the neighboring bit. The read-disturb effect is the result of two factors: the word-line and the bit-line. The word-line voltage during read may enhance room temperature (RT) drift in the neighboring bit [12]. On the other hand, a relatively large read bit-line voltage may cause unwanted channel hot-electron injection and, subsequently, result in a significant threshold voltage shift of the neighboring bit. In our measurements, the gate and drain biases were applied and the source was grounded. The results demonstrate clearly that almost no read disturbance occurred in our HfO2 nanocrystal tri-gate Flash memory under low-voltage reading (Vg =1.5 V; Vd = 1.5 V). For a larger memory window, we found that only a small read disturbance can be observed after operation at Vd = 2 V after 1000 s at 25 °C.
Figure 2-13 shows the programming drain disturbance of our HfO2 nanocrystal tri-gate Flash memory. Drain disturbance may occur during programming for the cells sharing a common bit-line while one of the cells is being programmed and gate disturbance may occur during programming for the cells sharing a common word-line while one of the cells is being programmed as in Figure 2-14. Two different drain voltages (Vd = 3 and 4 V) were applied in the programming drain disturbance measurements at room temperatures. We observed that a 1.5V drain disturb was observed after programming at a value of Vd of 4V under T = 25 °C and after stressing for 1000 s. Figure 2-15 shows the gate disturbance characteristics in the erasing state. Because we can program the device by Fowler-Nordheim tunneling injection, the gate disturbance will not be too small. Hence,we observed a threshold voltage shift of 2.5 V under the following conditions: Vg = 11 V; Vs = Vd = Vsub = 0 V;
stressed for 1000 s. Hence, a non-negligible current will be present in the tunnel oxide when a voltage of 11 V is applied to the gate electrode.
2.4 Summary
In this chapter, we have proposed a novel simple, reproducible, reliable technique for preparation of 55nm high density HfO2 nanocrystals tri-gate memory using spinodal decomposition of hafnium silicate on SOI. It has good characteristics in terms of large memory windows, high speed program/erase, good retention time, excellent endurance, and 2-bit operation.
With these superior performance, we believe that nano-scale HfO2 nanocrystal flash memory on SOI is the candidates used for the high density storage application.
Reference
[1] B. Eitan, P. Pavan, I. Bloom, A. Efraim, A. Frommer, and d. Finzi, “NROM: A novel localized trapping, 2-bit nonvolatile memory cell,” IEEE Electron Device Lett., vol. 21, pp. 543-545, Nov. 2000.
[2] M. H. White, D. A. Adams and J. Bu, “On the go with SONOS,” IEEE Circuits Devices Mag., vol. 16, pp. 22-31, July 2000.
[3] Peiqi Xuan, Min She, Harteneck. B., Liddle. A., Bokor. J., King. T.-J.,” FinFET SONOS flash memory for embedded applications” IEEE Electron Devices Meeting, 2003. IEDM '03 Technical Digest. 8-10 Dec. 2003 pp:26.4.1 - 26.4.4 [4] Yu-Hsien Lin, Chao-Hsin Chien, Ching-Tzung Lin, Chun-Yen Chang, and Tan-Fu
Lei, “High-performance nonvolatile HfO nanocrystal memory,” IEEE 2 Electron Device Lett, vol.26, Page:154 - 156 Issue 3, March 2005.
[5] Susanne Stemmer, Zhiqiang Chen, Carlos G. Levi, Patrick S. Lysaght, Brendan Foran, John A. Gisby, and Jeff R. Taylor, “Application of metastable phase diagrams to silicate thin films for alternative gate dielectrics,” Jpn. J. Appl. Phys., vol. 42, pp.
3593-3597, 2003.
[6] W.J. Zhu, Tso-Ping Ma, Takashi Tamagawa, J. Kim, and Y. Di, “Current Transport in Metal/Hafnium Oxide /Silicon Structure”, IEEE Electron Device Lett., vol. 23, no. 2, pp. 97-99, Feb. 2002.
[7] Barbara De Salvo, Gerard Ghibaudo, Georges Pananakakis, Gilles Reimbold, Francois Mondond, Bernard Guillaumot, and Philippe Candelier, “Experimental and theoretical investigation of nonvolatile memory data-retention,” IEEE Trans.
Electron Devices, vol. 46, no. 7, pp. 1518-1524, Jul., 1999.
[8] T. S. Chen, K. H. Wu, H. Chung, and C. H. Kao, “Performance improvement of SONOS memory by bandgap engineer of charge-trapping layer,” IEEE Electron
Device Lett., vol. 25, no. 4, pp. 205-207, Apr. 2002.
[9] “Test and test equipment” in The International Technology Roadmap for Semiconductors (ITRS), 2001, pp. 27-28.
[10] T. Sugizaki, M. Kobayashi, H. Minakata, M. Yamaguchi, Y. Tamura, Y. Sugiyama, H. Tanaka, T. Nakanishi, and Y. Nara, “New 2-bit/Tr MONOS type flash memory using Al2O3 as charge trapping layer,” in Proc. IEEE Non-Volatile Semiconductor Memory Workshop, Feb. 2003, pp. 60-61.
[11] Y. N. Tan, W. K. Chim, W. K. Choi, M. S. Joo, T. H. Ng, and B. J. Cho, “High-K HfAlO charge trapping layer in SONOS-type nonvolatile memory device for high speed operation,” in IEDM Tech. Dig., 2004, pp. 889-892.
[12]T.Sugizaki, M. Kobayashi, M. Ishidao, H. Minakata, M.Yamaguchi, Y. Tamura, Y.
Sugiyama, T. Nakanishi, H. Tanaka,” Novel multi-bit SONOS type flash memory using a high-k charge trapping layer” VLSI Technology, 2003. Digest of Technical Papers. 2003 Symposium, pp.27 – 28, June 2003
[13] W. J. Tsai, C. C. Yeh, N. K. Zous, C. C. Liu, S. K. Cho, T. Wang, S. C. Pan, and C. Y. Lu, “Positive oxide charge-enhanced read disturb in a localized trapping storage flash memory cell,” IEEE Trans. Electron Devices, vol. 51, no. 3, pp. 434-439, Mar.
2004.
Si
SiO2
Si
(a) The active region was patterned by E-beam lithography on SOI wafer
Si
SiO2
Si
(b) Tunnel oxide was grown at 1000°C in furnace
(c) HfSixOy deposited by sputter method as trapping laye SiO2
Si
HfSiOx
(d) blocking oxide then deposited by PECVD followed by 900°C in N2 densification
(e) Poly-Si deposited to serve as the gate electrode by LPCVD SiO2
Si
SiO2
Si
SiO2
Poly-Si
(f)SiN deposited as hard mask
(g) Gate electrode patterned and oxide spacer was formed SiO2
Si SiN
Poly-Si
SiO2
Si Poly-Si
SiN
SiO2 spacer
(i) Dopants were activated at 950 C and convert HfSixOy into HfO2 dots SiO2
Si
SiO2
Si As ion imp
(h) source/drain implanted by self-aligned As ion implantation
o
lantation
Poly-Si SiN
SiO2
Si
SiO2
S DSi
Poly-Gate
Fig.2- 1 Process flow of the flash memory d the cross-section of the flash memory (j)
an SiO2
Si Poly Si SiO2
SiO2
HfO2
S D
Poly Si
SiO2 spacer
Si
Fig.2-2 show the top view scanning electron micrograph of the memory devic
50nm
Gate
Source Drain
50nm
Gate
Source Drain
3(a)
5nm 80Å
79Å 22Å
HfO
2nanocrystal
5nm 80Å
79Å 22Å
HfO
2nanocrystal
3(b)
Fig.2-3a and 3b show the high-resolution TEM image of cross section and the ONO structure gate-dielectric stack are clearly seen. The gate length is around 55nm. Fig 3b show the high-resolution TEM image of the ONO-type gate stack The thickness of tunneling oxide, trapping layer, and blocking oxide are 22, 79, 80Å, respectively.
Vg(V)
-2 -1 0 1 2 3
Id(A)
10
-1510
-1410
-1310
-1210
-1110
-1010
-910
-810
-710
-610
-5Fresh
Prog Vg=8V t=0.3sec Erase Vg=-8V t=0.3sec
Fig. 2-4 show the Id-Vgs curves of the memory in the programmed/erased state.
Fig. 2-4 show the Id-Vgs curves of the memory in the programmed/erased state.