高介電材料及奈米微晶粒捕陷層在快閃記憶體之研究

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(1)國立交通大學電子工程學系. 電子研究所碩士班. 碩士論文. 高介電材料及奈米微晶粒捕陷層在快閃記憶體之研究. The Study of Flash Memory with High-K Material and Nano-crystal Trapping Layer. 研究生：楊宗元指導教授：雷添福博士. 中華民國九十五年六月.

(2) 高介電材料及奈米微晶粒捕陷層在快閃記憶體之研究 The Study of Flash Memory with High-K Material and Nano-crystal Trapping Layer. 研究生：楊宗元指導教授：雷添福博士. Student: Tsung-Yuan Yang Advisor: Dr. Tan-Fu Lei. 國立交通大學電子工程學系. 電子研究所碩士班. 碩士論文 A Thesis Submitted to Department of Electronics Engineering & Institute of Electronics College of Electrical & Computer Engineering National Chiao Tung University In Partial Fulfillment of the Requirements For the Degree of Master of Science in Electronic Engineering June 2006 Hsinchu Taiwan Republic of China. 中華民國九十五年六月.

(3) 高介電材料及奈米微晶粒捕陷層在快閃記憶體之研究學生：楊宗元. 指導教授：雷添福博士國立交通大學. 電子工程學系電子研究所碩士班. 摘. 要. 在本論文中，首先，我們製作出一個閘極長度為 55 奈米的氧化鉿奈米微晶粒記憶體在 SOI 晶片上。從實驗結果得知我們的元件有擁有記憶視窗大的特性、資料寫入/抹除速度快與資料保存能力好的特點，並且我們達成即使閘極長度為 55 奈米還可完成一個單元儲存 2 個位元的記憶體操作，並且我們的製程可與現今 CMOS 元件製程相配合。因此相信此元件在高密度儲存方面上的應用應該是有機會的。接著，我們使用高介電常數材料當作捕陷層成功的製作出了 SONOS 型非揮發性快閃記憶體，此材料為氧化鑭。我們在此實驗中達成有快速的寫入/抹除速度、大的記憶窗口、儲存資料持久性、以及寫入、清除操作造成的性能退化少的非揮發性快閃記憶體。並且，我們也成功的再此元件上設計出一個單元儲存 2 個位元的記憶體操作。因此相信使用氧化鑭來取代氮化矽在 SONOS 非揮發性快閃記憶體上是有機會的。最後，我們使用另一種高介電常數材料當捕陷層製作出了 SONOS 型非揮發性快閃記憶體，此材料為氧化鐠。我們在此實驗中，達成了電荷捕捉效率佳、有 I.

(4) 快速的寫入/抹除速度、大的記憶窗口的非揮發性快閃記憶體，但是其儲存資料持久性並不好。. II.

(5) The Study of Flash Memory with High-K Material and Nano-crystal Trapping Layer Student: Tsung-Yuan Yang. Advisor: Dr. Tan-Fu Lei. Department of Electronics Engineering & Institute of Electronics National Chiao Tung University ABSTRACT. In this thesis, first a tri-gate 55nm SONOS-type memories on SOI with HfSiOx nanocrystal trapping layers was proposed and demonstrated. We use CHE programming, FN programming, BTBHH erasing and FN erasing for the memory operation. Experimental results reveal that large memory windows, relative high P/E speed and good retention can achieve for SONOS-type memories and it is fully compatible to current CMOS technologies. In summary, tri-gate 55nm SONOS-type memories on SOI are the candidates used for the high density storage application. Then, a SONOS-type memories by using high-κ dielectric materials Lanthanum oxide trapping layers was proposed and demonstrated. We use CHE programming and BTBHH erasing for the memory operation. Experimental results reveal that large memory windows, relative high P/E speed and good retention can achieve for SONOS-type memories. In summary, La2O3 are the candidates used for the trapping layers for the SONOS-type memories and two-bit application. III.

(6) Finally, a SONOS-type memories by using high-κ dielectric materials Praseodymium oxide trapping layers was proposed and demonstrated. The SONOS-type Pr2O3 flash memories exhibit that they have large memory windows, relative high P/E speed but poor retention.. IV.

(7) 誌謝論文的完成，首先要感謝我的指導教授雷添福博士，兩年來的關心、指導與鼓勵讓我學到作研究的方法與精神。並且在我報告實驗進度與想法時，提供了很多寶貴的意見，讓我在這兩年覺得受益匪淺。在這兩年的碩士生涯中，在研究上能有些小成果，需要感謝的人很多。感謝林育賢學長的提攜，減少了我許多的摸索過程。感謝游信強學長、郭伯儀學長和小棟在實驗上的悉心指導和幫助。此外謝明山學長、楊學長、王獻德學長、陳志仰學長、張家文學長、桑學長、馬鳴文學長，感謝你們這些日子來的關心與指導。感謝同梯好友俊嘉、源竣、伯浩、梓翔，歷經了一起修課，一起惡搞實驗和機台，一起趕計測實驗報告的團體活動，讓我們成為彼此人生旅途上的重要一員。感謝錦石、統億、哲綸、久騰、明爵、仕傑、文呈，與你們相處的時光總是充滿歡樂。最後感謝我最親愛的家人，感謝我的父母楊吉香先生和郭李香女士無怨無悔的付出，數十年來，父母親對兒子關心，永識於心。謝謝你們的支持與鼓勵，僅以此論文獻給你們。. V.

(8) Contents Abstract (Chinese) ……………………………………………………………………I Abstract (English) …………………………………………………………………..III Acknowledge …………………………………………………………………………V Contents ……………………………………………………………………………..VI Table & Figure Captions .………………………………………………………...VIII. Chapter 1. Introduction …………………………………………………………….1. 1.1 Overview of Nonvolatile Flash Memory....……………………………………1 1.2 Motivation ……………….……………………………………………..……...4 1.3 Organization of the Thesis……………………………………………………..5 References …………………………………………………………………………7. Chapter 2. Characteristic of tri-gate Flash Memory with HfO2 nanocrystal. Trapping Layer..…....…………….…………………………….…………………...13 2.1 Introduction …………………………….………………………………...…..13 2.2 Experimental ….....………..…………………...……………………………..14 2.3 Results and discussion………………………………………………………..15 2.3.1 Material Analysis of HfO2 Nanocrystals…….....……..……….....…..15 2.3.2 Characteristics of Fresh Devices………………….. ..…………..……..15 2.3.3 Characteristics of 2-bit operation………………………………………17 2.3.4 Disturbance…………………………………………………………..…17 2.4 Summary …………………………………………………….…………….…19 References ………………………..………………………………………………20 VI.

(9) Chapter 3. Characteristic of SONOS-type Flash Memory by using La2O3. trapping layer...……………………………………………………………………39 3.1 Introduction …………………………………………………………………..39 3.2 Experimental …………………………………………………..……………..40 3.3 Results and Discussion ……………………………………………………….41 3.3.1 Material Analysis of La2O3 SONOS type flash memory..……….....…..41 3.3.2 Characteristics of Fresh Devices………………….. ..…………..……..41 3.3.3 Characteristics of 2-bit operation………………………………………42 3.3.4 Disturbance…………………………………………………………..…43 3.4 Summary ………………………………………………...…………………...44 References …………….………………………………………………………….45. Chapter 4. Characteristic of SONOS-type Flash Memory by using Pr2O3. trapping layer..…..………………………………………………………………….64 4.1 Introducion …………………………….……………………………………..64 4.2 Experimental …...……………………………………………….……………65 4.3 Results and Discussion ……………………………………………………….65 4.3.1 Characteristics of Fresh Devices………………….. ..…………..…..…65 4.3.2 Disturbance…………………………………………………………..…67 4.4 Summary ...…………………………………………………………………...68 References ……..…………………………………………………………………69. Chapter 5. Conclusions …………………….…….………………….…………….80. VII.

(10) TABLE CAPTIONS Chapter 1 Table 1-1 The comparison of the flash memory with PROM, EPROM, and EEROM.. Chapter 2 Table 2-1 Operation principles and bias conditions utilized during the operation of the HfO2 nanocrystal Flash memory cell. Chapter 3 Table 3-1 Operation principles and bias conditions utilized during the operation of the La2O3 Flash memory cell.. Chapter 4 Table 4-1 The summary of performance for La2O3 and Pr2O3 SONOS-like Flash memory.. VIII.

(11) FIGURE CAPTIONS Chapter 1 Fig. 1-1. The basic concept of Floating-gate (FG) non-volatile memory.. Fig. 1-2. The basic concept of the reading of the memory cell.. Fig. 1-3. The basic concept of SONOS-type non-volatile memory.. Fig. 1-4. The basic concept of nanocrystal non-volatile memory.. Chapter 2 Fig. 2-1. Process flow of the flash memory and the cross-section of the flash memory. Fig. 2-2. The top view scanning electron micrograph of the memory devic. Fig. 2-3. The high-resolution TEM image of cross section.. Fig. 2-4. The Id-Vgs curves of the memory in the programmed/erased state.. Fig. 2-5. Program characteristics of the memory devices with (a) CHE and (b) F-N programming.. Fig. 2-6. Erase characteristics of the memory devices with (a) BTBHH and (b) F-N erasing conditions.. Fig. 2-7. Retention characteristics of HfO2 nanocrystal memory devices at T=25°C, 85°C and 125°C.. Fig. 2-8. Endurance characteristics of the HfO2 nanocrystal flash memory devices. Slight degradation is found after 103 P/E cycles.. Fig. 2-9. Retention characteristics of HfO2 nanocrystal memory devices with cycling and fresh at T=25°C. Fig. 2-10. Ids-Vgs curve of the memory in the 2-bit per cell operation. ; forward read and reverse read for programmed bit1 and programmed bit2 IX.

(12) Fig. 2-11 Retention characteristics of the memory devices with Programmed bit-1 and Erased bit-2 at T=25°C. (b) show the schematic of lateral migration. Fig. 2-12 Read disturbance characteristics of the HfO2 flash memory Fig. 2-13 Drain disturbance characteristics of the HfO2 nanocrystal flash memory cells Fig. 2-14 The schematic illustration of disturb condition. When the cell is programming, those cell of the same word-line and the same bit-line are the gate disturb and drain disturb, respectively Fig. 2-15 Gate disturbance characteristics of the La2O3 memory devices. Chapter 3 Fig. 3-1. Process flow of the proposed flash memory cell.. Fig. 3-2. TEM image of the flash memory cell. The thickness of the O/N/O layers are 7/4/2 nm respectively.. Fig. 3-3. Ids-Vgs curves of the La2O3 memories. A memory window of larger than 3V can be achieved with Vg= Vd=9V programming operation.. Fig. 3-4. (a)Program characteristics of the memory devices with different programming conditions. (b). Erase characteristics of the memory devices with different erasing voltages.. Fig. 3-5. Retention characteristics of La2O3 memory devices at T=25°C, 85°C and 125°C.l.. Fig. 3-6. Endurance characteristics of the La2O3 memory devices.. Fig. 3-7. Retention characteristics of La2O3 memory devices with cycling and fresh at T=25°C, 85°C.. Fig. 3-8. Ids-Vgs curve of the memory in the 2-bit per cell operation. ; forward read and reverse read for programmed bit1 and programmed bit2. X.

(13) Fig. 3-9. Retention characteristics of La2O3 memory devices with Programmed bit-1 and Erased bit-2 at T=25°C. (b) show the schematic of vertical migration. Fig. 3-10 Drain disturbance characteristics of the La2O3 memory cells. Fig. 3-11 Gate disturbance characteristics of the La2O3 memory devices. Fig. 3-12 3-12 Drain current comparison between the programmed cell, erased and unselected cell. Cell information can be read out at Vg=4V and Vd=2V. Fig. 3-13 Read disturbance characteristics of the La2O3 flash memory.. Chapter 4 Fig. 4-1. Process flow of the proposed flash memory cell.. Fig. 4-2. Cross-section of the proposed flash memory cell.. Fig. 4-3. (. (a)Program characteristics of the memory devices with different programming conditions. (b)Erase characteristics of the memory devices with different erasing voltages... Fig. 4-4. Retention characteristics of Pr2O3 memory devices at T=25°C and 85°C.. Fig. 4-5. Endurance characteristics of the Pr2O3 memory devices. Slight degradation is found after 102 P/E cycles.. Fig. 4-6. Drain disturbance characteristics of the Pr2O3 memory cells .. Fig. 4-7. Gate disturbance characteristics of the Pr2O3 memory devices.. Fig. 4-8. Read disturbance characteristics of the Pr2O3 flash memory .. Fig. 4-9. Trapping efficiency of the Pr2O3 and La2O3 device.. XI.

(14) Chapter 1 Introduction. 1.1 Overview of Nonvolatile Flash Memory With the development of information technology, people put more and more emphasis on the materials and techniques of semiconductor memory, especially for the consumer electronic products. Memory can be divided in to two kinds by whether the storage data can be affect by the power supply. One is volatile memory, and the other s non-volatile memory. Volatile memory defines as that the data that stored in memory need power supply to maintain. On the other hand, non-volatile memory means that even if it encounters the break of power supply, the data in the memory also can maintain for a long time. For example, Dynamics Random Access Memory (DRAM) and Static Dynamics Random Access Memory (SDRAM) belong to volatile memory, and Read Only Memory (ROM), Electrically Programmable Read Only Memory (EPROM), and Flash memory belong to non-volatile memory. The speed of non-volatile memory although can not compare with volatile memory, but the data in non-volatile memory can maintain for a long time without power supply. Because of the advantage, non-volatile memory becomes more and more important and was used in all kinds of electronic products. In 1967, D. Kahng and S. M. Sze invented the first Floating-gate (FG) non-volatile memory at Bell Labs [1]. After that, all kinds of non-volatile memory were invented and were applied in our daily life. Read Only Memory (ROM) was the 1.

(15) early products of non-volatile memory. This memory programs its data in its fabrication process and it has the advantages of cheap and high density. Hence, ROM was applied widely in all kinds of electric products such as personal computer, printer, video game and etc. However, this memory is not convenient, because if we want to change one bit, we need a new mask. Latter, one kind of memory called Programmable Read Only Memory (PROM) was invented, which didn’t need specific mask for specific function because the data was written in after the whole ic chip fabrication. Hence, it has the advantage of fast production. Although PROM can be programmed according to the need of consumers, but the data in the memory can not be erased by the users. In order to solve the program, Electrically Programmable Read Only Memory (EPROM) was invented, and it programs the memory cell by electrical method such as channel hot electron (CHE). However, EPROM can’t erase by electrical method, and it need to illuminate the UV light to erase it. Because of this reason, a quartz window is necessary on the package of the EPROM. Thus, quartz window package lead to the expansive package cost and make EPROM inconvenient. The appearances of Electrically Erasable Programmable Read Only Memory (EEPROM) solve the program of EPROM that described above. It can both program and erase by electrical method, but it need a select transistor to achieve the advantage. Hence, the density of EEPROM is lower than EPROM and EEPROM is more expensive. Flash memory follows the basic structure of EEPROM without select transistor. Unlike EPROM and EEPROM, flash memory cell provides single-cell electrical program and fast simultaneous block electrical erase [2]. Thus, a small cell size is combined with a fast in-system erase capability, and flash memory has the advantage of long life time, low production cost, low power, and robust flash systems. Hence, 2.

(16) flash memory is good for consumer electric products such as mobile phone, pager, digital cameras, MP3 player, PDA and etc. Table1 compare the characteristics of the flash memory with PROM, EPROM, and EEROM [3]. The basic concept of Floating-gate (FG) non-volatile memory (as Figure.1(a)) is a MOSFET with a modified gate stack structure that has a control gate (CG) and a floating gate (FG) embedded in a dielectric material such as silicon dioxide (SiO2), and both the CG and FG is conductor. The MOSFET operated as a switch with the control gate modulating the electron current flow between the source and drain. The memory storage element is the isolated floating gate disconnected from the terminal voltage. It sits between the control gate and the channel. The storage charge will affect the threshold voltage. By the different threshold voltage, we can define that the operation voltage Vg of memory cell is at the middle of the two threshold voltage. Thus, the programming state can be determined by measuring the current in the MOSFET with the operation voltage Vg (as Figure.2). Because of manipulating electric field to control the data to program or erase, the tunneling oxide should be thin enough to let charge inject into the floating gate. However, if the tunneling oxide is too thin or it has local defect or it has stress induce leakage current (SILC) path (as Figure. 1(b)), it will lead to leak charge. And the floating gate is also a conductor, so it will lead to whole charge leak out. This is a big problem for data retention. In order to solve the problem, one method is that it can replace the conductive floating gate with insulator which has a large mount of trap sites (as Figure. 3), such as SiN3 [4], Al2O3 [5], HfO2 [6], ZrO2 [7] and some high-K materials [8]. This method uses the materials which are easy to trap charge to increase the capability of charge retention, and it stores the charge in the discrete trap site. Because the charge in the trap site will not interact, the local defect of tunneling oxide will not leak out all of the 3.

(17) charge. Besides, the high-k materials have higher dielectric constant. So they can reduce the equivalent oxide thickness of the gate stack and reduce the operation voltage. Another method is that it can replace the conductive floating gate with nanocrystals as charge storage node, such as Si nanocrystals [9], Ge nanocrystals [10], HfO2 nanocrystals [11], and metal nanocrystals [12,13] (as Figure. 4). Nanocrystals memory has separate and discontinuous charge storage node. Hence, the migration of charge in horizontal and vertical direction can be suppressed by the silicon dioxide. Thus, nanocrystals flash memory has good charge retention. Moreover, it can have thinner tunneling oxide and smaller operation voltage with good programming and erasing speed. So, it meets the requirements of low power and voltage in VLSI.. 1-2 Motivation Future high density flash memories for stand-alone data storage application require device with minimum feature smaller and smaller, such as 50nm. In this range it has been shown that silicon-oxide-nitride-oxide-silicon (SONOS) structure have promising scaling behavior in tri gate structure [14,15] due to the improved electrostatic control of the channeling region. And Lee et al. has reported that a high-k nanocrystal charge-trapping layer can be fabricated by annealing high-k silicate materials, such as HfSixOy. After applying a rapid thermal anneal to the silicates, phase-separation happens. HfO2 nanocrystals [16] are formed and surrounded by SiO2. The stored charges will be trapped in or around the nanocrystals and isolated by silicon dioxides. Hence, less opportunity of charge loss is expected and a local defect of tunnel oxide won’t cause a severe charge loss. With such a nanocrystal structure as the charge-trapping layer, the retention of. 4.

(18) nonvolatile memories can be further improved. Because of all of above, we want to fabricate a device with a gate length 60nm by using tri gate structure and HfO2 nanocrystals as charge trapping layer. And the device show that it has large memory window, good program /erase speed, good retention, and good endurance. . In floating gate device, there are some problems in the scaling down. The floating gate device should use thick tunneling oxide, which is required to guarantee long charge retention time. Thus, they need high voltage operation for program and erase. Recently, silicon-oxide-nitride-oxide-silicon (SONOS) structure of charging device become attractive because they do not have planar scaling problem for floating gate isolation and they show good retention characteristic due to the discrete and deep traps in the nitride trapping layer. Therefore, low voltage operation by application of thin tunneling oxide is practicable [17]. Besides, the localized carrier trapping in the trapping layer makes a 2-bits operation possible. From all of above, we want to fabricate a high performance nonvolatile memory with a high-k charge-trapping layer. The high-k dielectric material are La2O3 and Pr2O3. These high-k layer replace the silicon nitride layer in the SONOS structure. These materials provide high trapping state densities and deep trapping levels, therefore they can enhance the retention of nonvolatile memories. The charge-trapping efficiency can be improved, and larger operation window can be achieved. The application of high-k materials can further reduce the operation voltage and potentially can help memory device scaling.. 1.3 Organization of the Thesis 5.

(19) In the following section, we will show our research efforts. In chapter 2, the electrical characteristics and fabrication process of 55nm tri-gate flash memory with HfO2 nanocrystal trapping layer will be proposed. The Experiment results reveal that the program/erase speed and endurance of our device have good performance. In chapter 3, the electrical characteristics and fabrication process of Characteristics of SONOS-type Memories by Using Lanthanum Oxide Trapping Layers will be proposed. The Experiment results reveal that the program/erase speed and endurance of our device have good performance. In chapter 4, the electrical characteristics and fabrication process of Characteristics of SONOS-type Memories by Using Praseodymium Oxide Trapping Layers will be proposed. The Experiment results reveal that the program/erase speed and endurance of our device have good performance. At the end of this thesis, we will make a conclusion in chapter 4.. 6.

(20) References: [1] D. Kahng and S. M Sze, Bell Syst. Tech,J.,46,1288 (1967). [2] A.THean, and J.-p. Leburton, “Flash memory: toward single-electronics,”IEEE Potentials, pp.35-41, OCT./Nov.,2002 [3] Fujio Masuoka, Masamichi Asano, Hiroshi Iwahashi, Teisuke komuro, Norriyoshi Tozawa,. and. shinichi. Tanaka. “A. 256-kbit. Flash. E2PROM. Using. Triple-Polysilicon Technology,” IEEE Journal of Solid-State Circuit vol.sc-22, no.4, AUG., 1987. [4] M. H. White and D. Adams, “Low-Votage SONOS Nonvolatile Semiconductor Memory (NVSMs),” GOMAC 2000. [5] A.fernandes, B. DeSalvo, P. Masson, G. Pananakakis, G. Ghibuado, T. Baron, N.Buffet, D.Mariolle, B. Gullaumot, “Electrical Characteristic of Memory-cell Structure Emploting Ultra-thin Al2O3 Film as Storage Node”, Proc.ESSDERC 2001, pp. 139-142 [6].Yan-Ny Tan, Wai-kin Chim, Byung jin Cho, and Wee-Kiong Choi, “Ovre-Erase Phenomenon in SONOS-Type Flash Memory and its Minimization Using a Hafnium Oxide Charge Storage Layer,” IEEE Electron Device, vol. 51, no. 7.July 2004. [7] Vladimir A. Gritsenko,” Design of SONOS Memory Transistor for Terabit Scale EEPROM,” Electron Devices and Solid-State Circuits, 2003 IEEE Conference on 16-18 Dec. 2003 Page(s):345 - 348 [8] T. Sugizaki, M. Kobayashi, M. Ishidao, H. Minaka, /m. /yamaguchi, Y. Tamura, Y. Sugiyama, T. Nakanishi, and H. Tanaka, “Novel multi-bit SONOS type flash memory using a High-k charge trapping layer,” in Proc. VLSI Symp. Technology Dig. Technical Paper, 2003, pp.27-28.. 7.

(21) [9] M. L. Ostraat, J. W. De Blauwe, M. L. Green, L.D. Bell, M. L. Brongersma, J. Casperson, R. C. Flagan, and H. A. Atwater, “Synthesis and characterization of aerosol silicon nanocrystal nonvolatile floating-gate memory device,” Appl. Phys. Lett., vol 79, pp. 433-435, 2001. [10] P. W. Li, W. M. Liao, S.W. Lin, P.S.Chen, S.c. Lu, and M.-J. Tasi, “Formation of atomic. scale. germanium. quantum. dots. by. selective. oxidation. of. SiGe/Si-on-insulator,” Appl. Phys. Lett., vol.83, pp.4628-4630, 2003. [11] Yu-Hsien Lin, Chao-Hsin Chien, Ching-Tzung Lin, Chun-Yen Chang, and Tan-Fu Lei, “High-performance nonvolatile HfO2 nanocrystal memory,” IEEE Electron Device Letters, vol.26, Page:154 - 156 Issue 3, March 2005. [12] Z. Liu, C. Lee, V. Narayanan, G. Pei, and E. C. Kan, “Metal nanocrystal memory, part I: Device design and fabrication,” IEEE Electron Device, vol. 49, pp. 1606-1613, Sept. 2002. [13] Z. Liu, C. Lee, V. Narayanan, G. Pei, and E. C. Kan, “Metal nanocrystal memory, part II: Device characteristics,” IEEE Electron Device, vol. 49, pp. 1614-1622, Sept. 2002. [14] Peiqi Xuan, Min she, Bruce Harteneck, Alex Liddle, Jeffery Bokor and Tsu-Jae King, “FinFET SONOS flash memory for embedded application,” in IEDM Tech. Dig., 2003, pp.609-6013. [15] M. specht, R. Kommling, L. Dreeskornfeld, W. Weber, F. Hofmann, D. Alvarez, J. Kretz, R. J. Luyken, W. Rosner, H. Reisinger, E. Landgraf, T. Schulz, J. Hartwich, M. Stadele,V. Klandievski, E.Hartmann, and L. Risch, ”Sub-40nm tri-gate charge trapping nonvolatile memory cells for high-density application,“ VLSI Symp. Technology Dig. Technical Paper, 2004, pp.244-245 [16] Yu-Hsien Lin, Chao-Hsin Chien, Ching-Tzung Lin, Chun-Yen Chang, and Tan-Fu Lei, “High-performance nonvolatile HfO2 nanocrystal memory,” IEEE 8.

(22) Electron Device Lett, vol.26, Page:154 - 156 Issue 3, March 2005. [17] H. Wann and C. Hu, ”High–endurance ultra thin tunnel oxide in MONOS device structure for dynamic memory application,” IEEE Electron Device Lett., vol.16, pp.491-493, Nov.1995.. 9.

(23) Package Erase Time. Program Time Cell Area Eraser Structure. UVEPROM. PROM. EEPROM. Ceramic with window. Plastic. Plastic. Plastic. 20 min. No erase. 1 ms. 100 ms. <1 ms. <1 ms. <1 ms. Small. Small. UV light. No need. Double Poly-Si. Double Poly-Si. Large. Electrically Double Poly-Si. FLASH. 200 μs. Small. Electrically Triple Poly-Si. Table.1-1 The comparison of the flash memory with PROM, EPROM, and EEROM. 10.

(24) CG. Blocking Oxide. FG. e-. e. Source. e-. Drain. e-. mobile Charge. ee-. e-. conductors Tunneling Oxide Si substrate. SILC paths. (a). (b). Fig. 1-1 The basic concept of Floating-gate (FG) non-volatile memory. Id. High current is erased state. Low current is programmed state Sense memory state. Vg. Fig. 1-2 The basic concept of the reading of the memory cell. 11.

(25) Poly-gate. Blocking Oxide e-. Immobile Charge. e-. e-. High k material Source. e-. Drain. e. e-. Tunneling Oxide Si substrate. Fig. 1-3 The basic concept of SONOS-type non-volatile memory. Poly-gate. Blocking Oxide 50~110Å Oxide e-. ●●●●●. Source. Immobile Charge. e-. e-. Drain. e-. e-. Tunneling Oxide. Isolates conductors. Si substrate. Fig. 1-4 The basic concept of nanocrystal non-volatile memory. 12.

(26) Chapter 2 Characteristic of tri-gate Flash Memory with HfO2 nanocrystal Trapping Layer 2.1 Introduction With the development of semiconductor industry, high density flash memories for stand-alone data storage application require device with minimum feature smaller and smaller, such as 50nm. However, the conventional floating gate (FG) nonvolatile memory (NVM) devices use a poly-Si film as charge storage layer in which the information is stored by injecting charges from the inversion or accumulation layer of a MOSFET. Improvements of their performance are based on the shrinkage of the technology and, such as the reduction of the gate length and the thickness of the tunnel oxide. However, further scaling of the floating gate nonvolatile memories is facing severe reliability issues such as the difficulty to maintain long data retention times. In order to overcome the scaling limit, the idea of the discrete-trap mechanism has been proposed. It means that we can replace the floating gate of nonvolatile memories by many discrete trapping centers, which can be made by natural traps in an appropriate insulator such as a nitride layer in SONOS [1][2] memories or by nanocrystals. And it also has been shown that tri gate structure [3] can suppress short channel effects and drain-induced barrier lowering (DIBL) due to the improved electrostatic control of the channeling region. And Lee et al. [4] has reported that a high-k nanocrystal charge-trapping layer can be fabricated by annealing high-k silicate materials, such as HfSixOy. After applying a 13.

(27) rapid thermal anneal to the silicates, phase-separation happens. HfO2 nanocrystals [] are formed and surrounded by SiO2. Hence with the nanocrystals charge trapping layer, the stored charges will be trapped in or around the nanocrystals and isolated by silicon dioxides. Hence, less opportunity of charge loss is expected and a local defect of tunnel oxide won’t cause a severe charge loss. With such a nanocrystal structure as the charge-trapping layer, the retention of nonvolatile memories can be further improved. In this work, an ONO sandwich structure gate-dielectric stack with HfO2 nanocrystals trapping layer is form on Si in order to fabricate a tri-gate memory device. And the device show that it has large memory window, good program /erase speed, good retention, and good endurance.. 2-2 Experimental Figure 2-1 schematically depicts the process flow of the proposed flash memory. First, the active region was patterned by E-beam lithography and etching system. Then, a 2-nm tunneling oxide was grown at 1000°C in vertical furnace system. The trapping layer of amorphous HfSiOx silicate layer was deposited by co-sputtering method with pure Silicon (99.9999% pure) and pure Hafnium (99.9% pure) in the oxygen and argon gas ambient. Then, a blocking oxide of about 85nm was then deposited by plasma-enhanced chemical vapor deposition (PECVD) system. Subsequently, 50-nm amorphous silicon (a-Si) gate and 50-nm SiN3 were deposited by LPCVD. The a-Si gate layer was divided into in-situ n+ doped gate. The dopant of in-situ n+ doped a-Si gate was phosphorus. After gate patterning, the remaining oxide on source/drain regions was removed by diluted HF. Then, a self-aligned implantation was used to perform the n+ source/drain with As+ to dose 5 × 1015 cm-2. 14.

(28) and energy 20 keV, tilt 30o.After implantation, and a 50-nm TEOS oxide sidewall spacer was formed by deposition and etching of TEOS oxide. After that the dopants were activated by RTA at 950°C for 10s and at the same time, HfSiOx silicate layer was converted into the separate HfO2 and SiO2 phase. Finally, the nitride layer was etched by H3PO4 solution.. 2-3 Results and Discussion 2.3.1 Material Analysis of HfO2 Nanocrystals Figure 2-2 shows the scanning electron microscopy (SEM) image and Figure 2-3 shows cross-section-view high-resolution transmission microscopy (HRTEM) image of the HfO2 nanocrystals tri-gate device. Clearly, the gate length is about 55nm from the HRTEM image and the thicknesses of the tunnel oxide and blocking oxide layer are 2.2nm, 8nm, respectively. The trapping layer thicknesses are 7.9nm and the nanocrystals were separated in two dimensions within the SiO2; in which the average distance is >5 nm. This isolation of the nanocrystals prevents the formation of effective conductive paths between adjacent nodes. The mechanism responsible for the formation of HfO2 nanocrystal is through the phase separation of hafnium silicate into a crystallized structure [5]. For the Hf-silicate layer, the compositions within metastable extensions of the spinodal are unstable and HfO2 nanocrystal will be formed and enclosed by SiO2 after cooling down from RTA processing. All devices described in this paper had dimensions of L = 50nm.. 2.3.2 Characteristics of Fresh Devices Figure 2-4 shows the Ids-Vgs curves of the tri-gate HfO2 nanocrystal tri-gate memory devices with programming time of 0.3. Fowler-Nordheim tunneling injection was employed for programming and erasing. A memory window of about 1.5V can be 15.

(29) achieved at the Vg=8V program operation. Program characteristics of different pulse width for different operation conditions are shown in Figure. 2-5. We employed channel hot-electron injection and Fowler-Nordheim tunneling injection in Figure 2-5(a) and Figure 2-5(b). The “Vt shift” is defined as the threshold voltage change of a device between the written and the erased states. For channel hot-electron injection with Vg=11V Vd=4V, relatively high speed (0.1ms) programming performance can be achieved with a memory window of about 1.8V. For Fowler-Nordheim tunneling injection with Vg=11V, a memory window of about 1.8V can be achieved with 1ms pulse width. Hence, the speed of channel hot-electron injection is faster that of Fowler-Nordheim tunneling injection. Meanwhile, Figure 2-6 displays the erase. characteristics as a function of various operation voltages. Again, excellent erase speed of around 1 ms can be obtained with Vg=-3V Vd=4V for band to band hot hole injection. The retention characteristics of the HfO2 nanocrystal tri-gate memory devices at room temperature (T=25°C) and higher temperature (T=85°C, 125°C) are illustrated in Figure 2-7. The retention time can be up to 108 seconds for 17% charge loss at room temperature and 40% charge loss and 65% charge loss for the 85°C and 125°C s conditions. We ascribe these results to the combining effects of the tight embrace of HfO2 nanocrystals by SiO2-rich matrix and the sufficiently deep trap energy level [6,7]. As a result, superior retention characteristic of the charge storage can be procured[8-11]. The endurance characteristics after 104 P/E cycles are also shown in Figure 2-8. The programming and erasing conditions are Vg=11V Vd=4V for 1ms and Vg=-3V, Vd=4V for 1ms, respectively. Slight memory window narrowing has been displaye and the individual threshold voltage shifts in program and erase states become visible after 103 cycles.. This trend indicates the formation of operation-induced trapped 16.

(30) electrons. Certainly, this is intimately related to the use of ultra-thin tunnel oxide and very minute amount of residual charges in the HfO2 nanocrystals after cycling. The cycling retention is an important issue for flash memory. Therefore, we studied the retention loss behavior of the device before and after 10K cycling. Figure 2-9 show the cycling retention behavior of the cell at room temperature (25oC).As we can see in Figure 2-9, the charge loss behavior of the device with 10K cycling is more serious than the device without 10K cycling under room temperature condition. The retention time can be up to 108 seconds with 70% charge for cycling device. We ascribe these results to that the tunneling oxide was damage after10K P/E cycling. Hence, the capability of charge storage was decreased.. 2.3.3 Characteristics of 2-bit operation Figure 2-10 demonstrates the feasibility of performing two-bit operation with our HfO2 nanocrystal tri-gate memories through forward and reverse read scheme in a single cell. From the Ids–Vgs curves, it is clear that we could employ forward and reverse reads to detect the information stored in the programmed bit1 and bit2, respectively. Table 2-1 summarizes the bias conditions for two-bit operation. Figure 2-11 shows the 2-bit retention characteristics of the HfO2 nanocrystal tri-gate memories. The retention time can be up to 108 seconds with 0.8V memory window between programmed bit-1 and erased bit-2. We can see that charge loss occurred for programmed bit-1 and charge gain for erased bit-2. This suggests that there is lateral migration of trapped electron.[12]. 2.3.4 Disturbance Figure 2-12 demonstrates the read disturbance induced erase-state threshold voltage instability in a localized HfO2 nanocrystal tri-gate Flash memory cell under several operation conditions. For two-bit operation, the applied bitline voltage in a 17.

(31) reverse-read scheme must be sufficiently large (>1.5 V) to be able to “read through” the trapped charge in the neighboring bit. The read-disturb effect is the result of two factors: the word-line and the bit-line. The word-line voltage during read may enhance room temperature (RT) drift in the neighboring bit [12]. On the other hand, a relatively large read bit-line voltage may cause unwanted channel hot-electron injection and, subsequently, result in a significant threshold voltage shift of the neighboring bit. In our measurements, the gate and drain biases were applied and the source was grounded. The results demonstrate clearly that almost no read disturbance occurred in our HfO2 nanocrystal tri-gate Flash memory under low-voltage reading (Vg =1.5 V; Vd = 1.5 V). For a larger memory window, we found that only a small read disturbance can be observed after operation at Vd = 2 V after 1000 s at 25 °C. Figure 2-13 shows the programming drain disturbance of our HfO2 nanocrystal tri-gate Flash memory. Drain disturbance may occur during programming for the cells sharing a common bit-line while one of the cells is being programmed and gate disturbance may occur during programming for the cells sharing a common word-line while one of the cells is being programmed as in Figure 2-14. Two different drain voltages (Vd = 3 and 4 V) were applied in the programming drain disturbance measurements at room temperatures. We observed that a 1.5V drain disturb was observed after programming at a value of Vd of 4V under T = 25 °C and after stressing for 1000 s. Figure 2-15 shows the gate disturbance characteristics in the erasing state. Because we can program the device by Fowler-Nordheim tunneling injection, the gate disturbance will not be too small. Hence,we observed a threshold voltage shift of 2.5 V under the following conditions: Vg = 11 V; Vs = Vd = Vsub = 0 V; stressed for 1000 s. Hence, a non-negligible current will be present in the tunnel oxide when a voltage of 11 V is applied to the gate electrode.. 18.

(32) 2.4 Summary In this chapter, we have proposed a novel simple, reproducible, reliable technique for preparation of 55nm high density HfO2 nanocrystals tri-gate memory using spinodal decomposition of hafnium silicate on SOI. It has good characteristics in terms of large memory windows, high speed program/erase, good retention time, excellent endurance, and 2-bit operation. With these superior performance, we believe that nano-scale HfO2 nanocrystal flash memory on SOI is the candidates used for the high density storage application.. 19.

(33) Reference [1] B. Eitan, P. Pavan, I. Bloom, A. Efraim, A. Frommer, and d. Finzi, “NROM: A novel localized trapping, 2-bit nonvolatile memory cell,” IEEE Electron Device Lett., vol. 21, pp. 543-545, Nov. 2000. [2] M. H. White, D. A. Adams and J. Bu, “On the go with SONOS,” IEEE Circuits Devices Mag., vol. 16, pp. 22-31, July 2000. [3] Peiqi Xuan, Min She, Harteneck. B., Liddle. A., Bokor. J., King. T.-J.,” FinFET SONOS flash memory for embedded applications” IEEE Electron Devices Meeting, 2003. IEDM '03 Technical Digest. 8-10 Dec. 2003 pp:26.4.1 - 26.4.4 [4] Yu-Hsien Lin, Chao-Hsin Chien, Ching-Tzung Lin, Chun-Yen Chang, and Tan-Fu Lei, “High-performance nonvolatile HfO2 nanocrystal memory,” IEEE Electron Device Lett, vol.26, Page:154 - 156 Issue 3, March 2005. [5] Susanne Stemmer, Zhiqiang Chen, Carlos G. Levi, Patrick S. Lysaght, Brendan Foran, John A. Gisby, and Jeff R. Taylor, “Application of metastable phase diagrams to silicate thin films for alternative gate dielectrics,” Jpn. J. Appl. Phys., vol. 42, pp. 3593-3597, 2003. [6] W.J. Zhu, Tso-Ping Ma, Takashi Tamagawa, J. Kim, and Y. Di, “Current Transport in Metal/Hafnium Oxide /Silicon Structure”, IEEE Electron Device Lett., vol. 23, no. 2, pp. 97-99, Feb. 2002. [7] Barbara De Salvo, Gerard Ghibaudo, Georges Pananakakis, Gilles Reimbold, Francois Mondond, Bernard Guillaumot, and Philippe Candelier, “Experimental and theoretical investigation of nonvolatile memory data-retention,” IEEE Trans. Electron Devices, vol. 46, no. 7, pp. 1518-1524, Jul., 1999. [8] T. S. Chen, K. H. Wu, H. Chung, and C. H. Kao, “Performance improvement of SONOS memory by bandgap engineer of charge-trapping layer,” IEEE Electron. 20.

(34) Device Lett., vol. 25, no. 4, pp. 205-207, Apr. 2002. [9] “Test and test equipment” in The International Technology Roadmap for Semiconductors (ITRS), 2001, pp. 27-28. [10] T. Sugizaki, M. Kobayashi, H. Minakata, M. Yamaguchi, Y. Tamura, Y. Sugiyama, H. Tanaka, T. Nakanishi, and Y. Nara, “New 2-bit/Tr MONOS type flash memory using Al2O3 as charge trapping layer,” in Proc. IEEE Non-Volatile Semiconductor Memory Workshop, Feb. 2003, pp. 60-61. [11] Y. N. Tan, W. K. Chim, W. K. Choi, M. S. Joo, T. H. Ng, and B. J. Cho, “High-K HfAlO charge trapping layer in SONOS-type nonvolatile memory device for high speed operation,” in IEDM Tech. Dig., 2004, pp. 889-892. [12]T. Sugizaki, M. Kobayashi, M. Ishidao, H. Minakata, M.Yamaguchi, Y. Tamura, Y. Sugiyama, T. Nakanishi, H. Tanaka,” Novel multi-bit SONOS type flash memory using a high-k charge trapping layer” VLSI Technology, 2003. Digest of Technical Papers. 2003 Symposium, pp.27 – 28, June 2003 [13] W. J. Tsai, C. C. Yeh, N. K. Zous, C. C. Liu, S. K. Cho, T. Wang, S. C. Pan, and C. Y. Lu, “Positive oxide charge-enhanced read disturb in a localized trapping storage flash memory cell,” IEEE Trans. Electron Devices, vol. 51, no. 3, pp. 434-439, Mar. 2004.. 21.

(35) Si SiO2 Si. (a) The active region was patterned by E-beam lithography on SOI wafer. Si SiO2. Si. (b) Tunnel oxide was grown at 1000°C in furnace. HfSiOx. Si SiO2. (c) HfSixOy deposited by sputter method as trapping laye. 22.

(36) SiO2. Si SiO2. (d) blocking oxide then deposited by PECVD followed by 900°C in N2 densification. Poly-Si. Si SiO2. (e) Poly-Si deposited to serve as the gate electrode by LPCVD. 23.

(37) SiN. Poly-Si. Si SiO2. (f)SiN deposited as hard mask. SiO2 spacer SiN. Poly-Si. Si SiO2. (g) Gate electrode patterned and oxide spacer was formed. 24.

(38) As ion implantation. SiN. Poly-Si. Si SiO2. (h) source/drain implanted by self-aligned As ion implantation. Poly-Gate. S. Si. D. SiO2. (i) Dopants were activated at 950oC and convert HfSixOy into HfO2 dots 25.

(39) SiO2 spacer. Poly PolySi Si. HfO2. SiO2 SiO2 S. Si. D. SiO2 Si. (j) Fig.2- 1 Process flow of the flash memory and the cross-section of the flash memory. 26.

(40) Fig.2-2 show the top view scanning electron micrograph of the memory devic. 27.

(41) Gate. Source. Drain. 50nm 3(a). HfO2 nanocrystal 80Å. 79Å 22Å. 5nm 3(b) Fig.2-3a and 3b show the high-resolution TEM image of cross section and the ONO structure gate-dielectric stack are clearly seen. The gate length is around 55nm. Fig 3b show the high-resolution TEM image of the ONO-type gate stack The thickness of tunneling oxide, trapping layer, and blocking oxide are 22, 79, 80Å, respectively.. 28.

(42) Id(A). 10-5 10-6 10-7 10-8 10-9 10-10 10-11 10-12 10-13 10-14 10-15 -2. Fresh Prog Vg=8V t=0.3sec Erase Vg=-8V t=0.3sec. -1. 0. 1. 2. 3. Vg(V). Fig. 2-4 show the Id-Vgs curves of the memory in the programmed/erased state. The programming and erasing times are 0.3 sec and a memory window of 2V can be achieved. 29.

(43) 4. Vt shift (V). 3. Vg=8V, VD=3V Vg=8V, Vd=4V Vg=10V, Vd=4V Vg=11V, Vd=4V. 2 1 0 -1 10-7 10-6 10-5 10-4 10-3 10-2 10-1 100 101. Time (sec) 5(a) *. 4. Vt shift (V). 3. Vg=8V Vg=10V Vg=11V. 2 1 0. -1 10-6 10-5 10-4 10-3 10-2 10-1 Time (sec). 100. 101. 5(b) Fig.2-5 Program characteristics of the memory devices with (a) CHE and (b) F-N programming .(a) A memory window of about 1.8V can be achieved with Vg=11V Vd=4V, and time=0.1ms for CHE programming operation. (b). A memory window of about 1.8V can be achieved with Vg=11V time=1ms for F-N programming operation. 30.

(44) Vt shift (V). 0 -1 -2 -3 -4 -5 -6. Vg=-3V, Vd=3V Vg=-3V, Vd=4V Vg=-4V, Vd=3V. -7 10-7 10-6 10-5 10-4 10-3 10-2 10-1 100 101. Time (sec). Vt-shift (V). 6(a). 0.0 -0.2 -0.4 -0.6 -0.8 -1.0 -1.2 -1.4 Vg=-8V Vg=-10V -1.6 Vg=-11V -1.8 -2.0 10-6 10-5 10-4 10-3 10-2 10-1. 100. 101. pulse width (s) 6(b) Fig.2-6 Erase characteristics of the memory devices with (a) BTBHH and (b) F-N erasing conditions. The speed of BTBHH is faster than that of F-N method. 31.

(45) Normalized Vt shift %. 120 100 80 60 40 20. 25oC 85oC 125oC. 0 100 101 102 103 104 105 106 107 108. Time (sec) Fig.2-7 Retention characteristics of HfO2 nanocrystal tri-gate memory devices at T=25°C, 85°C and 125°C. Very low charge loss is seen even after 104 seconds. 32.

(46) 3 Erase State Vg=-3V, Vd=4V t=1ms Program State Vg=11V, Vd=4V t=1ms. Vt (V). 2 1. 1.1V. 0 -1 100. 101. 102. 103. 104. P/E cycles Fig. 2-8 Endurance characteristics of the HfO2 nanocrystal tri-gate flash memory devices. Slight degradation is found after 103 P/E cycles. 33.

(47) Normalized Vt shift %. 100 80 60 40 20. Fresh 25oC 10K P/E Cycles 25oC. 0 100 101 102 103 104 105 106 107 108. Time (sec) Fig.2-9 Retention characteristics of HfO2 nanocrystal tri-gate memory devices with cycling and fresh at T=25°C.. 34.

(48) Id or Is (A). 10-4 10-5 10-6 10-7 10-8 10-9 10-10 10-11 10-12 10-13 10-14 10-15. Erase state Bit1 Program Bit1 Forward read Vd=1.5V Bit2 Program Bit2 Forward read Vs=2V. -4. -2. 0. Vg (V). 2. 4. Fig. 2-10 Ids-Vgs curve of the memory in the 2-bit per cell operation. ; forward read and reverse read for programmed bit1 and programmed bit2. Program Erase Read Bit1 Vg 8V. -3V. 1.5V. Vd 4V. 4V. 0V. Vs 0V. 0V. >1.5V. -3V. 1.5V. Vd 0V. 0V. >1.5V. Vs 4V. 4V. 0V. Bit2 Vg 8V. Table.2-1 Operation principles and bias conditions utilized during the operation of the HfO2 nanocrystal tri-gate Flash memory cell. 35.

(49) 4.0. Charge loss. 3.5 3.0. Vt (V). 2.5. Programmed bit-1 Erased bit2 25oC. 0.8V. 2.0 1.5. Charge gain. 1.0 0.5. 0.0 100 101 102 103 104 105 106 107 108. Time (sec) (a). Laterl. G. migration. Block Oxide HfO2 dot. e-. Tunnel Oxide (b) Fig.2-11 Retention characteristics of the memory devices with Programmed bit-1 and Erased bit-2 at T=25°C. (b) show the schematic of Lateral migration.. 36.

(50) Erase state Vt shift (V). 1.0 0.5. Vg=1.5V,Vd=1V Vg=1.5V,Vd=1.5V Vg=1.5V,Vd=2V. 0.0. -0.5 -1.0 100. 101. 102. Time (sec). 103. Program state Vt shift (V). Fig. 2-12 Read disturbance characteristics of the HfO2 nanocrystal tri-gate flash memory. No significant Vt shift occurred for Vd < 2, even after 1000 s at 25 °C. 2 Vg=0V, Vd=3V Vg=0V, Vd=4V. 1 0 -1 -2 100. 101. 102. 103. Time (sec) Fig. 2-13 Drain disturbance characteristics of the HfO2 nanocrystal tri-gate flash memory cells. After 1000 s at 25 °C, a 1.5V drain disturb was observed for Vd=4V condition. 37.

(51) Drain (BL). Drain disturbance. Gate (WL). Program Gate disturbance. Erase state Vt shift (V). Fig. 2-14 The schematic illustration of disturb condition. When the cell is programming, those cell of the same word-line and the same bit-line are the gate disturb and drain disturb, respectively. 4 3 2 1 0. Vg=8V Vg=10V Vg=11V. -1 -2 1. 10. 100. 1000. Time (sec) Fig. 2-15 Gate disturbance characteristics of the memory devices. A threshold voltage shift of 2.5 V occurred after stressing at Vg = 11 V and Vs = Vd = Vsub = 0 V for 1000 s. 38.

(52) Chapter 3 Characteristic of SONOS-type Flash Memory by using La2O3 trapping layer 3.1 Introduction In the field of nonvolatile semiconductor memory, there have been essentially two types of device structure. One is the floating gate structure and the other is the charge trap structure. The floating gate device store charge in the polycrystalline silicon as free charge with a continuous distribution in the conduction. In floating gate device, there are some problems in the scaling down. The floating gate device should use thick tunneling oxide, which is required to guarantee long charge retention time. Thus, they. need. high. voltage. operation. for. program. and. erase.. Recently,. silicon-oxide-nitride-oxide-silicon (SONOS) structure of charging device become attractive because they do not have planar scaling problem for floating gate isolation and they show great potential for achieving high program/erase speed, low programming voltage and low power performance [1]. Besides, the localized carrier trapping in the trapping layer makes a 2-bits operation possible. However, many concerning issues are still presented for SONOS memories. In recent years, many papers have ever shown Al2O3[2]trapping layer as the potential candidate for replacing Si3N4 [3] and also demonstrated different kinds of high-k[4-7] material to provide charge storage for the non-volatile memories. In this work, we fabricate a high performance nonvolatile memory with a high-k charge-trapping layer. The high-k dielectric material is La2O3. This high-k layer replaces the silicon nitride layer in the SONOS structure. These materials provide 39.

(53) high trapping state densities and deep trapping levels, therefore they can enhance the retention of nonvolatile memories. The charge-trapping efficiency can be improved, and larger operation window can be achieved. The application of high-k materials can further reduce the operation voltage and potentially can help memory device scaling. It has good characteristics in terms of considerably large memory window, high speed program/erase, good retention time, good endurance, and good disturbance.. 3-2 Experimental Figure 3-1 schematically depicts the process flow of the proposed flash memory. First, the fabrication process of the Lanthanum oxide memory devices was started with LOCOS isolation process on a p-type, 5-10 Ω cm, (100) 150mm silicon substrates. First, a 2-nm-thick tunnel oxide was thermally grown at 1000°C in vertical furnace system. Next, a Lanthanum oxide layer was deposited by E-gun method with Lanthanum oxide targets. After that, the samples went through RTA treatment in O2 ambient at 900°C for 1 minute. A blocking oxide of about 7-nm-thick was then deposited by high density plasma chemical vapor deposition (HDPCVD) followed by 900°C 1 minute N2 densification process. Then, a 200-nm-tkick poly-Si was deposited to serve as the gate electrode by LPCVD. Then, the gate electrode was patterned and the source/drain (S/D) and gate were doped by self-aligned phosphorous ion implantation at the dosage and energy of 5x1015 ions/cm-2 and 20 KeV. Then the substrate contact was patterned and the sub-contact was implanted with BF2 at the dosage and energy of 5x1015 ions/cm-2 and 40 KeV. Aftetr these implantations, the dopants were activated at 950oC for 20 sec. The rest of the subsequent standard CMOS procedure were complete for fabricating the Lanthanum oxide high k memory devices.. 40.

(54) 3.3 Results and Discussion 3.3.1 Material Analysis of La2O3 SONOS type flash memory Figure 3-2 shows the cross-sectional HRTEM images of the gate stacks of the La2O3 flash memories. For SONOS-type structure, the thicknesses of the tunnel oxide and blocking oxide layer are 2nm, 7nm, respectively. The La2O3 trapping layer thicknesses are 4nm. All devices described in this paper had dimensions of L/W = 2/1 µm.. 3.3.2 Characteristics of Fresh Devices Figure 3-3 shows the Ids-Vgs curves of the La2O3 memory devices with programming time of 1s. Channel hot-electron injection and band-to-band hot-hole injection were employed for programming and erasing, respectively. A relatively large memory window of about 3V can be achieved at the Vg=Vd=10V program operation. Program characteristics as a function of pulse width for different operation conditions are shown in Figure 3-4(a). Both source and substrate terminals were biased at 0V. The “Vt shift” is defined as the threshold voltage change of a device between the programmed and the erased states. With Vd=Vg=9V, relatively high speed (100µs) programming performance can be achieved with a memory window of about 2.2V. Meanwhile, Figure 3-4(b) displays the erase characteristics as a function of various operation voltages. Again, excellent erase speed of around 10 ms can be obtained. More important, there is only a very small amount of over-erase observed. The reason is owing to the fact that the vertical electric field decreases with decreasing amount of trapped electrons in the trapping layer during erasing and the hole injection into the trapping layer will reduce significantly [9]. Figure 3-5 illustrates the retention characteristics for comparing different temperature (T=25°C, 85°C, 125°C). The retention time of the memory with La2O3 trapping layer 41.

(55) can be up to 108 seconds for 22% charge loss at room temperature, which is believed to be related to the deep trap energy level in the high-κ dielectrics [10]. But the retention got worse as the temperature increased, 40% charge loss and 65% charge loss for the 85°C and 125°C s conditions have obtained up to 108 seconds [11–15]. The endurance characteristics after 104 P/E cycles are also shown in Figure 3-6. The programming and erasing conditions are Vg=Vd=9V for 100µs and Vg=-3V, Vd=10V for 1ms, respectively. Slight memory window narrowing has been displaye and the individual threshold voltage shifts in program and erase states become visible after 102 cycles. This indicates the formation of operation-induced trapped electrons [16] in the tunneling oxide or the mismatch between the localized spatial distributions for injected electron and holes by using channel hot-electron programming and band-to-band hot-hole erasing. The uncompensated electron, residual charges in the La2O3 layer, will then cause the Vt to increase gradually over P/E cycling [17]. The cycling retention is an important issue for flash memory. Therefore, we studied the retention loss behavior of the device before and after 100K cycling[18,19]. Figure 3-7 shows the cycling retention behavior of the cell at room temperature (25oC) and high temperature (85oC). As we can see in Figure 3-7, the charge loss behavior of the device with 100K cycling is more serious than the device without 100K cycling under room temperature condition. The retention time can be up to 108 seconds with 50% charge for cycling device. We ascribe these results to that the tunneling oxide was damage after100K P/E cycling. Hence, the trap assisted tunneling increase and the capability of charge storage was decreased.. 3.3.3 Characteristics of 2-bit operation Figure 3-8 demonstrates the feasibility of performing two-bit operation [20] with our La2O3 memories through a forward read and reverse read scheme in a single cell.. 42.

(56) From the Ids–Vgs curves, it is clear that we could employ forward and reverse reads to detect the information stored in the programmed bit-1 and bit-2, respectively. The read operation was achieved using a reverse read scheme. Table 1 summarizes the bias conditions for two-bit operation. Figure 3-9 shows the 2-bit retention characteristics of the La2O3 trapping layer. The retention time can be up to 108 seconds with 1.2V memory window between programmed bit-1 and erased bit-2. We can see that charge loss occurred both for a programmed bit-1 and erased bit-2. This suggests that there is vertical migration of trapped electron [21].. 3.3.4 Disturbance Figure 3-10 shows the programming drain disturbance of our La2O3 Flash memory. Three different drain voltages (Vd = 5, 7 and 9 V) were applied in the programming drain disturbance measurements at room temperatures. We observed that a programming drain disturb exists (∆Vt < 1 V), even after programming at a value of Vd of 9V under room temperature and after stressing for 1000 s. Figure 3-11 shows the gate disturbance characteristics in the erasing state. Gate disturbance may occur during programming for the cells sharing a common word-line while one of the cells is being programmed. We observed a threshold voltage shift of 1 V under the following conditions: Vg = 10 V; Vs = Vd = Vsub = 0 V; stressed for 1000 s. The poor drain disturbance and gate disturbance was due to non-optimized process, such as thinner blocking oxide and tunneling oxide. Figure 3-12 show s the drain currents from a selected cell, in both programmed (Vg=4V, Vt=5.3V) and erased state (Vg=4V, Vt=3V), and the leakage current from an unselected cell (Vg=0V, Vt=3V) during the reading operation. The read current is more than six orders of magnitude larger than the leakage current, for read drain voltage up to 4V. Hence, the program state and erase state will not be erroneous. 43.

(57) judgment. Figure 3-13 demonstrates the read disturbance induced erase-state threshold voltage instability in a localized La2O3 trapping storage Flash memory cell under several operation conditions. For two-bit operation, the applied bitline voltage in a reverse-read scheme must be sufficiently large (>2 V) to be able to “read through” the trapped charge in the neighboring bit. The read-disturb effect is the result of two factors: the word-line and the bit-line. The word-line voltage during read may enhance room temperature (RT) drift in the neighboring bit. On the other hand, a relatively large read bit-line voltage may cause unwanted channel hot-electron injection and, subsequently, result in a significant threshold voltage shift of the neighboring bit. In our measurements, the gate and drain biases were applied and the source was grounded. The results demonstrate clearly that almost no read disturbance occurred in our La2O3 Flash memory under low-voltage reading (Vg = 4 V; Vd = 2 V). Even for a larger memory window, we found that almost no read disturbance (ca. 0.1 V) can be observed after operation at Vd = 4 V after 1000 s at 25 °C.. 3.4 Summary In this paper, we have investigated the memory effect on the performance of the La2O3 SONOS-type memories. It has good characteristics in terms of large memory windows, high speed program/erase, good retention time, excellent endurance, and 2-bit operation. Hence, La2O3 are the candidates used for the trapping layers for the SONOS-type memories.. 44.

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(60) Devices, vol. 46, no. 7, pp. 1518-1524, Jul., 1999. [16] Y. H. Lin, C. H. Chien, C. T. Lin, C. Y. Chang, and T. F. Lei, “High Performance Nonvolatile HfO2 Nanocrystal Memory,” IEEE Electron Device Lett., vol. 26, no. 3, pp. 154-156, Mar. 2005. [17] Yu-Hsien Lin, Chao-Hsin Chien, Ching-Tzung Lin, Ching-Wei Chen, Chun-Yen Chang, and Tan-Fu Lei, “High Performance Multi-bit Nonvolatile HfO2 Nanocrystal Memory Using Spinodal Phase Separation of Hafnium Silicate,” IEDM Technical Digest, pp. 1080-1802, Dec. 2004. [18] H. Kameyama, Y. Okuyama, S. Kamohara, K. Kubota, H. Kume, K. Okuyama, Y. Manabe, A. Nozoe, H. Uchida, M. Hidaka, and K. Ogura, “A New Data Retention Mechanism after Endurance Stress on Flash Memory,” in Reliability Physics Symposium Proceedings, 2000, pp. 194-199. [19] Wook H. Lee, Dong-Kyu Lee, Young-Min Park, Keon-Soo Kim, Kun-Ok Ahn, and Kang-Deog Suh, “A New Data Retention Mechanism after Endurance Stress on Flash Memory,” in Reliability Physics Symposium Proceedings, 2001, pp. 57-60. [20] Boaz Eitan, Paolo Pavan, Ilan Bloom, Efraim Aloni, Aviv Frommer, and David Finzi, “NROM: A Novel Localized Trapping, 2-Bit Nonvolatile Memory Cell,” IEEE Electron Device Lett., vol. 21, no. 11, pp. 543-545, Nov. 2000. [21]T. Sugizaki, M. Kobayashi, M. Ishidao, H. Minakata, M.Yamaguchi, Y. Tamura, Y. Sugiyama, T. Nakanishi, H. Tanaka,” Novel multi-bit SONOS type flash memory using a high-k charge trapping layer” VLSI Technology, 2003. Digest of Technical Papers. 2003 Symposium, pp.27 – 28, June 2003. 47.

(61) LOCOS. LOCOS. p-type si wafer. (a) LOCOS isolation on a p-type, 5-10 Ω cm, (100) 150mm silicon substrates. LOCOS. Tunneling oxide p-type si wafer. LOCOS. (b) Tunnel oxide was grown at 1000°C in furnace. LOCOS. La2O3 Tunneling oxide. LOCOS. p-type si wafer. (c) Lanthanum oxide layer deposited by E-gun method as trapping layer. 48.

(62) Blocking oxide LOCOS. La2O3 Tunneling oxide p-type si wafer. LOCOS. (d) RTA treatment in O2 ambient at 900°C, blocking oxide then deposited by HDPCVD followed by 900°C in N2 densification. Poly-Gate Blocking oxide LOCOS. La2O3 Tunneling oxide p-type si wafer. LOCOS. (e) Poly-Si deposited to serve as the gate electrode by LPCVD. 49.

(63) As Ion implantation. Poly-Gate. Blocking Oxide La2O3 LOCOS. LOCOS. p-type si wafer. (f) Gate electrode patterned and the source/drain and gate implanted by self-aligned phosphorous ion implantation. BF2 ion implantation. Photoresist Poly-Gate. Blocking Oxide La2O3 LOCOS. LOCOS. p-type si wafer. (g) Substrate contact patterned and the sub-contact was implanted with BF2 50.

(64) Poly-Gate. Blocking Oxide La2O3 LOCOS. LOCOS. Source. p-type si wafer. Drain. (h) Dopants were activated at 950oC. Poly-Gate. Blocking Oxide La2O3 LOCOS. LOCOS. Source. p-type si wafer. (i)Deposition of passivation. 51. Drain.

(65) Poly-Gate. Blocking Oxide La2O3 LOCOS. LOCOS. Source. p-type si wafer. Drain. (j)Contact hole opened and metal pads formation Fig.3-1 Process flow of the proposed flash memory cell.. 52.

(66) 7nm 4nm 2nm. SiO2 SiO2. La2O3. 5nm. Fig.3-2 TEM image of the flash memory cell. The thickness of the O/N/O layers are 7/4/2 nm respectively.. 53.

(67) Id (A). 10-4 10-5 10-6 10-7 10-8 10-9 10-10 10-11 10-12 10-13 10-14. Fresh Program state Vg=9V,Vd=9V Erase state Vg=-5V,Vd=9V. 0. 2. 4. 6. 8. Vg (V) Fig. 3-3 Ids-Vgs curves of the La2O3 memories. A memory window of larger than 3V can be achieved with Vg= Vd=9V programming operation. 54.

(68) 6. Vt shift (V). 5 4 3. Vg=7V, Vd=7V Vg=8V, Vd=8V Vg=9V, Vd=9V Vg=10V, Vd=10V. 2 1 0 10-7. 10-6. 10-5. 10-4. 10-3. 10-2. 10-1. 100. Time (sec) (a). 3.0. Vt-shift (V). 2.5. V g=-3V , Vd=9V V g=-4V , Vd=9V V g=-5V , Vd=9V. 2.0 1.5 1.0 0.5. Initial Vt. 0.0 -0.5 10 -7 10 -6 10 -5 10 -4 10 -3 10 -2 10 -1 10 0. 10 1. Erasing Tim e (sec) (b) Fig.3-4 Program characteristics of the memory devices with different programming conditions. A memory window of about 3.5V can be achieved with Vg=Vd=10V, and time=1ms programming operation. (b). Erase characteristics of the memory devices with different erasing voltages. 55.

(69) Normalized Vt shift %. 120 100 80 60 40 20. 25oC 85oC 125oC. 0 100 101 102 103 104 105 106 107 108. Time (sec) Fig.3-5 Retention characteristics of La2O3 memory devices at T=25°C, 85°C and 125°C. Very low charge loss is seen even after 104 seconds. 56.

(70) 6. Vt (V). 5 4. 1.66V. 3 2. Erase state Vg=-3V Vd=10V t=1ms Program state Vg=9V Vd=9V t=0.1ms. 1 100. 101. 102. 103. 104. Cycles Fig. 3-6 Endurance characteristics of the La2O3 memory devices. Slight degradation is found after 102 P/E cycles. 57.

(71) Normalized Vt shift %. 120 100 80 60 40. Fresh 25oC Fresh 85oC. 20. 100K P/E Cycled 25oC 100K P/E Cycled 85oC. 0 100 101 102 103 104 105 106 107 108. Time (sec) Fig.3-7 Retention characteristics of La2O3 memory devices with cycling and fresh at T=25°C, 85°C.. 58.

(72) Id (A). 10-4 10-5 10-6 10-7 10-8 10-9 10-10 10-11 10-12 10-13 10-14 0. E-b1 E-b2 (0,0) P-b1 E-b2 (0,1) P-b1 E-b2Forward read Vd=2V E-b1 P-b2 (1,0) P-b2 E-b1 Reverse reasd Vs=2V. 1. 2. 3. 4. 5. 6. 7. 8. Vg (V) Fig.3-8 Ids-Vgs curve of the memory in the 2-bit per cell operation. ; forward read and reverse read for programmed bit1 and programmed bit2. Program Erase. Bit1. Bit2. Read. Vg 9V. -3V. 4V. Vd 9V. 10V. 0V. Vs. 0V. >2V. Vg 9V. -3V. 4V. Vd 0V. 0V. >2V. Vs. 10V. 0V. 0V. 9V. Table.3-1 Operation principles and bias conditions utilized during the operation of the La2O3 Flash memory cell 59.

(73) 7 Charge loss. Vt (V). 6 5. 1.2V. 4 3. Charge loss Programmed bit-1 Erased bit-2 o T=25 C. 2 100 101 102 103 104 105 106 107 108. Time (sec) (a). G. Vertical. Block Oxide La2O3 eTunnel Oxide. migration. (b) Fig.3-9 Retention characteristics of La2O3 memory devices with Programmed bit-1 and Erased bit-2 at T=25°C. (b) show the schematic of vertical migration.. 60.

(74) Program state Vt-shift (V). 2 1 0 -1. Vd=5V Vd=7V Vd=9V. -2 100. 101. 102. 103. Time (sec). Erase state Vt-shift (V). Fig. 3-10 Drain disturbance characteristics of the La2O3 memory cells. After 1000 s at 25 °C, only a 1V drain disturb was observed for Vd=9V condition.. 2 1 0 Vg=8V Vg=9V Vg=10V. -1 -2 1. 10. 100. 1000. Time (sec) Fig. 3-11 Gate disturbance characteristics of the La2O3 memory devices. A threshold voltage shift of 1 V occurred after stressing at Vg = 10 V and Vs = Vd = Vsub = 0 V for 1000 s. 61.

(75) Id (A). 10-4 10-5 10-6 10-7 10-8 10-9 10-10 10-11 10-12 10-13 10-14. Vg=4V, Vt=3V Vg=0V, Vt=3V Vg=4V, Vt=5.3V. 0. 1. 2. 3. 4. Vd (V) Vd. Program state or. Vg. Erase state unselected cell. Fig. 3-12 Drain current comparison between the programmed cell, erased and unselected cell. Cell information can be read out at Vg=4V and Vd=2V.. 62.

(76) Erase state Vt shift (V). 2 1 0 Vg=4V, Vd=2V Vg=4V, Vd=3V Vg=4V, Vd=4V. -1 -2 1. 10. 100. 1000. Time (sec). Fig. 3-13 Read disturbance characteristics of the La2O3 flash memory. No significant Vt shift occurred for Vd < 4, even after 1000 s at 25 °C.. 63.