Chapter 1 Introduction
1.4 Organization of this Thesis
In this chapter we briefly review the history of ZnO TFTs. In Chapter 2 we will describe the fabrication and process flow of n-type ZnO TFTs. Another portion is measurement setup and some characteristics which are cause of fabrication. In Chapter 3 we will discuss fruitful experimental results by using various physical models and mathematic tools. Finally, we will give conclusions and suggestions for future works based on our experimental results.
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Chapter 2
Device Fabrication, Measurement Setup and Parameter Extraction
2.1 Device Fabrication and Process Flow
In this thesis, we use an inverted-staggered type structure which is one of the commonly-used TFTs in display industry due to its simple fabrication processes [29]. The complete fabrication processes only need four photolithography masks: gate electrode, source and drain (S/D), active area, and metal contact definition. The 3-dimensional and cross-sectional views of the fabricated ZnO TFT are shown in Figs. 2.4 (a) and (b), respectively. The detailed processes are as follows. First, Si wafers were oxidized in a horizontal furnace to simulate glass substrates for display industry. Second, a 200-nm-thick Al-Si-Cu film was deposited by physical vapor deposition (PVD) and then patterned by photolithography and wet etching to form gate electrode, as shown in Fig. 2.1. Third, a silicon dioxide (20 nm) was deposited by plasma-enhanced chemical vapor deposition (PECVD) as the gate dielectric. Fourth, a ZnO film was deposited by RF magnetron sputter as the channel layer. It should be noted that the ZnO target, which is composed of sintered ZnO powders, needs a pre-sputtering treatment prior to the deposition in order to remove the otiose particles.
More importantly, the deposition conditions for the channel layers, such as oxygen flow rate, pressure, deposition temperature, and time are the key to the electrical characteristics of devices. Therefore, we intentionally explore the impacts of deposition conditions on their characteristics in Chap. 3. Moreover, in Sect. 3.1, we specially give material analyses on the deposited ZnO films before we discuss our experimental results of the ZnO TFTs. Fifth, the photo-resist was spin-coated, exposed, and developed to define the S/D regions, as illustrated
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in Fig. 2.2 (a). Then, a 300-nm-thick Al layer was deposited by thermal coater as shown in Fig.
2.2 (b). Subsequently, the devices were immersed in a tank paired with ultrasonic oscillator to peel off the photo-resist. The S/D area appeared after the lift-off process which can suppress the damages induced on the channel surface. The active area was defined by standard photolithography and then etched by diluted hydrochloric acid (HCl), as illustrated in Figs.
2.3 and 2.4, in which the definitions of physical channel length (L) and channel width (W) were also described. Finally, the metal contact of gate was defined.
2.2 Measurement Setup
The typical current-voltage (I-V) electrical parameters are measured by an HP4156A precision semiconductor parameter analyzer, and the basic parameters of the ZnO TFTs, including sub-threshold swing (S.S.), threshold voltage ( ), field effective mobility ( 𝐹 ) and so on are also extracted. At the same time, the capacitance-voltage (C-V) electrical parameters are measured by an Agilent 4284 precision LCR meter. This method is capable of resolving a number of behaviors of the charges contained in the devices. When the charges are varied with the time-dependent electric field, it produces a displacement current [30].
Subsequently, capacitance C relates the displacement current i to the voltage V, and is defined as
𝑖 𝑑𝑉𝑑 (Eq. 2.1) or
𝑑𝑄𝑑𝑉. (Eq. 2.2) Furthermore, the C-V characteristics are evaluated by the multi-frequency C-V method in order to extract the density of states (DOS) and understand the behaviors of the charge in responses to the frequency. The frequency of the measurements is varied between 60 Hz-100 kHz. The gate and S/D are connected with high-terminal and low-terminal,
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respectively, as shown in Fig. 2.4(a). The equivalent circuit of basic model includes the device elements and an output resistor, which is due to the parasitic series S/D resistance ( ). The equivalent circuit of ZnO TFTs can be represented by the parallel channel transistors owing to the n-type doping nature of the material. The conduction mechanisms are discussed briefly in sub-section 2.3.3.
2.3.1 Metal-Semiconductor Contacts
The metal-semiconductor contacts are an important element in affecting the output characteristics of the fabricated devices. Here, we briefly discuss the operation of the metal-semiconductor contact, which is also called Schottky diodes. From Fundamentals of Modern VLSI Devices [31], the band diagram of the metal-semiconductor can be described in Fig. 2.6(a). When surface states are ignored, the barrier height of electrons (𝑞𝜑𝐵𝑛) is
𝑞𝜑𝐵𝑛 𝑞(𝜑𝑚 𝜒), (Eq. 2.3) where 𝑞φ𝑚 and qχ are the metal work function and the electron affinity of semiconductor, respectively. When the system is in thermal equilibrium with zero bias, the built-in potential 𝜑 𝑖 is
𝑞𝜑 𝑖 𝑞𝜑𝐵𝑛 ( 𝑐 ) 𝑙𝑘, (Eq. 2.4)
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where 𝑐 and are conduction band minimum and quasi Fermi-Level, respectively. When we apply a positive bias on metal, there is a net flow of thermic electrons from semiconductor into metal, as illustrated in Fig. 2.6(b). According to the above illustration, the is an important factor affecting 𝑞𝜑𝐵𝑛 which is also related to the carrier concentration in the semiconductor. If the semiconductor has a higher carrier concentration, the Schottky diodes behave like an ohmic contact.
2.3.2 Parasitic Series S/D Resistance
In this sub-section, we introduce the extraction of the based on the scheme reported in literatures [28] and [32]. As shown in Fig. 2.7(a), for conventional MOSFETs the total reduction in channel length due to the formation of S/D junctions, and thus L-ΔL represents the effective channel length, 𝐿 . Although with a structure distinctly different from the point due to the lower carrier concentration, with an example shown in Fig. 2.9 [32]. When this happens -dependent can be determined by
𝑚 𝑐 + 𝐵 + 𝐴 𝐿 (eq. 2.7) where the parameters A and B are extracted from the slope and intercept of 𝑚 𝐿 plots.
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The can be used in the scheme of DOS extraction employed in Chap. 3.
2.3.3 Comparison of Junctionless, Accumulation and Inversion mode
Recently, the junctionless transistor has received much attention because it is compatible with the CMOS fabrication and offers a few advantages over the inversion-mode devices, like the elimination of junction formation process [33]. To distinguish the differences between the device operation, the transfer curve of the three types of SOI MOSFETs: inversion-mode, accumulation-mode and junctionless transistors, as shown in Fig. 2.10 in which the flat-band voltage ( ) is labeled. From the figure it is seen that the of the inversion-mode devices is obviously below V . For accumulation-mode devices, is slightly above V , and is much larger than in the case of junctionless devices. Thus, and carrier concentration are very important in determining the type of the device and its operation mode.
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Chapter 3
Results and Discussion
3.1 Properties of ZnO
Pure ZnO films deposited under various deposition conditions are studied in order to understand the basic material properties which are important for the device characteristics. In this section, several characterization methods, including X-ray Diffractometer (XRD), X-ray photoelectron spectroscopy (XPS) and Hall Measurement, are presented.
Hall measurement: In the measurements a silicon dioxide as a high resistance buffer layer is
needed in order to prevent inevitable noises. Another note is that indium balls are adhered to the measured ZnO films for reducing the contact resistance. The results of five splits (sample A-F) of different deposition conditions, including various oxygen flow and substrate temperature, are presented in Table 3.1. The information about carrier concentration, resistivity and bulk mobility are shown in Table 3.1, too. The increase in electron concentrations at the small oxygen flow condition is reasonable because more oxygen vacancies are expected to be contained in the film. In the study we found that the measurement failed for the sample D prepared under the oxygen flow of 9 sccm because the resistivity is too large to be measured. However, the electron concentration seems not to increase with increasing temperature. Effects of this finding on the transfer characteristics of ZnO TFTs are discussed in Sect. 3.2.3.
X-ray photoelectron spectroscopy: XPS was used to identify the chemical state of IGZO
films in previous work [34-35]. According to the literature [35], O 1s peak could be fitted by three waves, centered at 530.06, 531.56 and 532.62 eV, respectively. The low binding energy OL is related to the texture of 𝑍𝑛2+ surrounded by 𝑂2−. The medium binding energy OM is
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associated with the magnitude of oxygen vacancies. The high binding energy OH is associated with the weak bound oxygen on the surface of ZnO films, such as adsorbed H2O or O2. For simplicity, we assume the influences of environment on various ZnO films are identical and negligible. Thus, the XPS spectrum were fitted by two waves, including OL and OM. Figs.
3.1-3.4 show the XPS spectrum of O 1s peak under various oxygen flow conditions, and they indicate that the Gaussian-fitted results fit the experimental data. The ratio ( 𝐴𝑀
𝐴𝐻+𝐴𝑀), where AM and AH are the sum of the intensity areas of OM and OL, respectively, increases when ZnO film
was deposited under a higher oxygen flow condition. The observed trend is consistent with the experimental results of Hall Measurements that the carrier concentration decreases with increasing oxygen flow.
X-ray Diffractometer: The XRD patterns of ZnO films with various deposition conditions are
shown in Figs. 3.5-3.10. These results show that the ZnO films are highly textured with c-axis (002), and the observed peaks are nearly the same among the test samples regardless of the various deposition conditions. Moreover, the coherently diffracting domain size can be calculated by Scherrer’s equation [36]. Grain size is estimated to be in the 5~10 nm range which is in agreement with the results of transmission electron microscopy (TEM), as shown in Fig. 3.11.
3.2 Extraction of Density of States (DOS) with Multi-Frequency C-V Measurements
In this section, we discuss the effect of varying frequency on the C-V curves and the extraction of DOS in the bandgap of the ZnO film based on the C-V results. Although varying the frequency of the applying basically does not change the equivalent circuit of devices, the components in the circuits, including capacitance and resistance, depend on the frequency.
Fig. 3.12 shows the measured capacitance-V characteristics of a device under various
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frequencies. Fig. 3.13 shows the transfer characteristics at 𝑑 0.1 and 1 V. The device’s L and W are 50 and 300 μm, respectively. The deposition conditions of the ZnO channel are the same as those of the sample B shown in Table 3.1. It is seen in Fig, 3.12 that the measured capacitance (Cm) becomes independent of the applied gate bias as the frequency is too high, implying the charges contained in the device are not responsible to the change of the small-signal frequency. Compared with the conventional MOSFETs, the channel resistance of the thin oxide channel is huge so the frequency repose of the devices is significantly affected.
Note that the C-V curves overlap each other under the lower frequency conditions (e.g., 60, 80 and 100 Hz), as shown in Fig. 3.12.
The multi-frequency C-V characterization allows us to extract the DOS in the bandgap [21-23]. When the localized states are below the quasi Fermi level, they prefer to be occupied by electrons. When they are close to 𝑐, the electrons contained in the localized states are likely to be released into the conduction band. By the same token, the valence-band electrons are likely to be trapped into the localized traps when they are close to the valence band edge.
Figs. 3.14(a) and (b) illustrate the charge transfer processes between these states occurring as Vg is smaller and larger than Vth, respectively. However, these behaviors (capture and emission) also need time to trigger and would draw consequence on the C-V measurements. A simplified C-V equivalent circuit accounting for the above description is illustrated in Fig.
3.15(a) which includes resistance and capacitance related to localized states ( ) and multi-frequency C-V measurements are given in the references [21-23]. To verify the above concept, Fig. 3.16 shows the 𝑚 of the ZnO TFTs under four frequencies (100, 1k, 5k and
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10k Hz). Based on the measured results and the procedure proposed in references [21-23], was calculated with three elements ( 𝐹 and ) and the results are shown in Fig.
3.17. Note that three different combinations of the frequencies show the same characteristics, verifying that the method is useful for eliminating the influences of frequency-dependent component. Then, the DOS can be determined as follows [22]:
𝑔𝐴 𝑉 𝑙 𝑚 𝑑𝑄 𝑑 𝑉 𝑙 𝑚 𝑞𝑑𝑄 𝑑𝑉 ( × ×𝑇𝐿𝑂𝐶
𝑍𝑛𝑂)×𝑞 (eq. 3.1) The DOS or the density of the localized states (𝑔𝐴 ) and the free electron density (𝑛 𝑟 ) versus are plotted in Fig. 3.18. The free electron density is in the 10 7~10 8 𝑐𝑚−3 range which is typical in the ZnO TFTs and is consistent with the enhancement-mode transfer characteristics shown in Fig. 3.13. One difficulty associated with such scheme is that it is hard to precisely determine the flat-band voltage ( ). For simplicity, an energy level is accumulation-mode device because of the relatively low 𝑛 𝑟 . The field-effect mobility 𝐹 increases when a positive is applied, as shown in Fig. 3.20.
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3.3 Effects of Different Deposition Conditions
3.3.1 Effects of ZnO Thickness (𝑻𝒁𝒏𝑶)
The influences of channel thickness, 𝑇𝑍𝑛 , are studied in this sub-section by characterizing the I-V transfer characteristics of ZnO TFTs with 𝑇𝑍𝑛 of 25, 40 and 55 nm.
These channel films were deposited with RF power of 100 W, substrate temperature of 25℃, chamber pressure of 5 mTorr and Ar/O2 ratio of 50/1. The device L and W are 50 and 300 μm, respectively. Obviously negative shift and slight degradation in S.S. with increasing 𝑇𝑍𝑛 are observed in Fig. 3.21. Thicker 𝑇𝑍𝑛 has more electrons in the channel, resulting in a higher conduction current at a specific gate bias. Moreover, the C-V plot in Fig. 3.22 for the one with 𝑇𝑍𝑛 -55nm is found to continuously decrease with decreasing gate voltage in the negative gate bias is adequately negative so that the channel is fully depleted. For the case with 𝑇𝑍𝑛 of 55nm, obviously the channel is too thick to be fully depleted in the gate voltage range applied in the figure. Thus, the series 𝑑 𝑝 tends to further lower 𝑚 in the negative voltage regime. Note that S.S. is also influenced by 𝑇𝑍𝑛 due to the higher amount of the charges in the channel depletion region.
3.3.2 Effects of Deposition Temperature
A rise in the deposition temperature is usually expected to promote the electron mobility in the deposited ZnO because of the better crystallinity. To explore the effects of temperature, parameters of the deposition conditions except temperature are fixed. They are 𝑇𝑍𝑛 of 15 nm, RF power at 100 W, chamber pressure at 5 mTorr and ratio of Ar/O2 at 50/1. The device L
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and W are 50 and 400 μm, respectively. Fig. 3.23 compares transfer characteristics of devices subjected to three various temperatures: 25, 100 and 200 ℃. It is seen in the figure that high temperature conditions cause a negative shift in and the S.S. degradation. The appearance of the shift is believed to be due to the increase in the electron concentration under the high temperature deposition condition as confirmed by the Hall Measurement. Fig. 3.24 shows that the electron concentration increases with increasing deposition temperature.
Furthermore, Fig. 3.25 shows the hysteresis phenomenon of the two devices deposited at 25 and 200 oC, respectively. Under the room temperature condition, the hysteresis is obvious, implying that abundant defects are contained in the channel. As the temperature is raised to 200 oC, the hysteresis becomes negligible. Promotion in the crystallinity is postulated to be responsible for such an observation. Fig. 3.26 shows the intensity versus angle (2θ) of the ZnO films deposited at 25 and 200 oC, respectively. The larger intensity of the c-axis (002) signal seen in the latter indicates that the ZnO film deposited at 200 oC has better crystallinity.
3.3.3 Effects of Oxygen Flow
To optimize the electrical characteristics of ZnO TFTs, we need to carefully control the oxygen levels because the changes from Zn- to O-rich condition would cause different characteristics of ZnO TFTs. Except the oxygen flow, all other parameters of the ZnO deposition conditions are fixed, including 𝑇𝑍𝑛 of 15 nm, RF power at 100 W, chamber pressure at 5 mTorr and ratio of Ar/O2 at 50/1. The device L and W are 50 and 300 μm, respectively. Fig. 3.27 shows the transfer characteristics of the devices with the ZnO channel deposited at various oxygen flows, including 1, 3 and 9 sccm. Based on a previous work [18], the oxygen vacancies are the source of n-type conduction carriers. Increasing the oxygen flow is thus expected to reduce the free carrier concentration which is essential for conduction of enhancement-mode devices. Fig. 3.27 shows indeed that the transfer characteristics have a positive shift when the oxygen flow increases. The cause of the positive shift is believed
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to be due to a reduction in the oxygen vacancies in the ZnO films. XPS results shown in Figs.
3.2-3.4 confirm the behavior. However, a positive shift of with a hump effect is also observed for the device with oxygen flow of 9 sccm. In order to investigate the source of such a hump, the DOS (𝑔𝐴 ( )) in the energy gap of the ZnO channel were extracted by multi-frequency C-V method presented in Sect. 3.2. 𝑔𝐴 ( ) versus is plotted in Fig. 3.28 for the device with oxygen flow of 9 sccm. In this figure E1 is the level corresponding to Vg =0.4 V. As shown in Fig. 3.28, a peak at 1.5 𝑒 is clearly observed. Band diagrams are illustrated in Figs. 3.29 and 30 to facilitate the understanding of the hump phenomenon. Fig. 3.29 is the band diagram in the off state (say, 𝑑 3.3 × 10− 4 A at 0.4 V), the states existing below were occupied by electrons. As shown in Fig.
3.30, the hump occurs as the surface potential is crossing the peak of 𝑔𝐴 ( ). The high amount of defects slows down the movement of surface potential with increasing and thus the S.S. is degraded. The result indicates that the ZnO films were changed to O-rich condition under the high oxygen flow conditions, as has been pointed out in a previous work [18]. Fig.
1.3 (b) shows that the formation energy of the oxygen interstitials (𝑂𝑖) and zinc vacancies ( 𝑍𝑛) are lower than the other species shown in the same figure, resulting in more defect states formed (𝑂𝑖 and 𝑍𝑛). These defects are speculated to be responsible for the appearance of 50 and 300 μm, respectively. The deposition conditions of the ZnO are the same as those of
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the sample B given in Table 3.1. The bias stress conditions were ±5 and 𝑑 0 , and the stress time is 1000sec. Figs. 3.31 ~ 3.34 show the characteristics of devices subjected to various stress conditions as a function of stress time. In Fig. 3.31, the PBS causes the transfer curve to shift in positive direction. The obvious positive shift and little degradation of S.S. by the PBS indicate that the shift is mainly caused by electron trapping in the gate
dielectric interface [37]. Figure 3.32 shows that the NBS also causes a positive shift, although the extent is much smaller than that of PBS. Electron trapping due to the gate injection current is postulated to be the root cause. However, the NBLS under the light illumination shows a large negative shift in the transfer curves, as shown in Fig. 3.33. The negative bias attracts excess holes generated by the light exposure to fill the traps located at the gate dielectric, thus a larger negative shift in Vth is resulted. On the other hand, the PBLS also shows a negative shift. It implies that the hole trapping events due to the photo-generated holes also occur and even outnumber that of the electron trapping. Nonetheless, the shift in Vth quickly ceases at stress time of just 1 sec. This implies the trapping holes are close to the channel/dielectric interface and tend to impede further injection of holes from the channel.
Subsequently, the dependence of measurement temperature on I-V transfer characteristics was investigated. Fig. 3.35 shows I-V transfer characteristics measured at
𝑑=0.5 V and temperatures of 25, 50, 75, 100, and 125 ℃ r s ctiv ly. The device length and width are 70 and 200 μm, respectively. In all devices, the and S.S. monotonically decreases and increases, respectively, with increasing temperature. In contrast, the dependency of on-current on temperature is more complicated. In Fig. 3.36, we can see that the on-current is promoted as the temperature increases from 25 to 50 oC. This is attributed to an increase of intrinsic carrier concentration in the channel which causes the increase in both
𝑑=0.5 V and temperatures of 25, 50, 75, 100, and 125 ℃ r s ctiv ly. The device length and width are 70 and 200 μm, respectively. In all devices, the and S.S. monotonically decreases and increases, respectively, with increasing temperature. In contrast, the dependency of on-current on temperature is more complicated. In Fig. 3.36, we can see that the on-current is promoted as the temperature increases from 25 to 50 oC. This is attributed to an increase of intrinsic carrier concentration in the channel which causes the increase in both