Chapter 1 Introduction
1.5 Organizations of the Thesis
This dissertation comprises of six chapters. Chapter 1 describes the background and purpose of this study. Chapter 2 introduces the main architecture of the devices proposed in this work. Chapter 3 and Chapter 4 investigate and analyze some constructive methods to improve the device performance. In Chapter 5, we will discuss the feasibility of poly-Si NWs for practical sensing applications. And all the
described as follows.
In Chapter 1, an overview of NWs is described, together with a brief introduction of low-temperature crystallization techniques and NW-based sensor devices. To overcome the issues encountered in the present NWs’ preparation methods, a novel Si NW fabrication scheme is thus proposed as the main motivation of this study. Then, the organization of the thesis is presented in the last section.
In Chapter 2, the structure and fabrication process of the poly-Si NW devices are specified. The basic electrical behaviors are then examined. To address the off-state issues found in the original design of the devices, several improvement methods are exploited, including structural and process modification. Afterwards, plasma post-treatment and MILC technique are employed to passivate the microstructural defects and to enhance the crystallinity of the NWs, respectively. Furthermore, MILC coupled with post high-temperature annealing will lead to excellent device performance.
In Chapter 3, the influence of structure and process parameters on MILC mechanism is investigated for better understanding of MILC-enhanced Si NWs. In the implementation of MILC process, it is shown that the arrangement of seeding window plays an important role in affecting the resulting film quality and the device
performance. In addition, the dimension of NWs also affects the effectiveness of MILC improvement. TEM analyses are extensively used in this chapter to inspect the microscopic properties.
In Chapter 4, a novel MG TFT with poly-Si NW channels is fabricated using a straightforward manner. The combination of an ultra-thin channel layer with MG structure is expected to further improve the device performance. In the proposed transistors, poly-Si NWs are formed in a self-aligned manner and precisely positioned with respect to the side-gate, top-gate and bottom-gate, resulting in much stronger gate controllability over the NW channels, thus dramatically boosting the device performance over conventional single-gated TFTs. Another great benefit of such scheme is that the independently applied gate bias could be utilized to adjust the threshold voltage of NW channels in a reliable manner, making it very favorable for practical applications.
In Chapter 5, poly-Si NWs are employed to study their feasibility and capability for chemical and biological sensing applications. Due to easy preparation and fabrication on a number types of substrates, poly-Si NW devices could reduce production cost and be favorable for constructing on versatile platforms. However, poly-Si suffers from inherent defects in inter/intra grains which would impede carrier
because of the issue of sensitivity degradation. In this work, we show that such concern could be alleviated as long as the measurement is carried out in an aqueous solution, and possible mechanism for this phenomenon is also addressed. Under all sensing measurements, the NW devices are encapsulated in a microfluidic system, which will provide safe and reliable environment for chemical and biological reactions on the NWs. As a result, the sensing capability of poly-Si NW device for detection of pH-value and biomolecules could be performed and investigated.
Finally, contributions and conclusions of this dissertation as well as recommendations for future research are given in Chapter 6.
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Fig. 1-1 Schematic illustration of Si NWs fabrication on SOI substrate by advanced lithography technique.
Fig. 1-2 Principle of imprint lithography: 1) mold with nano features is used to physically deform thin layer of resist; 2) mold is separated from the resist after curing; 3) nano patterns in resist are transferred into substrate.
Imprint
Separation
Pattern transfer
Fig. 1-3 Growth mechanism of nanowire by VLS method.
Fig. 1-4 Schematic illustration of the metal-induced crystallization (MIC) and metal-induced lateral crystallization (MILC). The arrows indicate the crystallization direction for each mechanism.
Fig. 1-5 Schematic representation of the formation of (a) NiSi2 precipitate in a-Si network, and (b) c-Si crystallite after the migration of NiSi2.
(a)
(b)
Fig. 1-6 Schematic equilibrium free energy diagram for NiSi2 in contact with a-Si and c-Si.
Fig. 1-7 Illustrations of sensing process for a Si NW device. (a) NW’s surface is modified with specific receptors and the conductance is recorded. (b) Target species are introduced and attached to the receptors. If the NW device is n-type and the target molecules are negatively charged, then the corresponding conductance is reduced.
Chapter 2
Novel Thin-Film Transistors Featuring Sidewall-Spacer Poly-Si Nanowire Channels
2.1 Introduction
Nanowire (NW) has attracted great interest as essential building blocks for functional devices because of its potential applications in nanoelectronics [2.1, 2.2].
Since the surface-to-volume ratio of a semiconductor wire is inversely proportional to its diameter or feature size, the characteristics of a NW device would be significantly affected by the surface condition during operation. Furthermore, thanks to its tiny body, the gate can exert better control over NW channels and thus effectively suppresses short-channel effects (SCEs) in extremely scaled-down field-effect transistors (FETs) [2.3]. These properties therefore lend NW itself nicely to a number of applications, including NW thin-film transistors (TFTs) [2.1], nano-scale complementary metal-oxide-semiconductor (CMOS) [2.3], memory devices [2.4], large-area electronics [2.1, 2.5], and sensors for sensing chemical or biological species [2.6, 2.7]. Among these applications, the NWs are traditionally prepared by either top-down [2.3, 2.7] or bottom-up approaches [2.1, 2.2, 2.4, 2.5]. The top-down
the NW patterns. Although compatible with mass-production, the use of advanced lithography tools with nanometer size resolution is costly. On the other hand, the bottom-up approaches usually employ metal-catalytic growth for preparation of NWs.
The later approaches, however, suffer seriously from the difficulty in precisely positioning the device location. Metal contamination and control of structural parameters are additional issues that need to be addressed for practical manufacturing.
Previously, the sidewall spacer formation technique has been proposed to define the nano-scale hardmask (HM) itself, with subsequent etching step to pattern the target materials underneath the HM [2.8]. In contrast, we propose instead to define directly the nano-scale Si lines that serve as the device channel in this work. The top-view layout of the proposed NW device is shown in Fig. 2-1(a), while the cross-sectional view is depicted in Fig. 2-1(b). It features a side-gate configuration with NW channels abutting against the gate. Note that the side-gate could be used to adjust the channel potential, thus controlling the device’s switching behavior. In addition, for the sidewall Si layer only the regions between the source and drain are shown and defined as the channel length. Also worth noting that, with large portion of the NW surface exposing to the environment, the surface serves as the sensing site when the device is used as a sensor. After specific immobilization treatment, the receptor agents formed on the surface could selectively detect the target species
contained in the test solutions [2.6, 2.7]. As comparing with other proposed NW approaches (either bottom-up or top-down), our approach presents several advantages comprising very simple fabrication flow [2.9], reliable source/drain (S/D) contacts, and accurate control of NWs’ dimensions as well as precise positioning and alignment.
In addition, it is also reproducible and suitable for low-cost manufacturing.
In this chapter, a novel TFT structure with sidewall-spacer NW channels is introduced and demonstrated. Though this distinctive scheme profits easy and reliable fabrication process, some distressing parts are revealed and should be addressed.
Consequently, in order to meet the requirement of future applications, several feasible approaches are explored to improve the issues and boost device performance.
2.2 Experimental
Since poly-Si film obtained by direct deposition method suffers from smaller grains and defective structure, the poly-Si NW TFTs in this study are fulfilled by crystallizing amorphous Si film into polycrystalline state to achieve better crystal property. Here, the recrystallization methods utilized are solid-phase crystallization (SPC) and metal-induced lateral crystallization (MILC), respectively.
2.2.1 Solid-phase Crystallized Poly-Si NW TFTs
Fig. 2-2(d) shows schematic structure of the proposed NW device. It adopts a side-gate scheme where two NW channels are formed on the sidewall of the gate. S/D regions lying across the gate are defined simultaneously with the formation of NW channels in a self-aligned manner. The key device fabrication steps are illustrated in Fig. 2-2 and 2-3. Briefly, an n+-poly-Si gate was first formed on a thermally oxidized Si substrate (Fig. 2-2(a)). For better step coverage, tetraethyl orthosilicate oxide (TEOS-SiO2) was selected to serve as the gate dielectric by low-pressure chemical vapor deposition (LPCVD) system. A 100 nm amorphous Si (a-Si) layer was then deposited on the 40 nm-thick TEOS gate oxide by LPCVD. Next, a SPC treatment was carried out at 600 oC in N2 ambient for 24 hours to transform the a-Si into poly-Si into polycrystalline (Fig. 2-2(b)). Subsequently, S/D dopants were implanted by P31+
ion beam with a dose of 1 x 1015 cm-2 at 15 keV and BF2+ with 1 x 1015 cm-2 at 20 keV for n- and p-type transistors, respectively (Fig. 2-2(c)). Note that the implant energy was kept low so that most implanted dopants were located near the top portion of the Si layer. S/D photoresist patterns were then generated by a G-line stepper.
Anisotropic plasma dry-etching with Cl2/HBr etchant was subsequently employed to shape the poly-Si layer. During the etching process, the NW channels were simultaneously formed abutting against the gate (Fig. 2-2(d)), similar to the formation
of sidewall spacers in standard CMOS manufacturing. Note that the NW channels were accomplished in a self-aligned manner with respect to the S/D and remained undoped because the aforementioned implant was done at a low energy so that the implanted dopants do not reach the channel. Afterwards, wafers were capped with a 200 nm-thick TEOS oxide as the passivation layer at 700 oC, and the S/D dopants were activated in this thermal process. The fabrication was completed after the formation of contact pads using standard metallization steps. It is noteworthy that only four-mask process is required to accomplish the NW TFT.
2.2.2 Metal-induced Lateral Crystallized Poly-Si NW TFTs
In the previous subsection, the NW TFT illustrated was prepared by crystallizing an amorphous Si layer with SPC scheme and the NWs are polycrystalline in nature.
The device performance is thus limited by the existence of inter/intra-grain boundary defects. For the purpose of further improving NW crystalline property, a common low-temperature poly-Si (LTPS) process is exploited. Namely, MILC technique is investigated to enhance the device performance in this work.
Basically the fabrication flow follows that described in Section 2.2.1, with the addition of the implementation of MILC process. After formation of the active regions,
the Si layer, unlike SPC-processed split, was still in amorphous state as shown in Fig.
2-4(a). A 100 nm-thick low-temperature oxide (LTO) was then deposited onto the device by plasma-enhanced CVD (PECVD). For MILC purpose, the seeding window was opened in the LTO layer on the source side (Fig. 2-4(b)). Here the source region was defined as the terminal that serves as the grounded source during normal device electrical characterization. Before the MILC treatment, a 5 nm-thick Ni layer was deposited in the window area as the seeding layer. The Ni induced crystallization was carried out at 550 oC for 16 hours in an N2 ambient, which also served the dual purpose of dopant activation. The un-reacted Ni was then removed by a mixture of H2SO4/H2O2 solution. The arrows in Fig. 2-4(c) indicate the induced crystallization directions. After the deposition of a 200 nm-thick passivation oxide layer and opening of contact holes, a standard metallization step was performed to complete the device fabrication. It is evident that the overall process flow is also quite simple and straightforward.
Figs. 2-5(a) and 2-5(b) are optical micrograph (OM) pictures of n- and p-type MILC NW devices, respectively. The portion surrounding the window with different colors indicates the region that has been laterally crystallized. Inside the window, however, the crystallization mechanism is called metal-induced crystallization (MIC), and normally with a lot amount of metal species and smaller grains compared with
that in the MILC region. From Fig. 2-5, MILC rate in p-type film is apparently higher than that in n-type film. This is because Ni acts as a cation (Ni+) when diffusing in Si.
The addition of electron acceptors, such as boron, into the Si layer will generate positive holes, and accordingly Ni atoms can easily give up their outermost electrons leading to lower ionization energy. This also explains why the formation temperature of NiSi2 is lowered down to 250-280 oC [2.10], though it is normally above 400 oC in the case of intrinsic film. Therefore, the hole-rich environment is conducive to the formation of Ni+ and enhances the Ni diffusion. On the contrary, higher ionization energy is required to create Ni+ in the electron-rich environment of an n-type film.
Besides, phosphorous and arsenic dopants are known for gettering transition metal elements, and thus tend to trap Ni atoms [2.11]. As a result, the Ni diffusion is retarded. The correlation of MILC rate and dopant type is revealed in Fig. 2-6, where the MILC rate is about 3.41 μm/hr for p-type and 1.72 μm/hr for n-type films.
Fig. 2-7 shows a SEM image taken near the seeding window. It can be seen that the needle-like Si grains protrude from the MILC seeding window, and the width of them could achieve 90 nm. Generally, the size of NW fabricated in our study is smaller than 50 nm in width. As a result, with the combination of our NW device architecture and MILC technique, monocrystalline Si NWs are expected. Moreover, it should also be noted that much smaller grains and more defects are observed in the
MIC region. Hence, device active region is usually constructed in the MILC region rather than MIC area.
2.2.3 Electrical Characterization Methods
First, the extraction method and definition of several important electrical parameters in this dissertation are briefly described. All the measurements are performed by HP 4156A semiconductor parameter analyzer together with Interactive Characterization Software (ICS).
1. Threshold voltage (Vth)
The threshold voltage (Vth) is obtained by the constant current method and defined as the gate voltage (VG) needed to achieve a specific drain current (ID). The expression is as follows,
L nA I W
at V
Vth = G D = ×100 (2-1)
where W and L are the channel width and length, respectively.
2. Subthreshold slope (S.S.)
This parameter is calculated from the subthreshold current in the weak inversion region, given by
)
The mobility is derived from the formula of ID as function of VG and described as follows,
where Cox is the gate oxide capacitance per unit area, and Gm stands for the transconductance given by,
Note that the drain current used for the extraction is divided by two because of the two effective conduction channels contributed to the current.
4. ON/OFF current ratio (ION/IOFF)
ION and IOFF are determined from the ID-VG curves, where ION is chosen as the maximal ID and IOFF is the minimal one.
Note that all the parameters are extracted from the ID versus VG characteristics operated in the linear regime, except for the ION/IOFF which is in the saturation regime.
2.3 Results and Discussions
2.3.1 Fabricated Device Structure
Major benefits of the proposed scheme are accurate positioning of NWs and reliable contacts between NW and S/D regions. Fig. 2-8 is the SEM image of a fabricated NW device showing such features. In addition, the dimension of NW could be effectively controlled by utilizing such sidewall-spacer scheme [2.12]. Fig. 2-9(a) shows cross-sectional TEM of the device in the aligned section of Fig. 2-1(a). The channel conduction width and thickness are 56 nm and 54 nm, respectively. By tuning the etching conditions properly, the size of NW can be further scaled down to smaller than 20 nm in both width and thickness as depicted in Fig. 2-9(b). As a result, this
Major benefits of the proposed scheme are accurate positioning of NWs and reliable contacts between NW and S/D regions. Fig. 2-8 is the SEM image of a fabricated NW device showing such features. In addition, the dimension of NW could be effectively controlled by utilizing such sidewall-spacer scheme [2.12]. Fig. 2-9(a) shows cross-sectional TEM of the device in the aligned section of Fig. 2-1(a). The channel conduction width and thickness are 56 nm and 54 nm, respectively. By tuning the etching conditions properly, the size of NW can be further scaled down to smaller than 20 nm in both width and thickness as depicted in Fig. 2-9(b). As a result, this