Chapter 4 Poly-Si Nanowire Thin-Film Transistors with
4.3 Results and Discussion
4.3.3 Tunable Threshold Voltage of MG NW TFTs
In addition to the MG operations demonstrated above, Vth adjustment by applying a fixed TG and/or BG bias is also feasible in the proposed device structure.
Figs. 4-16(a)-(c) show typical results in this aspect. In the figures, the SG acts as the active gate for controlling the device switching behavior. For each curve, a specific
voltage (Vset) ranging from -4 V to +4 V is applied to TG (VTG, Fig. 4-16(a)) or BG (VBG, Fig. 4-16(b)) alone, or jointly (VTG-BG, Fig. 4-16(c)). It can be found that the curves are shifted in parallel by varying the biases. This is because the potential of NW channel is modulated by Vset. Similar threshold voltage modulation has been studied on double-gated SOI devices previously, and was ascribed to the potential profile adjustment in the channel by the Vset [4.7, 4.15]. To qualitatively understand the situation, band diagrams of the NW under the influence of the gate bias conditions are shown in Fig. 4-17. When negative Vset is applied, it is conducive to suppress the generation of inversion charges in the channel, hence resulting in higher Vth. On the other hand, lower Vth is obtained when Vset is positive.
Fig. 4-18 shows Vth as a function of the applied Vset extracted from the data shown in Figs. 4-16(a)~(c). The results reveal that Vth could be linearly tuned to a suitable range. Magnitude of the slope can be regarded as an indicator that reflects the tuning capability of Vset. Among the three cases, the slope is the smallest when Vset is applied to TG only, due to the thick oxide used. The field strength is reduced with a thicker oxide, so the potential adjustment capability is degraded accordingly. While the largest slope is obtained when Vset is applied to both TG and BG, thanks to the strong gate coupling effect mentioned above. Similarly, for DG modes of operations, Vth could also be modulated by applying Vset to the remaining gate, as depicted in
Figs. 4-19 and 4-20. However, the tuning ability of Vset declines under DG modes as compared with that under SG mode. For instance, ΔVth set by BG for SG and DG-1 mode are 0.40 and 0.36, respectively. This is because SG coupling with TG could induce stronger control over the channel, and BG comparatively exhibits less effect on the Vth adjustment. Nevertheless, these results suggest that the threshold voltage of the new MG NW TFT could be easily adjusted to suit various applications.
For NW devices, the variation of structural parameters such as the feature size of the NW and the gate dielectric thickness, as well as dopant concentrations in the channel, could result in large fluctuation in Vth. Yet, in the proposed method, Vth
could be modulated by an electrical manner, and therefore the issue could be effectively resolved. Note that, the unique capability of electrically tuning the threshold voltage in the new NW structure is beneficial not only for circuit applications in electronics, but also for gas and biologic sensing applications. As described in a previous paper [4.6], the new NW architecture could be applied to chemical and biological sensing purposes, as some portion of the channel is exposed to the environment, as schematically shown in Fig. 4-21. After immobilization treatment, receptors are formed on the surface of the exposed channel. During the sensing stage, the receptors can capture the target species contained in the test environment with good selectivity, and the charges brought with the captured target
species will modulate the channel conductance. Overall the detection process functions as a virtual gate in the FET operation, and thus in reality the device is doubled-gated when the side-gate is also considered. To make the detection highly sensitive, it would be better if the device is operated in a bias condition in which the channel conductance is most sensitive to the surface charges. This could be achieved by applying a proper voltage (Vset) to the side-gate according to the above analyses, as shown in the figure. The applied side-gate voltage could be generated from a control circuit designed and fabricated by using modern complementary metal-oxide-semiconductor (CMOS) technology. This certainly increases the feasibility of the new NW device in practical applications.
4.4 Summary
In conclusion, a new poly-Si NW device with MG configuration was proposed and studied in this chapter. The NW channels are surrounded by three gates, i.e., top-, side- and bottom-gates, fabricated with a very simple and controllable process flow.
With MG operations, excellent electrical characteristics such as high ON/OFF current ratio of 107 and subthreshold slope of 250 mV/dec are obtained, which are significantly better than those reported in the previous work using only the side-gate
to control the device switching. The strong gate coupling effect of the MG operation, which is ascribed to the tiny body of NW channels, accounts for the observed improvement. The effect of NW volume on DG operation and gate coupling effect was investigated likewise. It is found that the benefit of DG control diminishes as the diameter of NW is larger than 35 nm. Moreover, the independently applied TG or/and BG biases can be employed to regularly adjust the Vth of NW channels in a reliable manner. The experimental results indicate that the Vth could be modulated by the gates with both positive and negative biases, making it suitable for practical applications.
The proposed NW TFT architecture is therefore promising for future manufacturing of high-performance NW devices.
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Fig. 4-1 Key fabrication steps of the MG NW TFT. (a) Source/drain ion implantation.
The dashed line represents the projected range which is near the top surface due to the low implant energy used. (b) Formation of source, drain and NW channels. The NW channels remain undoped due to the low implant energy used. (c) Stereo-view of the fabricated NW TFT. Top-, side-, and bottom-gates
(a)
(b)
(c)
(d)
Buried thermal oxide also as BG oxide (100 nm)
Formation of n+-poly-Si SG LPCVD TEOS as SG oxide (40 nm)
α-Si deposition and
crystallized at 600℃ for 24 hr
Formation of NW channels and S/D
S/D ion implantation (1x1015cm-2 Phosphorous,15 KeV)
LPCVD TEOS as passivation layer and TG oxide (200 nm) Al-Si-Cu as contact metal pads and TG electrodes
Dopant activation at 900℃ for 30 sec
NH3plasma treatment for 2 hr Buried thermal oxide also as BG oxide (100 nm)
Formation of n+-poly-Si SG LPCVD TEOS as SG oxide (40 nm)
α-Si deposition and
crystallized at 600℃ for 24 hr
Formation of NW channels and S/D
S/D ion implantation (1x1015cm-2 Phosphorous,15 KeV)
LPCVD TEOS as passivation layer and TG oxide (200 nm) Al-Si-Cu as contact metal pads and TG electrodes
Dopant activation at 900℃ for 30 sec
NH3plasma treatment for 2 hr
Fig. 4-2 Process flow for the fabrication of MG NW TFTs.
Fig. 4-3 (a) SEM image of a NW TFT before the deposition of passivation oxide and top-gate electrode, showing the self-aligned NW channels. (b) (Right) Cross-sectional view SEM photograph of a fabricated MG TFT showing NW channels surrounded by top-, side- and bottom-gates. (Left) Close-up TEM image of a NW channel specifying the width and thickness.
(a)
(b)
Table 4-I Active operating gates used in multiple-gated modes
Fig. 4-4 Diagram of a NW channel under the control of the three gates.
VG (V)
Fig. 4-5 Typical transfer characteristics of a NW TFT under (a) DG-1, (b) DG-2 and (c) TriG modes of operations compared with SG mode, respectively. (d) Comparisons of output characteristics between MG and SG modes of operations.
(a) (b)
(c) (d)
VG (V)
-1.0 -0.5 0.0 0.5 1.0
Gm (nS)
0 10 20 30 40 50 60
SG DG-1 DG-2 TriG W/ L = 30 nm/ 5 μm VD = 0.5 V
Fig. 4-6 Transconductance characteristics of a NW device under various modes of operation.
Fig. 4-7 2-dimensional simulation of electron density (eDensity) in NWs under DG-1, DG-2 and TriG modes of operation. The applied gate voltage is 5 V.
Table 4-II Comparisons of the electrical parameters among various modes of
VG (V)
-6 -4 -2 0 2 4 6 8
I D (A)
10-16 10-15 10-14 10-13 10-12 10-11 10-10 10-9 10-8 10-7 10-6 10-5
SG TG BG W/ L = 30 nm/ 5 μm
VD = 3 V
Fig. 4-8 I-V curves of single-gated mode of operation.
Fig. 4-9 Transfer and output (inset) characteristics for DG-1 operation as compared with the sum of the current of two individual single-gated operations.
VG (V)
Fig. 4-10 Transfer and output (inset) characteristics for DG-2 operation as compared with the sum of the current of two individual single-gated operations.
VG (V)
Fig. 4-11 Transfer and output (inset) characteristics for TriG operation as compared with the sum of the current of three individual single-gated operations.
VG (V)
Operation Mode Hollow : individual gate control
SG + TG
Fig. 4-12 ION enhancement under MG control for the data shown in Figs. 4-9~4-11.
Solid symbols indicate ION of MG control, whereas hollow ones represent the sum of ION of individual gate control.
Channel Length (μm)
0 1 2 3 4 5 6
S.S. Improvement (%)
-19 -18 -17 -16
ION Improvement (%) 50 60 70 80 W = t = 35 nm
Fig. 4-13 S.S. and ION improvement versus poly-Si NW channel length under DG-1 control compared with SG mode.
Fig. 4-14 Schematic carrier transport in polycrystalline structure without and with electric field.
Channel Cross-sectional Area (nm2) 1/2x(25x25)
1/2x(35x35)
1/2x(54x54)
S.S. Improvement (%)
-18 -17 -16 -15 -14 -13
Gm Improvement (%) 24 26 28 30 32 34 L = 1 μm 36
Fig. 4-15 S.S. and Gm improvement of poly-Si NW TFT with various channel volume under DG-1 operation with respect to SG mode.
VSG (V)
Fig. 4-16 ID-VSG characteristics of a side-gated transistor with Vset applied to (a) TG, (b) BG and (c) both TG and BG.
Fig. 4-17 Band diagrams of the NW channel with varying VTG or VBG.
Vset (V)
-6 -4 -2 0 2 4 6
Vth (V)
-4 -3 -2 -1 0 1 2
Vth-set by VTG Vth-set by VBG Vth-set by VTG-BG
ΔVth/ ΔVTG =0.12
ΔVth/ ΔVBG = 0.40
ΔVth/ ΔVTG-BG = 0.51 SG mode
Fig. 4-18 Dependence of Vth as a function of Vset in SG operation mode.
VDG-1 (V)
Fig. 4-19 Transfer behaviors of the double-gated transistor with various TG or BG biases: (a) DG-1 mode and (b) DG-2 mode.
Vset (V)
-6 -4 -2 0 2 4 6
Vth (V)
-2.5 -2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5
Vth-set by VBG Vth-set by VTG
DG mode
ΔVth(DG-1) / ΔVset by BG = 0.36
ΔVth(DG-2) / ΔVset by TG = 0.09
Fig. 4-20 Dependence of Vth as a function of Vset in DG operation modes.
Fig. 4-21 For sensing applications, Vset generated from a control circuit (not shown) could be used to set the NW channel potential to a condition most sensitive to the surface charges of the exposing site.
Chapter 5
Sensing Devices Based on Poly-Si Nanowire Field-Effect Transistors
Nano-devices based on silicon nanowire (Si NW) structures have drawn much attention in the recent decade. Si NWs are particularly attractive as sensors because their critical dimension is comparable to the size of chemical and biological species.
Due to its high surface-to-volume ratio, the NW’s sensitivity is greatly enhanced when the signal is effectively transduced. In the preceding chapters, we have investigated and demonstrated the use of poly-Si NW field-effect-transistors (FETs).
With its easy preparation, low-cost, and compatibility with various substrates, poly-Si NW devices are favorable for many applications. However, poly-Si suffers from inherent defects in inter/intra grains that impede carrier transport. This could potentially hinder poly-Si from sensor applications because of sensitivity degradation issue. In this work, we show that such concern is alleviated as long as the operation is carried out in an aqueous solution. Finally, the sensing capability of poly-Si NW devices for detection of pH-value and biomolecules is also presented.
5.1 Introduction
Field-effect transistors (FETs) have been proposed for chemical sensor applications since 1975 by Lundstrom et al., who reported a hydrogen-sensitive FET with palladium as gate metal [5.1]. The fundamental concept is that FETs exhibit a conductivity change in response to variations in the electric field or potential at the surface since the electric field resulting from binding of charged species to the surface is analogous to applying a voltage using gate electrode. In addition to gas detection, FET can also be used to measure pH or ions in aqueous solutions [5.2]. In those early works, the test devices adopted a planar structure having a channel exposed to the environment. During the sensing operation, the channel conductance is modulated by the amount of charges bound to the channel surface. Such scheme is easy to fabricate.
However, the sensitivity is seriously affected by the leakage current from source to drain through the bulk of the substrate. To address this issue, recently a new sensing structure utilizing Si NW as the channel was proposed [5.3]. Si NWs can overcome the limitations of planar FETs because the one-dimensional morphology and nano-scale cross-section of the NW lead to nearly depletion or accumulation of carriers in the channel of the device when a species is bound to the surface [5.3, 5.4].
Also owing to the high surface-to-volume ratio and tiny body, the bulk leakage could be effectively suppressed and thus the sensitivity is greatly improved. Such Si NW
sensors have demonstrated their function and sufficient sensitivity to detect protein [5.3], DNA [5.5], glucose [5.6] and virus [5.7].
The aforementioned works on biosensing applications employed monocrystalline Si NWs as the channel layer. Few defects are contained in such materials, enabling a high carrier mobility which is essential for good device performance. Recently we investigated the use of poly-Si NW channels for building novel electronic devices [5.8, 5.9]. The scheme we proposed could greatly simplify the fabrication process.
However, defects contained in the grain boundaries of the poly-Si NW would impede carrier transport and thus degrade the mobility [5.10]. For biological sensors, the polycrystalline nature of NWs raises the concern of sensitivity degradation. In this work, we show that such concern could be lifted as long as the measurement is carried out in an aqueous solution. Possible mechanism for this phenomenon is also proposed.
5.2 Fabrications of Poly-Si NW Sensors
5.2.1 Fabrications of Poly-Si NW Sensing FETs
The fabrication of the poly-Si NW devices is briefly described as follows: a 90 nm-thick amorphous Si was first deposited on a Si substrate with 100 nm-thick SiO2
source/drain (S/D) regions with phosphorus species, the film was annealed at 600 oC for 24 hours to fulfil dual purpose of Si re-crystallization and dopant activation.
Formations of poly-Si NW channels and S/D regions were simultaneously accomplished by e-beam lithography and the following dry-etching step. Fig. 5-1(a) shows the scanning electron microscopic (SEM) picture of a device which contains six NW channels. Planar width of each NW is 70 nm. Afterwards, a passivation oxide deposited by LPCVD was capped on the wafer surface. The Si NW channels were then exposed by removing the covering oxide, and the entire device was then enclosed in a polydimethylsiloxane (PDMS) microfluidic structure with an aim of performing electrical measurements in an aqueous environment (Fig. 5-1(b)). During the measurements the Si substrate itself serves as the gate electrode upon which a bias is applied to modulate the drain current.
5.2.2 Preparations of Microfluidic Systems
To perform biosensing process, a robust microfluidic channel is required to flow the sample solutions in and out of the sensing site. The microchannels used in this study were fabricated with replica molding technique by employing PDMS as the material. PDMS possesses several advantages, such as good thermal stability,
biochemical compatibility and easy molding. The transparent nature of this material allows the sensing process to be monitored directly by human eyes. Fabrication process of the poly-Si NW sensing device with microfluidic structure is schematically shown in Fig. 5-2 and briefly described as follows:
(1) Using a glass substrate as the master mold and fashioning reverse microfluidic patterns on it.
(2) Mixing PDMS and curing agent with a ratio of 10 to 1, followed by using vacuum pump to degas air in PDMS.
(3) Pouring PDMS onto the master mold and curing it at 80 oC for 20 min.
(4) Carefully peeling off PDMS from the mold, and cleaning PDMS and the NW device with acetone.
(5) Performing O2 plasma treatment on both PDMS and NW devices for 1 min.
(6) Bonding PDMS microfluidic structure to the NW device.
(7) Baking them at 90 oC for 30 min to remove surplus moisture.
Note that the purpose of O2 plasma treatment in step (5) is to create –OH bonds on both PDMS and the NW device surfaces so that PDMS can covalently bond to the NW device. Next, baking the system to expel residual H2O molecules and achieve
better bonding effects. This procedure is illustrated in Fig. 5-3.
5.2.3 Immobilization of Biomolecules on Poly-Si NWs
For the purpose of selectivity and specificity, the poly-Si NW’s surface must be functionalized with a specific molecule to attach the target active compound.
3-aminopropyltriethoxysilane (APTES) has been widely used in affinity-based biosensors because the silane group can tightly bind to Si or glass substrates, while its amine group can form covalent bonds with carboxyl groups (functional groups that are commonly found in biomolecules) [5.11]. The structural formula is show in Fig.
5-4. In this study, the natively oxidized poly-Si NW’s surface provides natural sites for the immobilization of APTES on it. The procedure is briefly described as follows:
(1) Using ethanol to wash the poly-Si NW device.
(2) Immersing the device in 2 % APTES ethanol solution for 30 min.
(3) Washing the device with pure ethanol.
(4) Heating the device at 120 °C for 10 min to remove excess ethanol.
To explore biomolecular sensors, the detection of the reaction between mouse-IgG and anti-mouse-IgG is inspected in this work. The immobilization of
mouse-IgG on the poly-Si NW FET is performed by the following steps:
(1) Immobilizing APTES on the poly-Si NW device as described above.
(2) Mixing the device with 2.5 % glutaraldehyde in phosphate buffered saline (PBS) buffer that contains 4 mM sodium cyanoborohydride for 1.5 hours.
(3) Washing the device with PBS buffer.
(4) Coupling mouse-IgG (50 μg/ml) in PBS buffer that contains 4 mM sodium cyanoborohydride to the surface of NW for 9 hours.
(5) Washing the device with PBS buffer.
(6) Blocking the un-reacted aldehyde groups with ethanolamine.
(7) Washing the device with PBS buffer.
To carry out the biosensing process, anti-mouse-IgG (6.9 μg/ml) and α-rabbit-IgG (9.3 μg/ml) were used for experimental and control groups, respectively.
To carry out the biosensing process, anti-mouse-IgG (6.9 μg/ml) and α-rabbit-IgG (9.3 μg/ml) were used for experimental and control groups, respectively.