Outcontrol

Just like RX_DV is pulled up when PHY send data to FPGA in upstream steps, here we also pull up TX_EN when FPGA send data to PHY. In this module, it also controls the enable pin of buffero, we can see how it works in figure3.18. If data are recognized in main PON MAC, packet length is recorded and sent to outcontrol module. Notice the red circle, the length is been recorded. If another packet is coming, the lengths are then been added. Now we know how many bytes there in the buffer, so the module pulls up TX_EN pin and send the data out. All the works in down stream steps are now done.

Simulation results for outcontrol are shown in figure3.18.

Figure 3.18 Simulation results for outcontrol

3.4.4 Simulation Result

The RTL scheme is shown in figure3.19.

The simulation result after post-place & route can be seen in figure3.20, we can see that header is removed, and after TX_EN pin is pulled up, the output are then of 4 bits in 25 MHz.

Figure 3.19 RTL scheme of the full downstream module

Figure 3.20 Simulation result for full downstream module after post-place & route

CHAPTER 4 ONBOARD TESTING

4.1 Field Programmable Gate Array (FPGA)

A field-programmable gate array is a semiconductor device containing programmable logic components called "logic blocks", and programmable interconnects. Logic blocks can be programmed to perform the function of basic logic gates such as AND, and XOR, or more complex combinational functions such as decoders or simple mathematical functions. In most FPGAs, the logic blocks also include memory elements, which may be simple flip-flops or more complete blocks of memories [26].

Field Programmable means that the FPGA's function is defined by a user's program rather than by the manufacturer of the device. A typical integrated circuit performs a particular function defined at the time of manufacture. In contrast, the FPGA's function is defined by a program written by someone other than the device manufacturer. Depending on the particular device, the program is either 'burned' in permanently or semi-permanently as part of a board assembly process, or is loaded from an external memory each time the device is powered up. This user programmability gives the user access to complex integrated designs without the high engineering costs associated with application specific integrated circuits [27].

In our experiment, we use a Xilinx Virtex-4 FPGA. Table4.1 shows the specification of it. The FPGA is just one part of our board, but it’s the most important.

The verilog module we write in chapter 3 is loaded into the FPGA, and works the way we want.

1490nm/1310nm/1550nm

Figure 4.1 ONU Board front view

Figure4.1 shows the board of ONU. The component which is been circled is our Virtex4 FPGA. We drive the board in about 0.4mA (12V). When we have simulated, synthesized our design, we generate a bit file, and download it on to FPGA using a Xilinx iMPACT. The board is now working according to the functions we design. To assure that it is really working, we can give input data and get output data through the test pins. We can see the test pins are in the bottom of figure4.1.

The board and computer are connected using a network line. We use EthView to generate Ethernet packets and send into the board. The serial data are converted to parallel data in the physical layer (PHY). The data are then been sent into FPGA. We use Logic Analyzer (LA) to get the output in the test pins. Finally, we can show that our FPGA does work or not.

4.3 Testing Result

The target of this design is to connect ONU and OLT, and transfer data between central office and users. If we want to see the signals in the output, we assign the output pins to the test pins of the board. After that, we use a Logic Analyzer, which displays signals in a digital circuit that are too fast to be observed by a human being and presents it to a user so that the user can more easily check correct operation of the digital system.

The equipment we use is shown in figure4.2. We can then get the output data by connecting the probes to the test pins. We can see how they are connected in figure4.3.

Comparing the input data and the output data, we can see if our design works.

Now, we check the up stream module and down stream module separately.

Figure 4.2 Logic Analyzer

Figure 4.3 LA Probes

4.3.1 Up Stream

In upstream process, we use EthView to collect packets on the network. After that we connect the board and computer using a network line. EthView can continuously send the packets we have picked. As we can see in figure4.4, we send the selected packets to the board. The data of the packets are also shown in the figure.

Logic Analyzer now shows the output in the screen. We can see the results in figure4.5 to figure 4.9.

Figure4.5 shows that our module has successfully separated the packet into slots.

Figure4.6 and Figure4.7 show that the header is added in front of the packet, the data also match the data we send in. Figure4.8 and Figure4.9 show that at the end of the packet, we add idle signal 16’hAAAA. After that, the next packet is started.

Figure 4.4 Ethernet Packet

Figure 4.5 Packet has been separated into slots

Figure 4.6 The header

Figure 4.7 Data of the slot

Figure 4.8 The end of the packet

Figure 4.9 Next packet comes in

In figure 4.10 we send a short packet of 60 bytes only. We can see that only one slot is presented.

Figure 4.10 60 bytes packet

4.3.2 Down Stream

In down stream process, the data it receives should be from OLT. If we want to test ONU part only, we should generate the packets by our own. So we again write a module to generate Ethernet packets and send into the input of the first module of the down stream modules.

Figure4.11 shows the data we send in, we set the MAC address to be 16’h0001, 16’h0003, 16’h0007. In figure4.12, we can see clearly that the header has been removed, the data start at MAC address. We can also see our packet in figure4.13, the data perfectly match the data we send in.

Therefore, we are sure that our module for down stream does work in the ONU board. Thus we can now try to connect OLT and ONU. It’s our future work.

Figure 4.11 Data sent into the down stream module

Figure 4.12 MAC address of output data

Figure 4.13 Output data

CHAPTER 5 CONCLUSION

5.1 DHPON

Passive Optical Networks are the basis of FTTx access applications. Within the access network, there’s no active components, therefore require little maintenance and have a high MTBF (Mean Time Between Failures). PON also Provides higher bandwidth due to deeper fiber penetration, and it has Longer distances between central offices and customer premises. PON is Easy to upgrade to higher bit rates or additional wavelengths, and Share their costs of fiber and the equipment at the central office among multiple customers

However, PON also suffers from serious problem that packet delay might occur due to the long round trip time. Some bandwidth might also be wasted in this situation.

Therefore a distributed-control hybrid passive optical network is introduced. In this architecture, it contains both TDM and WDM system. Distributed-control dynamic bandwidth allocation is worked close to a few ONU. A shorter RTT means the packet delay problem is solved. The queue sizes are updated quickly because control massage and data transmitting are using different wavelength. Now, we have theoretically known that DHPON does have some advantage compare to the traditional PON.

5.2 Future work

The design for Optical Network Unit (ONU) is successfully worked. In the upstream part, after user sending packet to ONU, our module divides the packet to some 280 bytes slots. Each slot contains 12 bytes header including 8 bytes Preamble, 1 byte delimiter, 1 byte ONU-ID and 2 bytes payload length. In the downstream part, ONU

receive packets from OLT. Our module then remove header of the packet and check the MAC address. If the MAC address matches the ONU, the packet is then send to user. On the other hand, the design for Optical Line Terminal (OLT) is also done by Chien-Ho Fang.

Therefore, we have successfully set up an OLT and ONU that send and receive Ethernet packets. To complete the whole architecture, we now start to connect OLT and ONU together. We’ll check both upstream and downstream flow and compare the packet that sent in and sent out. After that we’ll work the distributed-control DBA among several ONUs. Finally, we’ll set up a real distributed-control hybrid passive optical network.

In the end, we will prove that our DHPON will work in the real world and how it is superior to the traditional PON.

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