CHAPTER 1 INTRODUCTION
1.1 Overview
In advanced vehicle control system, steering control plays an important role. It should take appropriate actions in according to the inputs such as speed, yaw rate and steering angle. The reason why we choose FPGA to be the experimental platform is that FPGA can be implemented for real-time applications.
To implement real-time control, we also need sensitive sensors for measuring steering angle and yaw rate. We usually do some modification of steering angle while driving so that the steering angle sensor would be effective and precise enough to transmit data.
Lateral velocity and yaw rate are the central in lateral control systems [1]. In this thesis, we consider the relationship between yaw rate and the steering actuator. The basic architecture we use for the lateral control system is composed of a fuzzy logic controller, a steering actuator and a vehicle for our experiment [2]. The input of the system is the desired path and the output is the real path. The steering actuator is treated as a subsystem of a lateral control system, it contains a motor, driving circuits and the steering wheel.
Steer-by-wire system [3] has big advantages of packaging flexibility, advanced vehicle control system and superior performance. Steer-by-wire system has no mechanical linkage between the steering gear and the steering column. It’s possible to control the steering wheel and the front-wheels independently [6, 7].
The fuzzy logic controller (FLC) for lateral control has been proposed in [4, 5]. The parameters of FLC are tuned manually according to human experience in driving. The FLC deals the useful information, such as yaw rate, and then sends commands to the steering actuator. In this thesis, FLC receives the feedback data of yaw rate, calculates the error and
commands to the actuator. Hence, the output from the actuator will change with the yaw rates and the steering angles [8].
In addition to the actuator and the controller, the CAN-BUS (Controller Area Network BUS) based sensor for measuring steering angles is important. In order to receive the data from this sensor we use several devices such as 8951, CAN-BUS stand-alone controller, and a transceiver [8-12] for implementation.
1.2 Organization of the thesis
Decoding the data through CAN-BUS is the first important part of this work because it can transmit a lot of data in a short period of time. The details of CAN BUS and other peripheral circuits will be mentioned in Chapter 2.
The next important step is controller design. After studying previous literatures, we know that it is necessary to control the steering angle first and then to determine the method to control the yaw rates. In the first step, we will use PD controller which can modulate both the speed and directions of steering. And then, we choose fuzzy logic for yaw rate control. Details will be discussed in Chapter 3.
How to implement the system is described in Chapter 4. In previous literatures [15, 19-24], there are some ways for implementation. For convenience, we will use sequential circuits to do the work in FLC step by step.
After designing the system, we must test and verify it in our experimental car. The results will be shown in Chapter 5.
In Chapter 6, conclusions and future researches will be addressed.
Chapter 2
Peripheral Circuits
The steering control system is composed of a motor, a motor’s driver, two sensors (steering angle sensor and yaw rate sensor), and 8951 subsystem for CAN-BUS steering angle decoding [8]. The external input is pre-defined yaw rate, which is the reference command used for controlling the steering behavior. The steering angle and yaw rate are the feedback data we obtained by the two sensors. The motor is controlled with three control signals and the steering wheel is its load. In order to control the motor, the controller transmits three signals to motor’s driver with the feedback data. As the steering wheel is turning, we can get the steering angle and yaw rate immediately and reduce the difference between the output and our target.
The steering controller, implemented by FPGA development board, receives the sensor’s data as the feedback. The 8951 subsystem is composed of a 89C51, a stand-alone CAN-BUS controller (SJA1000) [10] and a transceiver (PCA82C251) [11]. They convert the CAN-BUS signal to 16-bit value and transmit it to the controller with communication to the FPGA board.
The A/D converter transfers the analog data to digital ones as the feedback to the controller.
We use the steering angle sensor and gyro to obtain the steering wheel angle and yaw rate of the experimental car.
2.1 Introduction to CAN-BUS protocol
Figure 2-1 Layer’s architecture
Figure 2-2 CAN’s physical structure [10]
CAN defines a physical layer and data link layers as shown in Figure 2-1 [9]. Physical layer includes the definition of transmission medium and logic level. In general, CAN network uses two signals named CANH and CANL to access the information, and the terminals should be two 120Ω resistors shown in Figure 2-2.
Since it transmits data by two serial streams, the definition of logic level is different .It can be expressed as the binary values, 1/0.
Binary ‘1’ is called recessive bit (CANH= CANL=2.5V) and binary ‘0’ is called dominant bit (CANH=3.5V; CANL=1.5V). Since the binary value is presented with the difference, bit level = (CANH+δ)-(CANL+δ), it has good capability of EMI noise rejection.
Data link layers define the format, message filter, bit rate and arbitration. Here is some brief introduction of CAN’s characteristics.
Data frame:
Figure 2-3 Data frame format
As shown in Figure 2-3, arbitration field includes CAN’s ID (ex. the steering angle sensor is 0C0) and RTR bit. Every message has an identifier, which is unique within the whole network since it defines content and also the priority of the message. The identifier with the lowest binary number has the highest priority.
Arbitration:
Whenever the bus is free, any node may start to transmit a message. If two or more nodes start transmitting messages at the same time, the bus access conflict is resolved by bit-wise arbitration using the identifier. The mechanism of arbitration guarantees that neither information nor time is lost. All nodes with lower priorities do not re-attempt transmission until the bus is available again.
2.2 8951 subsystem [9-11]
In order to receive the CAN BUS signal and covert it to 16-bit data, 8951 system is composed of a transceiver (PCA82C251), a stand alone controller (SJA1000), and a 89C51.
2.2.1 Transceiver
Transceiver is the interface between stand-alone controller and the physical layers of CAN network which converts CANH and CANL from physical layers to serial stream signals as the
transceiver.
Figure 2-4 shows the transceiver’s pins and its internal blocks. The most important ones are CANH (Pin 7), CANL (Pin 6) and RXD (Pin 4). Because we use it only for receiving data, only these three pins should connect to the stand alone controller. The receiver’s comparator converts the differential bus signal to a logic level signal which is the output at RXD. The serial receive data stream is provided to the bus protocol controller for decoding.
Figure 2-5 [9] shows the bus state: When CANH and CANL are both 2.5V, the bus is recessive (logic‘1’). When CANH is 3.5V and CANL is 1.5V respectively, the bus is dominant (logic‘0’).
Figure 2-4 CAN Transceiver
Figure 2-5 CAN BUS state
2.2.2 Stand-alone controller and 89C51
Figure 2-6 Block diagram of SJA1000
Figure 2-6 shows the block diagram of SJA1000 [10]. The CAN Core Block controls the transmission and reception of CAN frames according to the CAN.
The Interface Management Logic block performs a link to the external host controller which can be a microcontroller or any other device. Every register access SJA1000 multiplexed address/data bus and controlling of the read/write strobes is handled in this unit.
When receiving a message, the CAN Core Block converts the serial bit stream into parallel data for the Acceptance Filter. With this programmable filter, SJA1000 decides which messages actually are received by the host controller.
All received messages accepted by the acceptance filter are stored within a Receive FIFO.
Depending on the mode of operation and the data length up to 32 messages can be stored.
Figure 2-7 shows the 8951 subsystem circuit [10]. Port 0 of 8951(address/data bus) is used to communicate with the stand alone controller SJA1000. We can set the register value in SJA1000 via this address/data bus. Since 8951 treats SJA1000 as the external memory, the address/data bus should cooperate with /RD and /WR signals.
To set the register value, we should notice the mode of SJA1000 (reset mode or operation mode), this will be mentioned later.
Figure 2-7 8951 subsystem
Pin 11 of SJA1000: select the host controller family with Intel or Motorola mode.
Intel mode: Mode=high Motorola mode: Mode=low
The SJA1000 can operate with an on-chip oscillator or with external clock sources.
Additionally CLK OUT (Pin 7) can be enabled to output the clock frequency for the host controller.
2.2.3 Set the registers of SJA1000
When power on (SJA1000 is reset mode), we can set the registers:
(a) Acceptance code. (b) Acceptance mask
They can set the acceptance filter.The received data is compared bitwise with the value contained in the Acceptance Code register (ACR). The Acceptance Mask Register (AMR) defines the bit positions, which are relevant for the comparison (0 = relevant, 1 = not relevant).
For accepting a message, all relevant received bits have to match the respective bits in ACR.
In other words, if we set the AMR as “11111111”, all identifiers can be accepted.
Figure 2-8 An example of acceptance filter Figure 2-8 explains how the acceptance filter works.
The registers shown below are set in reset mode.
(1) Bus-timing registers (2) Output control register (3) Command register
When Pin 17 is low, SJA1000 enters operation mode. It starts receiving data and transmitting the 16-bit value to host controller. Figure 2-9 shows the flow diagram of data reception [10, 12].
The host controller reads the Status Register of the SJA1000 on a regular basis, checking if the Receive Buffer Status flag (RBS) indicates that at least one message has been received.
The Receive Buffer Status flag indicates “empty” means no message has been received. The host controller continues with the current task until a new request for checking the Receive Buffer Status is generated. The Receive Buffer Status flag indicates “full” denotes one or more messages have been received.
Figure 2-9 Flow diagram of reception of a message [10,12]
Figure 2-10 Timing diagram of transmit data to controller
Tx2 is a control signal generated by host controller. At its negative edge, host controller transmits high-8 bits steering angle data from Port 1. At its positive edge, host controller transmits low-8 bits steering angle data from Port 1.
2.3 Steering angle sensor
This sensor transmits signed 16-bit data (range:-7800~7800) and its identifier is 0C0 (hex), so the acceptance code of SJA1000 is 0C0 (“00001100000”).
The sensor is Basic-CAN (CAN 2.0A) mode since it has 11-bit identifier.
Table 2-1 Information of steering angle sensor Value in the message
(hex)
Value in the message (decimal)
Angle value in° remark
E188 -7800 -780° Negative limit angle
range
1E78 7800 780° Positive limit angle
range
7FFF 32768 3276.8° invalid
Figure 2-11 Steering angle sensor
It is put around the steering wheel. When the steering wheel is turning, the sensor is also turning and measuring the steering angle. Figure 2-11 shows the steering angle sensor which mainly uses 4 pins: (1) GND, (2) +12V, (3) CANH, (4) CANL.
2.4 Sketch of the yaw rate sensing system
Figure 2-12 shows the yaw rate sensor. The red wire is connected to +5V, the green wire is connected to GND and the white one is connected to output. It should be fixed to sense the yaw rate of the vehicle.
Figure 2-13 Peripheral circuits of yaw rate sensor
Figure 2-14 Comparison
Figure 2-13 shows yaw rate sensor peripheral circuits. Two OP amplifiers form a low pass filter. Since the signal from yaw rate sensor is easily disturbed by high frequency noises, the filter can reduce them. The output of low pass filter is treated as the input of ADC0804.
Figure 2-14 shows the results with and without low pass filter. The upper signal is processed by low pass filter and the lower one is the original signal from yaw rate sensor.
ADC0804 converts the analog sensor output to 8-bit digital input of FPGA, the pins /CS and /RD are tied at ground, and /WR control signal is fed by FPGA. At negative edge of /INTR, FPGA receives data from Pin 11 to Pin 18.
2.5 Actuator
Figure 2-15 is the block diagram of actuator which is composed of a motor, motor’s driving circuit and the steering wheel. This can implement the concept of steering by wire technique.
The steering wheel is the load of motor, which is driven by the motor.
Figure 2-16 shows the motor with its driving circuit and the steering wheel, there are several pins used for control. The most important is the switch which is directly operated by users so that the motor rotates if we press the switch.
Figure 2-16 The Actuator
Our plant (motor) is associated with its driving circuit. In order to control the motor, we should transmit control signals to this driving circuit such as pulses. There are several methods to control the motor, the one we choose is to control rotation speed and rotation directions.
Figure 2-17 shows the control signals of motor, which include the pulses and direction control signals. The higher frequency makes the steering wheel rotate faster. Sign 1 and sign 0 control the direction of rotation. But the frequency should be in the range of [0, 20khz]. High frequency may cause the motor damage.
Figure 2-17 Control signals of motor
Chapter 3
Design of Vehicle Lateral Control Systems
Figure 3-1 describes the block diagram of proposed lateral control system. The FLC decides the desired steering angle. The inputs of FLC are error of yaw rate and the change of error. The output is treated as the command of the PD controller. It can not only reduce the difference between the actual steering angle and the desired one but also tune the speed of rotation. The desired yaw rate is predefined with the fixed path (ex: circle-path, s-path, etc.), at the low speed (ex: 20 km/h). The device “dSPACE” used to record the yaw rate.
Figure 3-1 The block diagram of proposed lateral control system 3.1 PD controller
Figure 3-2 shows the PD controller [13], where kp is proportional gain and kd is derivative gain. As mentioned in Chapter 2, the direction and speed are two most important behaviors we should consider.
First, we make the motor rotate in positive direction if the error is positive. (i.e. actual angle
< desired angle ) and vise versa.
Second, we make the motor rotate smoothly. In general, human rotates the steering wheel faster when the change of steering angle is larger. P control can implement this action. We must notice that the change of rotation speed should not be too large since the steering wheel will not rotate smoothly. In other words, D control produces little regulation to make the speed not too fast. When the error is positive, the regulation is negative. Otherwise, when the error is negative, the regulation is positive. It can improve the transient performance. For the whole system, the PD controller can be viewed as time delay since it just affects the yaw rate by means of controlling the steering wheel. And it ensures the steering angle is identical to the output of FLC.
3.2 Introduction to FLC
Figure 3-3 Basic architecture of FLC
As shown in Figure 3-3, FLC is composed of four important parts [14].
(1) Fuzzifier: a fuzzifier performs the function of fuzzification which is a subjective valuation to transform measurement data into valuation of a subjective value.
Hence, it can be defined as a mapping from an observed input space to labels of fuzzy sets in a specified input universe of discourse.
Ex:
NB (negative big); NM (negative medium); NS (negative small);
ZE (zero)
PB (positive big) ; PM (positive medium); PS (positive small).
(2) Fuzzy rule base: fuzzy control rules are characterized by a collection of fuzzy IF-THEN rules in which the preconditions and consequents involve linguistic variables.
The general form of fuzzy control rules in the case of multi-input-single-output systems (MISO) is:
Ri: IF x is A, AND y is B THEN z=C (3.1) i =1,2,3,…,n
where x, y and z are linguistic variables representing the process state variables and the control variables, respectively. A, B and C are the linguistic values of the linguistic variables x, y, and z in the universe of discourse U, V and W, respectively.
(3) Inference engine: this is the kernel of the FLC in modeling human decision making within the conceptual framework of fuzzy logic and approximate reasoning.
This is an example:
IF x is A, THEN y is B.
x is A1.
Conclusion => y is B1.
There are four operations usually used:
a. Max-min operation.
b. Max product operation.
c. Max bounded product operation.
d. Max drastic product operation.
(4) Defuzzifier: it is a mapping from a space of fuzzy control actions defined over an output universe of discourse into a space of nonfuzzy (crisp) control actions. This process is necessary because in many practical applications crisp control actions is required to actuate the control. There is no systematic procedure for choosing a defuzzification strategy. Two common used methods of defuzzification are the center of area (COA) method and the mean of maximum (MOM) method.
Because we get the feedback data via 8-bit A/D (ADC0804), the original yaw rate is in the range [0,255]. Where 0(“00000000”) represents -100°/s and 255(“11111111”) represents +100°/s.
Figure 3-4 Fuzzification.
In our experiments, we don’t turn the steering wheel to extreme angles (i.e. too positive or too negative angles.) because we don’t drive the cars like this. So the error and change of error won’t be too large. (-100°/s~+100°/s)
First, the inputs e(k) and ∆e k( ) must be normalized into the range [0,255] for convenience. If e(k) or ∆e k( ) is positive, it will be normalized into the range [128,255], and if e(k) or ∆e k( ) is negative, it will be normalized into the range [0,127]. Figure 3-4 is the diagram of fuzzification.
3.4 Rule base
In Section 3.3, the inputs e(k) and ∆e k( ) both have 7 linguistic variables {NB, NM, NS, ZE, PS, PM, PB}. There are 49 rules. Let u(k) be output linguistic variable.
Rule (1): IF e(k) is PB and ∆e k( ) is NB THEN u(k) is ZE.
.
Rule (25): IF e(k) is ZE and ∆e k( ) is ZE THEN u(k) is ZE.
. .
Rule (49): IF e(k) is NB and ∆e k( ) is PB THEN u(k) is ZE.
Table 3-1 Look-up table
3.5 Inference engine
The method we use is singleton mechanism which is modified from max-min operation.
Figure 3-5 shows singleton inference mechanism which is similar to max-min operation [15].
It is more convenient to store the centers of all triangles with lower membership values of min product so that it can reduce the complexity when defuzzyfing.
Figure 3-5 Singleton inference mechanism
3.6 Defuzzification
The output of fuzzy inference is a linguistic value. For control, we need to transfer it to a crisp value which is treated as a command of motor-steering wheel system. In our experiments, this crisp value must be mapped to the desired steering angle as shown in Figure 3-6.
Use (3.2), we can derive the center of gravity so that the linguistic output of FLC can be obtained.
In Section 3.5, we use singleton of inference mechanism to reduce the complexity in defuzzyfication. It is more convenient since the modified mechanism uses less point than max-min operation to calculate the crisp output. Also, it saves operation time when the implementation is done with FPGA.
Figure 3-6 Relationship between FLC output and motor-steering wheel desired angle
Chapter 4
Implementation of Vehicle Lateral Control Systems
FPGA (Field Programmable Gate Array) is the kernel of the system because of its speed of process and flexibility. We must write the functions with VHDL and then download them to the development board. If we will change the contents of the functions, we only re-write and download the new functions again after compiling.
In Figure 4-1, ALTERA Stratix EP1S25 DSP development board is included with the DSP Development Kit, Stratix Edition. This board is a powerful development platform for
In Figure 4-1, ALTERA Stratix EP1S25 DSP development board is included with the DSP Development Kit, Stratix Edition. This board is a powerful development platform for