Chapter 7 Integer Factor Decimator
7.4 Performance
The simulation platform in Fig.7.8 is similar to the one used in chapter 6.4. All elements’ specification is the same except that the integer factor decimator is added.
Figure 7.8: Simulation platforms for integer factor decimator
To make improvement in chapter 6 visible, three half-band filters are not those introduced in chapter 7.3 but the sinc-filters are used. The benchmark’s parameters are:
source signal bandwidth π/16, a.b = 1.1649, c = 8, and 4-levels sigma-delta modulators. The fractional factor decimator with 1st order and 2nd order sigma-delta modulators are tested. Result is shown below.
If the final stage uses the half-band filters introduced in chapter 7.3, then the performance improvement of using 2nd order sigma-delta modulator is no longer significantly as shown in Fig. 7.10. This is because that these three half-band filter’s pass-band ripple is 0.01dB, which is larger than the error caused by timing jitter.
Therefore, to take advantage of using 2nd order sigma-delta modulator, the pass-band ripple of half-band filters needs to be further reduced.
Figure 7.10: Output signal error PSD of overall SRC scheme using non-ideal filters
7.5 Summary
In software radio system, the decimation ratio’s range may be very large. To satisfy the requirement, variable rate decimation architecture is introduced here. The SCIC filter resolves CIC filter’s problem which is introduced in chapter 7.2. To resolve large transition band of SCIC/CIC filter, series of FIR filter are used to remove unwanted frequency component. The half-band filters can be implemented efficiently
Chapter 8
Conclusion
The work of this thesis is concentrated on the timing tracking scheme. First, the error caused by the timing jitter is analyzed comprehensively where the 1st order error residue is the majority one and property is also validated by simulation. Based on such property, we would like to build certain timing tracking scheme such that the corresponding timing jitter is high pass. The solution is the use of sigma-delta modulator.
The 1st order sigma-delta modulator, which suffers strong limited cycle problem, is not suitable for this application. We have also proven that the traditional timing tracking scheme (NCO) is actually the same as using 1st order sigma-delta modulator.
By slightly modifying the original timing tracking scheme, from 1st order to 2nd order sigma-delta modulator, the behavior of timing jitter in frequency domain becomes desired high-pass response and we can take advantages of such property. In traditional approach (NCO), the only way to combat the error caused by timing jitter is to increase the resolution of interpolator, which reduces the amount of timing jitter.
The method enhances the resolution of interpolator which may increase chip area, power and limits the circuit speed. By using the method proposed in this thesis, we can achieve the same performance while using lower-resolution modulator. The changes are not much, but gracefully resolve the problem using NCO timing tracking scheme.
Higher-order sigma-delta modulator, if the modulator could be stable, could also
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