Parallel CIC-filter

CIC stands for Cascaded-Integrator-Comb which was first proposed in [21]

which can implement economical digital decimator and interpolator. Basic CIC filter consists of integrator stage and differentiator stage shown in Fig. 4.11. The CIC filter presents several advantages over basic implementation of decimation and interpolation filters:

z No multipliers are required,

z No storage is required for filter coefficients

z The structure of CIC filters is very regular, consisting of two simple building blocks

z Very little external or complicated control is needed

Figure 4.12: Integrator stage and differentiator filter stage

The CIC interpolator’s structure is shown in Fig. 4.12. The differentiator stage’s delay is unit-delay. To analyze the interpolator’s frequency response, we need an additional identity in Fig. 4.13. With the identity, we can exchange the up-sampler and differentiator in Fig. 4.12 and writes the z-domain representation of the system

1

Figure 4.13: Three-stage CIC interpolator

Figure 4.14: The interpolator identity

The up-sampler in Fig. 4.12 results in high intermediate circuit speed which is undesired. [3] proposed a parallel CIC structure which parallelizes the integrator section in Fig. 4.12 such that keeps the circuit speed unchanged.

Fig. 4.13 shows a parallel CIC structure. First, the input signal is fed into the differentiators. Then, the operation of interpolated cascaded integrators can be described by the state-space recursion. The adders are implemented as carry-save adders (CSA) in order to avoid carry propagation and obtain high-speed circuit. The adder arrays are arranged by using the retiming technique to further speed up the circuit. All the digital circuits of the parallel CIC structure operate at the same clock rate, which is identical to the input from differentiators.

4-2

Figure 4.15: Parallel CIC Structure

4.4 Summary

In this chapter, the continuous and discrete B-spline interpolation mathematic backgrounds are discussed. We have discussed the performance of the B-spline interpolator in the frequency domain and the way to simplify the B-spline interpolator and its performance loss. Finally, we covered the circuit architecture for the pre-filter and parallel CIC-filter.

Before closing the chapter, we will remind the reader that the purpose of using B-spline interpolator is to “simulate” a virtual ADC running at m times fast the physical ADC. The designer should carefully select the B-spline parameters including B-spline order n, length of pre-filter, the structure of CIC-filter, and whether to omit post-filter.

Chapter 5

Mathematics Model for Fractional Factor Decimator

In this chapter, fractional factor decimator’s timing jitter model is developed. As mentioned in chapter 3, the decimator doesn’t use fractional delay filter but “select”

incoming signal as output. Under such scheme, the majority of error comes from timing jitter. Therefore, before we start to build the decimator, it is crucial to understand the effect of timing jitter first.

5.1 Introduction

Fractional factor decimator decreases the sample rate by a factor “a.b” where a is integer and b is fraction. Let us review the block diagram in Fig. 3.1. The sampled signal is interpolated by B-spline interpolator. Assume that B-spline interpolation is ideal, we can treat the interpolator’s output as signal sampled by a faster ADC. Thus, the function of B-spline is to enhance time domain resolution of sampled signal.

Intuitively speaking, because the decimator would only perform simple and low-resolution interpolation to the input signal, it is reasonable to use heavily over-sampled signal as the fractional factor decimator’s input.

When developing the decimator’s mathematical model, B-spline is used to model the continuous-time signal. B-splien interpolation theory will be revisit in chapter 5.2.

Mathematical model of timing jitter will be covered in chapter 5.3. Based on the

model, we will develop the design guide of fractional factor decimator in chapter 5.4.

5.2 B-spline Interpolation Revisit

The first two blocks in Fig. 3.1 are re-drawn in Fig. 5.1 to emphasize internal operation of B-spline interpolator.

 ( )ⁿ

x t x k [ ]ⁿm

Figure 5.1: Idea of B-spline interpolation

Continuous-time waveform x(t) is sampled by ADC and x[k] is sampled signal.

x[k] is interpolated by B-spline interpolator and  [ ]

x k is its output. Within B-spline

ⁿm

interpolator, continuous-time interpolated waveform  ( )

x t is constructed by x[k]:

ⁿ



( ) ( ( )

^{1 1}

) ^{( ) ( )}

The error between interpolated waveform  ( )

x t and original waveform x(t) can be

ⁿ controlled by varying B-spline order n. With higher order n, error is getting smaller.

By properly selecting B-spline order n,  ( )

x t is good replacement to x(t).

ⁿ

The reason to use continuous-time interpolated waveform  ( )

x t is because in

ⁿ later paragraph, we need to calculate differentiation of x(t) which is hard to find close form analytic solution. But when working on  ( )

x t , B-spline basis provides good

ⁿ properties to accomplish the task. As error between  ( )

x t and x(t) is small enough,

ⁿ

5.3 System Model

The decimation factor is a+b, where a is integer and 0≦b<1. As we mentioned earlier, the fractional factor decimator decrease the sample rate by “selecting”

incoming signal. In other words, we would like to generate a sampling period sequence {

τ

k

} satisfying

The amount of timing jitter is assumed to be less than q. Fig. 5.2 illustrates the relationship of

τ

k, Ik and

ε

_k.

τ

1

τ

₂

ε 1 ε 2

(

^{a b+ ⋅}

)

¹

(

a b+ ⋅

)

2

Figure 5.2: Sampling time, sampling time residue and sampling time sequence

Using ^{x knm[ ]=x k mn}

(

^/

)

, we can connect ^x I^nm

[ ]

k and continuous waveform ^{x tn}

( )

which shows the amount of timing jitter in continuous time:



[ ]

^{ }

^{( )}

By intuition, as the expanding factor m getting larger, the timing jitter

ε

_k

m

reduces.

As timing jitter is small enough, we can apply Taylor’s series on eq. (5.6) to disassemble x I^nm

[ ]

k as sum of derivatives of  ( )

x t :

ⁿ



[ ] ^{( )}

^{( )}

^{( )}

n

,

1

correct sample error residue in terms of derivative of x (t)

1

How to find the differentiation?

The derivative of continuous B-spline basis is already discussed in chapter 4.1.3, rewrite it here for convenience:

( ) ( )

Time domain representation of eq. (5.9) is

( )

¹

{ ( ) } ^{( ) ( )}

where delay operator D^l

(z) is defined as

( ) (

^{12 12}

)

^l

D z

l =

z

−

z

⁻ . (5.11)

with continuous-time basis

^β

^{n l−}

(

^{t k−}

)

. The reason is that it is more convenient to process delay operation in discrete time domain than continuous time domain. One can find that digital coefficients and continuous waveform are separated. We will use the technique to perform continuous operation such as differentiation while leave digital coefficients unchanged. Therefore, the differentiation of ^{x tn}

( )

in eq. (5.8) is

 ^{( )}

( )

^

( )

In eq. (5.14), to reflect the effect of expanding factor m, we can use the property in chapter 4.1.7 to change B-spline basis from

^β

^{n l−}

( )

^{t to}

^β

^{n l−}

( )

^{mt :}

In eq. (5.15), within the bracket of digital operation, x is replaced by

x

ⁿ. The

replacement takes the effect of m-fold expansion into consideration. Now, eq. (5.15) is already decomposed as sum of correct sample and error residue. The error residue is defined below directly is somewhat difficult, so we will apply a series of simplification to extract essential information.

Holder’s Inequality

Holder’s inequality is defined as

1 1 of a vector. Two terms in the right hand side of Holder’s inequality are p-norm and q-norm respectively. Basically, there are three types of norm which are commonly used:

z 1-norm is the absolute sum of a sequence:

1

z 2-norm is the Euclidean length of a sequence:

1

z Infinite-norm is the maximum absolute value of a sequence:

The result shows that the error residue is bounded by maximum absolute value of

, , ( ) where we imposed an upper bound:

( ) ( ^{( )}

¹

) ^{( )}

After applying the upper bound q to

ε

_k, the result is no longer related to amount of timing jitter of k^th output. Therefore, we omit the index k and have

S

_m^{n l,}( )

s

. Analyzing

,( )

To measure the largeness of error residue in frequency domain, from [30], we define the p-norm ( p > 1) of a Fourier transform

H e

( ^jω) as

Applying Holder’s inequality given by [30] to eq. (5.28),

, , , , ,

and (p, q) = (2, 2):

Table 5.1 ~ 5.4 are 1-norm and 2-norm of several combinations of l and m with n

= 3 and n = 5. The maximum value of sampling time residue is set to 1.

N=3 m=4 m=8 m=16 m=32 m=64

l=1

9.53 15.7279 21.8059 27.8445 33.8723

l=2

20.6658 32.7070 44.7482 56.7894 68.8306

l=3

32.4535 49.6309 66.9564 84.3883 101.9001

l=4

44.3766 65.4487 86.5208 107.5929 128.6650

Table 5.1:

^3, ( )1

l j

Fm e^ω with different l and m

N=5 m=4 m=8 m=16 m=32 m=64

l=1

9.6506 15.9207 22.0024 28.0387 34.0652

l=2

21.2585 33.5623 45.6717 57.7301 69.7756

l=3

33.9747 52.2639 70.4002 88.4848 106.5533

l=4

47.3771 71.4594 95.5418 119.6242 143.7066

Table 5.2:

^5, ( )1

l j

Fm e^ω with different l and m

N=3 m=4 m=8 m=16 m=32 m=64

l=1

6.8614 11.5293 16.0819 20.6066 25.1244

l=2

18.1020 28.7830 39.3569 49.9025 60.4410

l=3

30.3272 46.8838 63.4404 79.9971 96.5537

l=4

42.5468 63.6189 84.6910 105.7631 126.8352

Table 5.3:

^3, ( ) 2

l j

Fm e^ω with different l and m

N=5 m=4 m=8 m=16 m=32 m=64

l=1

6.5702 11.3282 15.9031 20.4333 24.9524

l=2

17.896 28.6734 39.2688 49.8197 60.3594

l=3

30.5346 47.3005 63.9086 80.4781 97.0379

l=4

44.1247 66.8692 89.4904 112.0787 134.6588

Table 5.4:

^5, ( ) 2

l j

Fm e^ω with different l and m

Figure 5.3: Error upper bound of 1-norm and 5

^th order B-spline in dB

Figure 5.4: Error upper bound of 2-norm and 5

^th order B-spline in dB

indicate that n has little effect on the norm of

F

_m^{n l,}(

e

^jω). This is reasonable since n is

only related to the error between of interpolated waveform ^

x t

ⁿ( ) and x(t). Increasing

m and decreasing q will enhances time-domain resolution and shrinks the value

( )

^{qm l within}

^F

^{mn l, (}

^e

^jω). So it makes sense that larger m and smaller q will make

,( )

n l j

F

m

e

^ω smaller. Higher order derivative l, also reduces

( )

^{qm l and}

^F

^{mn l, (}

^e

^jω).

Therefore, the 1^st order derivative contributes major portion of error residue. If the rms values of

F

_m^{n l,}(

e

^jω) is small, then the norm of

r

_m^{n l k, ,} will be bounded by a

1st order error residue 2nd order error residue n n

5.4 Spectrally Shaped Sample-Time Residue

The 1^st order error residue in eq. (5.32), in frequency domain, is the convolution

of timing jitter and the first order derivative n,(1)

(

a b k

)

band-limited, its first order derivative is also band-limited and located at the same band. If the we can find a sampling period sequence

{ }

τ that makes k

{ }

ε k

high-pass, then the 1^st order error residue in eq. (5.32) will not contaminate the signal

( )

n a b k x ⎛ + ⎞

⎜ ⎟

 that we are interested. The ideal is illustrated in Fig. 5.5 and 5.6.

( e

^jw

) Ε

i

^{,(1) ( ( ))}

( e

^jw

) X

ⁿ

( e

^{jw m a b+}

)

Ε ∗

i

^n,(1)

(

^{jw m a b( ( ))}

)

X e

⁺

Figure 5.5: The frequency domain behavior of modulating band-limited signals

with high-pass timing jitter signal

iⁿ( ^{jw m a b( ( ))}) ( ^j ) i^n,(1)( ^{jw m a b( ( ))})

X e

⁺ + Ε

e

^ω ∗

X e

⁺

Figure 5.6: Magnitude response of output of fractional factor decimator

The 1^st design guideline of fractional factor decimator is to separate 1^st order error residue and desired signal in different bands. The key is to generate high-pass timing jitter

{ }

^{ε .}

timing jitter terms are squared, the whole sequence

{ } ε

k² will become a all positive sequence. This means that

{ } ε

k² is actually low pass and the 2^nd order error residue will contaminate signal band. The only way to suppress 2^nd order error residue is to reduce timing jitter. So the 2^nd design guideline is to reduce the amount of timing jitter.

5.5 Summary

In this chapter, we derive mathematics model for the fractional factor decimator.

As we emphasis repeatedly, the decimator decrease sample rate by “selecting”

incoming signal. In other words, the decimator would like to find an sampling period sequence

{ }

τ . Timing jitter is unavoidable in this scheme. Therefore, we derive k

mathematics model for the timing jitter.

The result in chapter 5.3 shows that the 1^st and 2^nd error residue contributes the majority of the error residue. The 1^st order error residue can be eliminated by generating high-pass timing jitter

{ }

ε which will separate desired signal and timing k

jitter in different band. The 2^nd order error residue is related to total amount of timing jitter. The remedy for 2^nd order error residue is reducing the timing jitter.

In next chapter, the technique to generate sampling period sequence

{ }

τ with k

high-pass timing jitter and technique to reduce timing jitter will be discussed.

Chapter 6

Fractional Factor Decimator

Based on the results in chapter 5, we develop the structure of fractional factor decimator in this chapter. The core element within the decimator is the sigma-delta modulator. The modulator is used to generate sampling period sequence

{ }

τ with k

high-pass timing jitter. The mathematics model of timing jitter error will also be verified here.

6.1 Overview of Fractional Factor Decimator

The block diagram of the proposed fractional factor decimator is depicted in Fig.

6.1. The task of the decimator is to decrease sample rate by factor “a.b”. By putting

‘b’ to input of the sigma-delta modulator, the output sequence’s mean is ‘b’. Adding

‘a’ to the sequence and will get a new sequence whose mean is ‘a.b’. The sequence is the sampling period sequence

{ } τ

k introduced in chapter 5. In chapter 6.2, we will introduce sigma-delta modulator and check whether the sampling period sequence has high-pass timing jitter. In chapter 6.3, the design of selector will be covered. In chapter 6.4, the error caused by timing jitter will be analyzed. Finally, performance of the fractional factor decimator will be stated in chapter 6.5.

Figure 6.1: The block diagram of fractional factor decimator

6.2 Sigma-Delta Modulator

The sigma-delta modulator’s block diagram can be represented in Fig. 6.2. The output signal Y(z) in Fig. 6.2 is

In eq. 6.1, STF stands for Signal Transfer Function and NTF stands for Noise Transfer Function. For the simplest 1^st order sigma-delta modulator, we choose H(z) as ¹ ₁

1 signal is undistorted and error signal E(z) is filtered by NTF(z). Magnitude response of

NTF(z) is drawn in Fig. 6.3 and it is high-pass.

Figure 6.2: The block diagram of sigma-delta modulator

Figure 6.3: Magnitude response of 1

^st order differentiator

A practical modulator may use more complicated H(z), for example, higher orders. The quantizer after the loop filter, H(z), adds quantization noise to make the output signal be of finite levels. The quantizer’s parameters include the number of output levels and level of maximum/minimum output. For example, a two-level sigma-delta modulator’s output may be (-1, 1) or (0, 1). To reduce quantization noise, multiple-levels sigma-delta modulator may be employed.

In typical application, we will not use the simple 1^st order sigma-delta modulator.

A typical plot of STF and NTF is depicted in Fig. 6.4. In base-band, where the input signal is located, the STF is flat while NTF sinks deeply. The quantization noise, usually been modeled white process, is been pushed away from base-band by NTF, which is the desired result in chapter 5.

Figure 6.4: Typical STF and NTF of a band-pass sigma-delta modulator

In Fig. 6.1, input to the sigma-delta modulator is fractional decimation factor ‘b’, which is DC. Therefore, the required STF and NTF character is like that in Fig. 6.4.

Another requirement for NTF is illustrated in Fig. 5.5, where NTF should have a range of bands with low magnitude response. But how wide the range is required; and how small the magnitude response is needed, depends on the specification and shall be decided by the designer.

6.2.1 Delta Sigma Toolbox

In the thesis, we are not focus on the theory of sigma-delta modulator. The

“Delta Sigma Toolbox” [31] can design the modulator with specified parameters. The modulator’s major parameter includes:

z Order

z Optimize (Switch whether to optimize zeros allocation)

z Center frequency fc (for band-pass sigma delta modulator) z Maximum gain of out-of-band noise of NTF Hinf

These parameters will affect number and location of zeros and poles of NTF and STF.

The sigma-delta modulator designed by the toolbox is optimized in the sense of best pole and zero allocation.

6.2.1.1 Order

The order equals to the number of zeros and poles. The sigma-delta modulator is real-input and real-output. Therefore, the zeros and poles are conjugate pairs. As in Fig. 6.5, two zeros form a null. As the order getting higher, the transition band of NTF becomes sharper. We can conclude that as order getting higher, we have better ability to control response of NTF. Though high order brings good performance, it also makes the modulator unstable. We will discuss the stability issue later.

6.2.1.2 Optimize and OSR

The conventional sigma-delta modulator over-samples analog signal and the signal bandwidth in digital domain shrinks. As optimization option enabled, the zeros of NTF will spread evenly in signal band which will provides better in-band noise rejection. For example, when analog signal is low-pass and OSR is 32, the signal band is located at

(

^−π₃₂^,π₃₂

)

. At that region, STF should be flat and NTF should be low.

As a result, changing OSR will affect the location of NTF’s zeros. Fig. 6.6 shows NTF when OSR=4 and 16.

On the other hands, if optimize is not enabled, all zeros are put in z=1 and OSR option becomes no use. For simpler hardware implementation, we may prefer such allocation. This issue will be covered later.

Figure 6.6: The NTF and STF under different OSR

6.2.1.3 Center Frequency

The center frequency fc affects the location of nulls. In our design, the input to the sigma-delta modulator is DC and set fc to zero is reasonable selection. In this thesis, if not mentioned purposely, fc is set to zero.

6.2.1.4 Maximum Out-of-Band Noise Gain: H

_inf

The parameters controls maximum absolute value of NTF(f). When synthesizes the NTF, the toolbox allocates zeros first and then allocates poles to meet specified Hinf. For easier hardware implementation, we may put all poles in z=0.

6.2.2 Timing Jitter Simulation

By using model in chapter 5.3, the sigma-delta modulator is used to generate

{ }

τ and the integrator in Fig. 6.1 is used to generate sampling time Ik k where

With Ik and decimation rate, we can calculate timing jitter defined in eq. (5.5). In chapter 5.4, we have stated that the desired property of timing jitter sequence is high-pass.

Considering the GPS receiver example in chapter 3.3.2, we had shown all possible combination of (a.b, c) in Table 3.1. The sigma-delta modulator parameters are order=4, Optimize=1, OSR=32, fc

=0.0045, H

inf

=1.6, and output level=±1 and its

NTF and STF is depicted in Fig. 6.4. Two input values that make the modulator stable and unstable are selected and corresponding timing jitter are shown in Fig. 6.7.

The left one is stable because its PSD is high-pass and magnitude of its timing

amount of timing jitter. All combinations in Table 3.1 are tested for stability and whether the modulator is stable is listed in Table 6.1. When the modulator is stable, its timing jitter behavior is similar to left part of Fig. 6.7.

b=0.100684 b=0.550342

Figure 6.7: Timing jitter on sigma-delta modulator with output level=±1

Now, use the same sigma-delta modulator except that output levels are (0, 1) and repeat simulations above. Like simulation above, stable modulator’s configurations have similar results like right part of Fig. 6.8.

b=0.100684 b=0.550342

Figure 6.8: Timing jitter on sigma-delta modulator with output level 0 and 1

(a.b) c work?

Table 6.1: Stability of combinations in Table. 3.1 at different sigma-delta modulator

output configurations

6.2.2.1 Stability Issue

Simply speaking, the unstability is caused by unbalanced quantization noise. In Fig. 6.2, considering a modulator with ±1 output levels, when input is 0.7, quantization noise is

There is a feedback loop within the modulator. Although all poles of NTF are stable and any input to the feedback loop will diminish gradually, when quantization noise is unbalanced, it requires longer time to make large input (large quantization noise) “expire” which causes bad timing jitter behavior as left part of Fig. 6.7.

Thus, for a modulator with ±1 output levels, it is stable only when input is near 0 because the magnitude of timing jitter is balancing. The reader could find that in Table 6.1, when ‘b’ is near zero, the configurations with ±1 output levels are stable. On the other hand, when the modulator’s output levels are 0 and 1, ‘b’ near 0.5 is stable. So

designer shall avoid unbalanced quantization noise.

6.2.2.2 Increase Number of Output Levels to Enhance Stability and Reduce Timing Jitter

To investigate how multiple levels output affects the stability of the modulator, a special metric is developed here. The possible input to the modulator is between 0 and 1. In usual applications, extreme inputs such as 0.001 or 0.999 are rare cases. So the stable criterion is that when input is between 0.01 and 0.99, corresponding timing jitter must be high-pass.

To check the stable criterion of the modulator, 10000 values between 0.01 and 0.99 are randomly selected as input to the sigma-delta modulator and we can get 10000 PSD of timing jitter. These PSD are plotted in a diagram such that it is easy to check whether the modulator is stable under different input values.

The parameters of sigma-delta modulator under test are order=4, OSR=32,

f

c

=0.0045, H

inf

=1.6. Its output levels are from dividing (0, 1) evenly. The modulators

with levels of (4, 8, 16, 32, 64, 128) are simulated and results are shown in Fig. 6.9.

For levels of (4, 8 and 16), the sigma-delta modulator is not stable because the PSD of timing jitter is not clean in lower-band.

When the modulator is stable, the PSD of timing jitter is clean in the band (0 to 0.1π). Referring to Fig. 5.5 and 5.6, band (0 to 0.1π) is the place where decimated signal located. As a result, maximum bandwidth of input is roughly 0.05π which means that input signal should be over-sampled 20 times.

In the aspect of the amount of timing jitter, in Fig. 6.9, we are also able to find that total power of timing jitter shrinks as number of level increasing. Note that noise power in the band (0 to 0.1π) will contaminate output signal which can’t be removed.

We can conclude that increasing level of sigma-delta modulator helps to enhance stability and reduce timing jitter.

4 Levels 8 Levels

16 Levels 32 Levels

64 Levels 128 Levels

Figure 6.9: PSD of timing jitter of classical 4

^th order sigma-delta modulator

6.2.3 Hardware Implementation and 2

^nd

Order Sigma-Delta Modulator

Considering the structure in Fig. 6.2, we need to design a loop filter H(z). By eq.

(6.1), when we have NTF(z), the loop filter can be realized by

( ) ( )

( )

1 NTF z

H z NTF z

= − . (6.3)

NTF(z) of sigma-delta modulator in chapter 6.2.2 is

( )( )

( )( )

2 2

2 2

z 2 1 z 1.997 1

z 1.423 0.5157 z 1.643 0.7569

z z

z z

− + − +

− + − + (6.4)

It is obvious that corresponding loop filter is hard to implement. To have simple

NTF(z), it makes sense to let all zeros located in z=1 and all poles located in z=0.

Following parameters could synthesize such type of NTF(z): order=2, Optimize=0,

OSR=32, f

c

=0, H

inf

=9 and synthesized NTF(z) is ( )

²

2

z-1

z . Actually, this is the classical 2^nd order sigma-delta modulator in the textbook and it can be implemented in Fig. 6.10. The structure contains only register and adders, which is very economy.

Figure 6.10: Classical 2

^nd order sigma-delta modulator

Surprisingly, the classical 2^nd order sigma-delta modulator has very nice stability property and wide noise-free band in base-band. Comparing Fig. 6.9 and 6.11, the

4 Levels 8 Levels

16 Levels 32 Levels

64 Levels 128 Levels

Figure 6.11: PSD of timing jitter of classical 2

^nd order sigma-delta modulator

6.2.3.1 Parallel Sigma-Delta Modulator

In chapter 3, we have stated that the fractional factor decimator needs to operate

modulator is not made parallel. If the sigma-delta modulator can be implemented in parallel, then the fractional factor decimator may be able to operate at lower clock rate.

To investigate the possibility, referring to Fig. 6.10, the difference equation of the 2^nd

To investigate the possibility, referring to Fig. 6.10, the difference equation of the 2^nd

在文檔中 軟體無線電之無乘法器取樣率轉換器 (頁 43-0)