Plasma Treatment

According to Moore’s law, the significant scale of the transistors is going to shrinking quickly. Nowadays in order to satisfy two requirements of high operating speed and high integrated density, introducing high-κ materials will be the best choice to replace the gate silicon dioxide layer in the future generations. Although high-κ materials improve many kinds of problems in reducing the thickness of the conventional gate silicon dioxide layer, oppositely it results several thorny questions to be resolved. The questions are as the following: 1) Low-κ interfacial layers are produced. When high-κ materials are deposited, oxygen diffuses the loose thin films. Then the oxygen would react with Si-sub to form low

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quality silicon dioxide and/or metal oxides and limit the EOT scaling down. 2) There are amounts of fixed charges existing in high-κ thin films and resulting in threshold voltage shift to degrade the gate controllability. 3) Carrier mobility degrades. When high-κ thin film is deposited on the Si-sub surface, there are lots of dangling bonds produced from lattice mismatch. For this reason, the electrons moving in the channel are also affected by Coulomb’s scattering, and the driving current degrades. 4) Crystallization temperature is low. The changed phase in high fabrication temperature makes thin films crystallize to increase the probability of leakage current and impurity penetration, e.g. boron penetration. Because of this, many groups suggested to insert a step of surface plasma treatment into the fabrication procedure.

In terms of electrical and optical properties of polycrystalline silicon thin-film transistors (poly-Si TFTs), grain boundaries and intragranular defects exert a profound influence on device characteristics and degrade carrier transport. These defects have been measured by electron spin resonance (ESR) and identified as silicon dangling bonds [76]. In order to obtain device-grade material, it is essential to minimize the dangling-bond density. Commonly, this is achieved by the incorporation of hydrogen which effectively passivates Si dangling bonds and thus improves the electrical properties of the material [77][78]. Afterward several groups proposed an oxygen plasma treatment of poly-Si TFTs which significantly improves the device performance. Furthermore, combinations of H2 and O2 plasma treatments to poly-Si TFTs were found to be more efficient than just a hydrogen or oxygen plasma [79][80][81].

Besides, the NH3-plasma passivation was employed to enhance both the electrical reliability and the thermal stability of the poly-Si TFTs.

A hydrogenation process has been utilized to reduce the poly-Si film trap states to improve device performance. However, the poly-Si TFTs characteristics after hydrogen passivation suffer from serious instability issue due to weak Si-H bonds, causing inferior reliability for product applications. Accordingly, the NH3-plasma passivation after gate oxide

deposition can improve the electrical properties of the poly-Si TFTs because of the passivation effect of hydrogen and nitrogen radicals [82][83][84]. In our study, we will apply the NH3 plasma treatment to our fabrication procedure to compare with the poly-Si TFTs without this process, and the more detail results and discussion with this treatment will be demonstrated in the fourth chapter.

1.6 Polysilicon Thin-Film Transistors with High- κ κ κ κ Gate Dielectrics

As aforementioned in section 1.4, low-temperature polycrystalline silicon thin-film transistors (LTPS-TFTs) have been used for active-matrix liquid crystal displays (AMLCDs) and system on panel (SOP) on glass substrate as pixel switch devices and driving integrated circuits instead of amorphous silicon (α-Si), because the field effect mobility (µ_FE) in poly-Si is significantly higher than that in amorphous silicon. So that complementary metal-oxide-semiconductor (CMOS) devices with suitably high driving currents could be achieved in poly-Si TFTs. However, the highest temperature of TFTs fabrication procedure for the application of SOP is limited to the melting point of the glass substrate. Therefore, it is difficult to develop high-performance LTPS-TFTs with low threshold voltage (VTH), low subthreshold swing (S.S.), low gate leakage current (IG) and high driving current (ID,sat) to drive the liquid crystal of the large area panel, and these electrical properties have to be necessary urgently to the next generation. In order to enhance the driving current of poly-Si TFTs and break through this challenge, a thinner gate oxide must be used to increase the gate capacitance density. However, a higher gate leakage current would be introduced when the thickness of the gate oxide becomes thinner. Besides, low quality silicon dioxide (SiO2) deposited by using a low-temperature manufacture instrument, plasma-enhanced chemical vapor deposition (PECVD), is generally employed as a gate dielectric of the traditional LTPS-TFTs. To compare with low quality SiO₂, high-κ gate dielectrics could possess better

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quality and be more proper to replace the conventional low-temperature SiO₂. Many high-k materials have been used to suppress the gate leakage current and to enhance the transconductance (Gm). Among these dielectric materials, NiTiO3 could be the promising candidate of the future high-κ gate dielectric because of its high permittivity (κ ~ 40). In the following chapters, poly-Si TFTs with a NiTiO3 gate dielectric prepared by sol-gel spin coating method will be introduced particularly.

Figure 1.1 Transistor counts for integrated circuits plotted against their dates of introduction.

Curve shows Moore's law - the doubling of transistor counts every two years.

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Figure 1.2 Trend of gate-oxide-thickness scaling over the past five technology generations from the 0.18-µm to 65-nm nodes.

Figure 1.3 Measurement and simulation of direct tunneling currents under inversion conditions of nMOSFET’s.

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Figure 1.4 Leakage-current values of various high-κ dielectrics at subnanometer EOT. The leakage current was measured at accumulation ( Vfb − 1 V ) in the nMOS devices.

Figure 1.5 XRD spectrum of spin-on CoTiO₃ films. The marked peaks correspond to crystallized CoTiO₃ phases.

(0 1 2 (1 0 4 (1 1 0 ) (1 1 3 (0 2 4 ) (1 1 6 )

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Figure 1.6 SPM images of spin-on CoTiO3 films with various thermal treatments at (a)600^°C, (b)700^°C, (c)800^°C, (d)900^°C. The image size is 1 µm by 1 µm.

Figure 1.7 Transmission electron micrograph of (a) ZnO/ZrO2/SiO2/Si multilayered film heated at 900^°C and (b) ZnO/ZrO2/ITO/glass multilayered film heated at 600^°C.

(a) (b)

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Figure 1.8 Top-gate structure of ZnO-TFT in (a) crosssectional schematic, (b) top view schematic and (c) optical transmission spectra.

(a)

(b)

(c)

Table 1.1 High-κ gate dielectric materials with a dielectric constant reported in the literatures.

Material ε Material ε Material ε

Al2O3 8-11.5 LaAlO3 23.8-27 TaON

AlxSiyOz LaLuO3 32 Ta2O5-TiO2

(Br, Sr)TiO3 200-300 LaScO3 22-30 TiO2(rutile) 86-95 BeAl2O4 8.3-9.43 La2O3-SiO2 5-16 TiO2-SiO2

CeO2 16.6-26 MgAl2O4 8.3-9.4 TiO2/Si3N4

CeHfO2 10-20 Pr2O3 14.9 Y2O3 8-11.6

CoTiO3 45-50 PrAlO3 25 YxSiyOz

DyScO3 22 NdAlO3 22.5 ZrO2 22.2-28

EuAlO₃ 22.5 Sc₂O₃ 13 Zr-Al-O 12-18

GdScO₃ 22 Si₃N₄ 7 Zr silicate 11-12.6

HfO₂ 26-30 SmAlO₃ 19 (Zr, Hf)SnTiO₄ 40-60

Hf silicate 11 SrTiO₃ 150-250 Ta₂O₅-TiO₂

La2O3 18-20.8 Ta2O3 25-45 Y2O3 8-11.6

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Table 1.2 Conduction mechanism in insulator with expression and band diagram.

Mechanism Expression Band Diagram

Schottky

Chapter 2

Experiment Procedures

In this chapter we will illustrate the device fabrication processes of capacitors and polycrystalline-silicon thin-film transistors (poly-Si TFTs) with figures and list the instruments for material and physical properties measurements.

2.1 Device Fabrication

2.1.1 Capacitors

In this thesis, NiTiO3 films were formed by a sol-gel spin coating method in a controlled surroundings, where was kept at temperature of 22^°C and relative humidity of 43%. In the beginning, (100) p-type single crystal silicon wafers with resistivity in the range of 1-10 Ω-cm were prepared as substrates. Firstly, the bare silicon wafers were cleaned by standard RCA steps followed by a dilute-HF dip to remove the native silicon dioxide. Then, the liquid precursor for NiTiO3 was directly spun on Si substrates at about 3000 revolutions per minute, and the spin speed was maintained for 30 seconds. However, the precursor elements of nickel and titanium were nickel acetate tetrahydrate Ni(OOCCH₃)₂‧4H₂O and titanium isopropoxide Ti(OCHC₂H₆)₄, respectively. These two precursors were dissolved in 2-methoxyethanol for the spin coating method. After the precursor was spun on substrates, in order to remove the solvent, the samples were baked step by step at different curing temperatures in atmosphere on a hotplate as shown in figure 2.1. And the procedure (coating-and-baking) was repeated for 5 times due to for poly-Si TFTs fabrication. Then, the spin-on NiTiO3 films were oxidized at 400^°C in N2/O2 ambient with 50-sccm airflow for 10 min. In order to investigate the characteristics of the high-κ NiTiO₃ material as gate dielectric after high temperature

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treatment, rapid thermal annealing (RTA) was performed. The samples were annealed at temperatures of 500^°C, 600^°C, 700^°C, 800^°C, and 900^°C for 30 seconds in N₂ ambient.

Photolithography was used to define gate areas and then TaN metal was deposited on the top of the samples by reactive DC-sputtering. Lift-off was performed to fabricate the MIS capacitors. Finally, ohmic contacts were formed by thermal evaporation of 300-nm-thick aluminum (Al) electrode on the backside of the samples. The process flow of a capacitor was shown in figure 2.2.

2.1.2 Polycrystalline-Silicon Thin-Film Transistors

In this section, we will make a description on the process flow of thin-film transistors with sol-gel spin coating NiTiO₃ films and the main fabrication steps were summarized as shown in figure 2.3. In the beginning, all wafers proceeded from using the traditional RCA cleaning to remove any contaminations, native oxide, and atomic scale roughness.

Subsequently, a 500-nm thermal oxide grown on 6-inch silicon wafers by using a horizontal furnace was used to simulate the glass substrate of the active matrix liquid crystal display (AMLCD). And then, an undoped amorphous silicon (α-Si) film with a 50-nm thickness was deposited on the 500-nm thermal oxide by using a low-pressure chemical vapor deposition (LPCVD) system in silane (SiH4) ambient with a pressure of 350 mtorr at 560 °C as shown in figure 2.3(a). After a 24-hour annealing at 600^°C by using the conventional solid-phase crystallization (SPC) method due to its low-production cost and good grain-size uniformity, amorphous silicon became to poly-crystalline silicon (poly-Si). Active area region was patterned by photolithography and then source/drain region were formed by using BF2 ion implantation as shown in figure 2.3(b). The following steps were to spin NiTiO3 material as a gate dielectric on poly-Si films by using the sol-gel spin coating method for 5 times as the aforementioned step. Then, the spin-on NiTiO₃ films were oxidized at 400^°C in N₂/O₂ ambient by using a horizontal furnace with 50-sccm airflow for 10 min, and afterward the

samples were just annealed at 500^°C, 600^°C, and 700^°C for 30 seconds in N₂ ambient. A 200-nm-thickness TaN metal was deposited on the top of the samples by reactive DC-sputtering at 600 mtorr with a DC power of 1500 watt and patterned as the gate electrode by photolithography as shown in figure 2.3(c). A 400-nm tetraethoxylsilane (TEOS) oxide film used as an inter-layer dielectric (ILD) layer was deposited by using a plasma-enhanced chemical vapor deposition (PECVD) system at 300^°C. Then contact holes were opened and etched by by using a buffered oxide etching (BOE) solution as shown in figure 2.3(d).

Aluminum (Al) electrode with 600-nm thickness was deposited by e-gun evaporator, and then the aluminum pads were lithographically patterned. Subsequently, metal pads were etched by using a TCP metal etcher, and thus the poly-Si TFTs with a high-κ NiTiO3 gate dielectric prepared by sol-gel spin coating method were accomplished as shown in figure 2.3(e).

Eventually, an NH3 plasma treatment was performed at 350^°C for 30 min for partial samples, which were the poly-Si NiTiO₃ TFTs with a 500^°C-RTA treatment after the Al gate electrode formation in order to compare to the samples without NH₃ plasma treatment.

2.2 Material and Physical Properties Measurements

The microstructure of spin-on NiTiO3 films and silicon substrate were investigated by JEOL JEM-2010F field emission transmission electron microscope (TEM) equipped with Link ISIS-300 energy dispersive X-ray analyzer (EDS). And the TEM EDS with a 0.23-nm electron beam size was used to perform chemical analysis qualitatively.

The property of crystallization of spin-on NiTiO3 film with different annealing temperatures was identified by PANalytical X’Pert Pro X-ray diffraction system under normal atmosphere. Optical module with X-ray mirrors and a parallel plate collimator was used to perform gracing incident X-ray diffraction (angle of incidence θi ~ 1^°). The beam source originated from Cu Kα radiation with a 0.154-nm wavelength and this beam source was

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Surface morphology of spin-on NiTiO₃ film with different annealing temperatures was obtained by Veeco multimode scanning probe microscope (MMAFM) at normal atmosphere.

The highest resolution in X-Y plane and Z direction were about 1.5 nm and few angstroms, respectively. And the tip curvature radius was about 2 nm.

A ULVAC-PHI Quantera high resolution X-ray photoelectron spectrometer (HR-XPS) with 180^° spherical capacitor analyzer was used to analyze quantitatively the chemical composition of the dielectrics NiTiO3 prepared by sol-gel coating method.

The capacitance-voltage (C-V) curves and current-voltage (I-V) curves of capacitors were measured in the same probe station by using HP 4284 and Keithly 4200, respectively.

2.3 Equation Derivation and Electrical Parameters Extraction

In this section, we firstly formulate a general drain current for thin-film transistor by using gradual channel approximation (GCA) model, which the variation of the electrical field along the channel is much less than the corresponding variation perpendicular to channel.

Hence, the inversion charges density (Q_inv) could be simplified to the 1-D form of Possion’s equation. The current-voltage characteristic of the thin-film transistor could be calculated by estimating the elemental resistance dR and the elemental segment dy of the conducting channel given by

, where W is the channel width and µ_EF is the field-effect mobility. Then, integrate Eq. (2-1) from source (V=0 at y=0) to drain (V=VDS at y=L). The drain current could be expressed as

0 0

Following, we use the charge-sheet approximation model, which assumes that the inversion charges (Q_inv) are located at the silicon surface as a sheet of charges with no potential dropping or band bending across the inversion layer, to derive drain current as

(

²

)

²

⁽

²

⁾

capacitance density of insulator layer, ε_Si is the dielectric constant of silicon, and N_B is the effective channel dpoant in active channel of the thin-film transistor. Substituting Eq. (2-3) into Eq. (2-2) and carrying out the integration, the drain current (I_DS) could be presented by

( )

²

Substituting Eq. (2-6) into Eq. (2-4), the saturation current I_{DS sat,} could be written as

( )

²

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Secondly, we will introduce the extractions of the device electrical parameters. An automatic measurement system, ICS software, combined a personal computer (PC), Agilent-4156 semiconductor parameter analyzer, Agilent-4285 precision LCR meter, Agilent E5250A low leakage switch mainframe, and a probe station is used to measure the drain-source current versus gate-source voltage (IDS-VGS) curves and the drain-source current versus drain-source voltage (IDS-VDS) curves of the fabricated thin-film transistors. The electrical parameters of thin-film transistors, for examples on the threshold voltage (VTH), the subthreshold swing (S.S.) and the field-effect mobility (µFE), are also extracted to estimate the benefits of integrating high-κ NiTiO3 gate dielectric or nitrogen incorporation.

According to the thin-film transistor theory described in Eq. (2-8), in the linear regime,

< − ,

Thus, the transconductance (Gm) in the linear regime is given by

∂ ,

Therefore, the field-effect mobility in the linear regime (µFE,lin) could be obtained as

, ~0.1

, where the drain-source voltage (VDS) is usually set at 0.1 V. Because the inversion carriers in the active channel layer could be easily drained out with enough high carrier mobility at low drain bias, we calculate the field-effect mobility in the linear regime (µFE,lin) for low-temperature polycrystalline silicon (LTPS) TFT device. The transfer curve of LTPS TFT device, drain current (IDS,lin) versus gate-source voltage (VGS), is measured at VDS = 0.1 V, and then µFE,lin could be obtained by using Eq. (2-12).

For extraction convenience, the threshold voltage (VTH) is defined as the gate voltage required a normalized drain current of IDS,N = (W/L) × 100 nA at VDS = 0.1 V. The ON/OFF

current ratio (I_{ON, max}/I_{OFF, min}) and the subthreshold swing (S.S.) present the switching and the gate-controlled capabilities of TFT device, respectively. In this work, the ON/OFF current ratio of LTPS TFT device is defined as that ratio of the maximum on-state current to the minimum off-state current at VDS = 1 V. The subthreshold swing is measured at the inverse of the maximum slope in the plot of drain current (in denary logarithm) versus gate-source voltage (VGS).

By integrating the depletion charges (Qdep) in active channel with the charge-sheet approximation , the subthreshold current (IDS,SUB) in the subthreshold region (at a small VDS ~ 0.1 V) could be derived as the following equation:

2 2

and C_dep is the depletion capacitance density. Substituting Eq. (2-16) into Eq. (2-13) yields the subthreshold current as a function of VGS

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Consequently, the subthreshold swing (S.S.) could be presented following equation:

1

(2-18), the subthreshold swing (S.S.) neglected the depletion charges (Qdep = q × Cdep) could be rewritten as

Therefore, the maximum interface states density (NSS,max) presents the interface quality between the dielectric and the active channel layer of TFT device could be calculated from the S.S. without the depletion capacitance as

,max

In pentacene-based organic TFT device case, because its inversion carriers in the active channel could not be easily drained out the device with a low carrier mobility at a low drain bias, its parameters are usually extracted in the saturation regime (V_DS >V_GS−V_TH) as

( )

, , 2

2 1

=

FE sat DS sat −

ins GS TH

I L

C W V V

µ . (2-23)

Strictly speaking, the Eq. (2-23) is valid only when the mobility is constant. In fact, µFE,sat is dependent on the gate-source bias (V_GS). The Eq. (2-23) is only used for estimating an approximated value for the field-effect mobility calculation of organic TFT devices.

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3000 r.p.m.

Spin Coating

90°°°°C 1.5min 120°°°°C 3min

200°°°°C 5min Wafer

Holder

Sol-Gel NiTiO₃

5 cycles

Hot Plate

Figure 2.1 The process flow of the sol-gel spin coating method to form a high-κ NiTiO₃ film.

P.R. P.R.

Si-sub

NiTiO₃

TaN/Al

TaN/Al

Al

NiTiO₃

RAC clean and DHF

NiTiO₃formed by spin coating

Si-sub

Si-sub

Si-sub

90°°°°C, 120°°°°C, 200°°°°C baking

400°°°°C annealing in N₂/O₂furnace RTA (500°°°°C ~ 900°°°°C) in N₂

Define patterns with photoresist TaN/Al deposition

Lift-off and gate electrode formation Back contact of Al deposition

Repeat 5 times

Figure 2.2 The main process flow of sol-gel spin coating method to form a NiTiO3

capacitor.

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500-nm Thermal Oxide Si Substrate 50-nm ααα-Si Filmα

(a) Thermal oxidation, α-Si film deposition.

500-nm Thermal Oxide Si Substrate Poly-Si Film BF₂ion implantation

P.R. P.R. P.R.

(b) SPC annealing, active region patterning, source and drain ion implantation.

P⁺ P⁺

200-nm TaN Gate

500-nm Thermal Oxide Si Substrate Poly-Si Film 5-Coated NiTiO₃Layer

(c) Source and drain activation, 5-coated NiTiO3 layer formed, and TaN metal deposition and patterning as a gate electrode.

P⁺

(d) ILD layer deposition and contact holes opening.

P⁺

(e) Al metal deposition and patterning as metal pads.

Figure 2.3 The main process flow of the thin-film transistor with sol-gel spin coating NiTiO3 films.

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Chapter 3

Material and Physical Characteristics of Capacitors

In this chapter, we will firstly report the material characteristics of spin-on NiTiO₃ thin films analyzed by High-Resolution Transmission Electron Microscope (HR-TEM), Grazing Incident X-Ray Diffraction (GI-XRD), Scanning Probe Microscope (SPM), Auger Electron Microscope (AEM), and Electron Spectroscopy for Chemical Analysis (ESCA). Afterward we will report the physical characteristics of that such as dielectric permittivity, C-V and I-V properties.

3.1 Surface Morphology

As mentioned in section 1.2.4, it is common that the surface morphology of high-κ dielectric is still flat even if it undergoes high temperature treatment. PANalytical X’Pert Pro X-ray diffraction system and Veeco Dimension 5000 Scanning Probe Microscope (D5000) are used to analysis surface morphology of films after different high temperature annealing.

Figure 3.1 gives the GI-XRD spectrum of the NiTiO3 thin films with different temperature treatments. There are no marked signals to be detected for samples which are treated at temperatures below 700^°C, and this phenomenon displays that spin-on NiTiO3 films are amorphous phases initially. Consequently, the samples are annealed at temperatures above 700^°C, and signals of crystallized NiTiO3 phases are exhibited. This suggests the crystallization temperature of spin-on NiTiO3 films begin between 600 ~ 700^°C.

Figure 3.2 to figure 3.8 present the SPM images of NiTiO3 films with different high temperature treatments. From figure 3.2 to figure 3.8 are the flatten and 3-D images of samples which are baked or annealed at 200^°C, 400^°C, 500^°C, 600^°C, 700^°C, 800^°C, and

Figure 3.2 to figure 3.8 present the SPM images of NiTiO3 films with different high temperature treatments. From figure 3.2 to figure 3.8 are the flatten and 3-D images of samples which are baked or annealed at 200^°C, 400^°C, 500^°C, 600^°C, 700^°C, 800^°C, and

在文檔中 利用凝膠轉塗佈法製備高介電常數鈦酸鎳閘極介電質層於複晶矽薄膜電晶體之研究 (頁 24-0)