利用凝膠轉塗佈法製備高介電常數鈦酸鎳閘極介電質層於複晶矽薄膜電晶體之研究

(1)

國

立

交

通

大

學

電子物理學系

碩

士

論

文

利用凝膠轉塗佈法製備高介電常數鈦酸鎳閘極

介電質層於複晶矽薄膜電晶體之研究

Study on Polysilicon Thin-Film Transistors with High-

κ

NiTiO

₃

Prepared by Sol-Gel Spin Coating Method

研究生：顏榮家

指導教授：趙天生博士

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利用凝膠轉塗佈法製備高介電常數鈦酸鎳閘極介電質層

於複晶矽薄膜電晶體之研究

學生

學生：

：顏

：

顏

榮

家

指導教授

指導教授：

指導教授

：趙

：

趙

天

生

博士

國

立

交

通

大

學

電

子

物

理

學

系

摘

要

在此論文裡，利用新穎低溫技術凝膠旋塗佈法製備具高介電常數的鈦酸鎳介電質層，並對五百到九百度不同溫度熱退火後的樣品做材料與物理特性分析，接著將所得之電性結果應用在複晶矽薄膜電晶體上做進一步之研究。從X 光繞射光譜分析圖可得知此塗佈上去的鈦酸鎳介電質層的結晶溫度大約介於六百與七百度之間。掃描式探針顯微鏡所顯示在經過不同溫度熱退火之後的鈦酸鎳介電質層的表面形貌，藉此可發現當溫度高於六百度後，樣品的表面粗操度會隨著溫度上升而產生劇烈的劣化現象。由化學分析電子能譜儀的結果顯示，所有的樣品都含有鎳-氧與鈦-氧兩種金屬氧化鍵，另外又發現在低溫兩百度烘烤會有氫氧化物的存在。而更進一步的化學分析電子能譜儀分析確定了此塗佈上去並經過六百度熱退火的介電質層的原子濃度比例，[Ni]：[Ti]：[O]約為 1：1：3。利用高解析度穿透式電子顯微鏡所拍之影像與對應的電容電壓曲線圖，求得介電質鈦酸鎳的介電常數的範圍值約介於36~42 之間。此外，由電容電壓曲線圖可看出鈦酸鎳介電質具有較薄的電容等效厚度與較高的閘極電容密度。接下來將凝膠旋塗佈法應用於固相再結晶複晶矽薄膜電晶體上，且鈦酸鎳介電質層經過五百、六百與七百度三種溫度的快速熱退火處理。從種種電性量測結果得知，經過五百

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Department of Electrophysics in NCTU II 度熱處理的樣品明顯電性優於其它六百與七百度熱處理的樣品。之後，取五百度熱處理樣品另外做氨電漿處理發現，經過氨電漿鈍化處理的電晶體在元件性能以及臨界電壓下降特性上都有顯著的改善。此論文所提出製程薄膜電晶體的技術即便沒有添加其它電漿處理或是先進窄製程窗相結晶技術，都能擁有不錯的電性結果。

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Study on Polysilicon Thin-Film Transistors with High-

κ

κ NiTiO

κ

3

Prepared by Sol-Gel Spin Coating Method

Student：

：

：Rong-Chia Yen Advisor：

：

：Dr. Tein-Sheng Chao

Department of Electrophysics

National Chiao Tung University

ABSTRACT

In this thesis, the high-κ NiTiO3 dielectrics are prepared at different annealing temperatures from 500°C to 900°C by a sol-gel spin coating method, which is a novel low-temperature technique to form thin films. The X-ray diffraction (XRD) spectrum describing the crystallization temperature of the spin-on dielectric is between 600°C and 700°C. The scanning probe microscope (SPM) images display that the surface roughness abruptly increases with the annealing temperature higher than 600°C. The electron spectroscopy for chemical analysis (ESCA) exhibits the metal-oxide bonds of Ni-O and Ti-O in all samples and the hydroxides in 200°C-baking sample. Besides, the ESCA also proves that the atomic concentration ratio of the spin-on dielectric with 600°C-RTA treatment is [Ni]:[Ti]:[O]~1:1:3. The high dielectric constant (High-κ) of the NiTiO3 material calculated to be in a range of 36 ~ 42 is extracted from the high-resolution transmission electron microscopy (HR-TEM) image and the corresponding C-V

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Department of Electrophysics in NCTU

IV

curves. The C-V curves shows that the NiTiO3 gate dielectric can achieve a thin capacitance equivalent thickness (CET) and high gate capacitance density.

The solid-phase crystallized (SPC) poly-Si TFTs with a NiTiO3 gate dielectric prepared by the sol-gel spin coating method with 500°C, 600°C and 700°C-RTA treatments have been demonstrated. The electrical characteristics of the poly-Si TFTs with NiTiO3 gate dielectric (poly-Si NiTiO3 TFTs) at 500°C annealing temperature are better than that at 600°C and 700°C-RTA treatments. The device performance and threshold-voltage rolloff properties of the poly-Si NiTiO3 TFTs with 500°C-RTA treatment can be significantly improved with a NH3 plasma passivation. The proposed poly-Si NiTiO3 TFTs crystallized by the SPC technique could possess good electrical properties even without additional plasma treatments or other advanced phase crystallization techniques with narrow process window.

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誌

誌謝

謝

本論文能順利完成，要感謝的人實在太多，那就先感謝天吧！沒有眾人的支持與陪伴，就無法成就這一切！因此，首要感謝的人就是我的指導教授趙天生博士。老師總會在我做實驗之前一再地提醒該注意的細節，在實驗完成後仔細地與我討論量測結果並且給予意見。更令人感動的是，老師在我遇到人生中嚴重的低潮時，同時扮演著心靈導師的重要角色，發揮他那佛心來的慈悲，適時地給了我無限的勇氣去面對未來。在此真心地感謝老師對我的包容與耐心，令我獲益良多，讓我更成長與茁壯。感謝已畢業的楊宗諭(砲哥)學長，在早期我孤立無援時，還願意帶我進入實驗室教導機台的操作步驟與技巧，並且熱心地為我解答製程上的任何問題。感謝高國興(高興)學長，在中期我遇到瓶頸時，願意撥空領導我執行此篇論文主要的材料分析部份。感謝吳仕傑(小 P ) 學長，在後期我虛擲光陰時，突然空降來帶我進行電晶體部分的實驗製作，不時地叮嚀我量測進度，跟我ㄧ起討論與分析實驗的量測結果，是我能完成碩士論文的最大功臣！感謝黃俊嘉(黃博)學長，在我剛來到電子工程所研究室時熱心地對待，讓我能夠很快地融入這個新環境。感謝鄧至剛學長(天王)，除了在製程上無私的幫助之外，也提供撰寫論文的寶貴意見。感謝郭柏儀學長，常常將大家帶出研究室到戶外打棒球和郊外旅遊，是所有人最好的教練與導遊。感謝高中兼碩士班同學王冠迪，在我孤獨無助時一直給我精神上的鼓勵和行動上的協助，讓我保有繼續學業的一絲動力。感謝工四館薄膜與量測實驗室的其他夥伴們，文呈學長(羅大)、家文學長(老張)、桑學長、冠良、子恆、治宏(莎莎)、志偉、緯宸、振昌(昌哥)，實驗室因為有你們而充滿歡樂，並一起度過漫長的研究時光，豐富了我最後的碩士生涯。感謝國家奈米元件實驗室的機台工程師們，彭馨誼小姐、鍾昌貴先生、陳琇芝小姐、李春杏小姐、林婉貞小姐，以及曾經幫助過我的昌學，因為有你們的大力幫忙，讓我在實驗上事半功倍，在此獻上我最深的敬意。此外，還要感謝我的大學室友孫董鴻志，即使每個週末都有飯局，但還是願意挪出時間陪我上館子吃美食聊是非，甚至帶我遊遍台北，看煙火跨年和逛元宵燈會，讓我的課餘生活依然多采多姿！感謝欣怡學妹讓我懂得如何成為一個更成熟的男人。感謝黑妞怡諍時常關心我的生活作息，與我分享心情和舒解壓力。感謝昀平姐在工讀時對我像弟弟般的照顧，讓外出求學的我感受到異地的溫暖。在此感謝你們點綴了我的碩士生涯。最後，想要感謝的是我敬愛的雙親，父親顏啟發先生與母親黃春季女士，因為有你們無怨無悔的犧牲奉獻，才能成就今日完成碩士學位的我。感謝姐姐慈玲對家庭完全的付出，感謝弟弟榮原對我的體諒與忍讓。謹以此論文獻給所有關心我的親人與朋友。顏榮家 2009 于新竹‧‧‧‧交大

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Department of Electrophysics in NCTU VI

Chapter 1 Introduction

....

1

1.1 High-κ Gate Dielectrics Development...1

1.2 Requirements for High-κ Materials as a Gate Dielectric...4

1.2.1 Dielectric Constant and Barrier Height...4

1.2.2 Thermal Stability...4

1.2.3 Interface Quality...5

1.2.4 Film Morphology...6

1.2.5 Process Compatibility...6

1.3 Sol-Gel Spin Coating Method...7

1.4 Summary of Thin-Film Transistors...8

1.4.1 Solid-Phase Crystallization (SPC)...9

1.4.2 Metal-Induced Lateral Crystallization (MILC)...10

1.4.3 Excimer Laser Annealing (ELA)...11

1.5 Plasma Treatment...11

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Chapter 2 Experiment Procedures

...

25

2.1 Device Fabrication...25

2.1.1 Capacitors...25

2.1.2 Polycrystalline-Silicon Thin-Film Transistors...26

2.2 Material and Physical Properties Measurements...27

2.3 Equation Derivation and Electrical Parameters Extraction...28

Chapter 3 Material and Physical Characteristics of Capacitors

...

38

3.1 Surface Morphology ...38

3.2 Auger Electron Microscope...39

3.3 Electron Spectroscopy for Chemical Analysis

.

...39

3.4 Dielectric Permittivity...40

3.5 Device Performance...41

Chapter 4 Electrical Characteristics of Thin-Film Transistors

...

64

4.1 Device Performance for Different Thermal Treatments

.

...64

4.2 Threshold-Voltage Rolloff for Different Thermal Treatments...66

4.3 Device Performance with NH3 Plasma Treatment...66

4.4 Threshold-Voltage Rolloff with NH3 Plasma Treatment...68

Chapter 5 Conclusions and Further Works...78

5.1 Conclusions...78

5.2 Further Works...79

References...81

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VIII

Figure Captions

Chapter 1

Figure 1.1 Transistor counts for integrated circuits plotted against their dates of introduction. Curve shows Moore's law - the doubling of transistor counts every two years...15 Figure 1.2 Trend of gate-oxide-thickness scaling over the past five technology generations from the 0.18-µm to 65-nm nodes...16 Figure 1.3 Measurement and simulation of direct tunneling currents under inversion conditions of nMOSFET’s...17 Figure 1.4 Leakage-current values of various high-κ dielectrics at subnanometer EOT. The leakage current was measured at accumulation (Vfb − 1 V) in the nMOS

devices...18 Figure 1.5 XRD spectrum of spin-on CoTiO3 films. The marked peaks correspond to

crystallized CoTiO3 phases...19

Figure 1.6 SPM images of spin-on CoTiO3 films with various thermal treatments at

(a)600°_{C, (b)700}°_{C, (c)800}°_{C, (d)900}°_{C. The image size is 1 µm by 1}

µm...20 Figure 1.7 Transmission electron micrograph of (a) ZnO/ZrO2/SiO2/Si multilayered film

heated at 900°C and (b) ZnO/ZrO2/ITO/glass multilayered film heated at

600°C...21 Figure 1.8 Top-gate structure of ZnO-TFT in (a) crosssectional schematic, (b) top view schematic and (c) optical transmission spectra...22

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Chapter 2

Figure 2.1 The process flow of the sol-gel spin coating method to form a high-κ NiTiO3

film...34

Figure 2.2 The main process flow of sol-gel spin coating method to form a NiTiO3

capacitor...35 Figure 2.3 The main process flow of the thin-film transistor with sol-gel spin coating NiTiO3 films...37

Chapter 3

Figure 3.1 XRD spectrum of spin-on NiTiO3 with different temperature treatments. The

significant peaks correspond to crystallized NiTiO3 phases...43

Figure 3.2 SPM images of spin-on NiTiO3 films with different thermal treatments at 200°C.

The image size is 1µm by 1µm...44 Figure 3.3 SPM images of spin-on NiTiO3 films with different thermal treatments at 400°C.

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X

The image size is 1µm by 1µm...50 Figure 3.9 Surface roughness of spin-on NiTiO3 dielectric as a function of annealing

temperature...51 Figure 3.10 Auger depth profile of spin-on NiTiO3 dielectric annealed at

600°C...52 Figure 3.11 ESCA spectrum of nickel element with different annealing

temperatures...53 Figure 3.12 ESCA spectrum of titanium element with different annealing

temperatures...54 Figure 3.13 ESCA spectrum of oxygen element with different annealing

temperatures...55 Figure 3.14 ESCA spectra of (a) Ni 2p, (b) Ti 2p and (c) O 1s for the spin-on NiTiO3

dielectric annealed at 600°_C...56

Figure 3.15 TEM micrograph of 1-layer NiTiO3 film spin-coated on a high-quality thermal

SiO2 layer and annealed at 600°C...57

Figure 3.16 C-V curves of capacitors with Si/SiO2/NiTiO3/TaN and Si/SiO2/TaN stack

structures...58 Figure 3.17 C-V curves of the NiTiO3 gate dielectric after forward and reverse switching for

hysteresis loop shift...59 Figure 3.18 C-V curves of spin-on NiTiO3 films with different thermal

treatments...60 Figure 3.19 I-V curves of spin-on NiTiO3 films with different thermal

treatments...61 Figure 3.20 Capacitance equivalent oxide thickness (CET) and current density of spin-on

NiTiO3 gate dielectrics as functions of annealing

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Chapter 4

Figure 4.1 The typical transfer characteristics of the poly-Si NiTiO3 TFTs prepared by

sol-gel spin coating method annealed at different treatment temperatures...70 Figure 4.2 The typical output characteristics of the poly-Si NiTiO3 TFTs prepared by

sol-gel spin coating method annealed at different treatment temperatures...71 Figure 4.3 The threshold-voltage rolloff properties of the poly-Si NiTiO3 TFTs and the

poly-Si TEOS TFTs...72 Figure 4.4 The typical transfer characteristics of poly-Si NiTiO3 TFT at 500°C thermal

annealing compared to NH3-implanted plasma

treatment...74 Figure 4.5 The typical output characteristics of poly-Si NiTiO3 TFT at 500°C thermal

annealing compared to NH3-implanted plasma

treatment...75 Figure 4.6 The threshold-voltage rolloff properties of poly-Si NiTiO3 TFT at 500°C

thermal annealing compared to NH3-implanted plasma

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XII

Table Lists

Chapter 1

Table 1.1 High-κ gate dielectric materials with a dielectric constant reported in the literatures...23 Table 1.2 Conduction mechanism in insulator with expression and band

diagram...24

Chapter 3

Table 3.1 The sum of capacitance equivalent thickness, leakage current density, and roughness value for NiTiO3 films after different temperature treatments...63

Chapter 4

Table 4.1 The sum of electrical characteristics for poly-Si NiTiO3 TFTs with 500, 600 and 700°_{C-RTA temperature treatments...73}

Table 4.2 The sum of electrical characteristics for poly-Si NiTiO3 TFT at 500°C thermal annealing compared to NH3-implanted plasma treatment...77

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Chapter 1 Introduction

Firstly in this chapter, we will explain why the traditional silicon dioxide should be replaced by high-κ gate dielectrics. Then, the fundamental properties of high-κ materials and the requirements for analyzing high-κ gate dielectrics will be introduced. Afterward we will introduce the sol-gel spin coating method used in this thesis and summary of thin-film transistors. Finally, we will introduce the advantages of the plasma treatment for polycrystalline-silicon thin-film transistors (poly-Si TFTs) with high-κ gate dielectrics.

1.1 High-κ Gate Dielectrics Development

In order to enhance the operating speed of the complementary metal-oxide-semiconductor (CMOS) integrated circuit (IC), the high dielectric constant (High-κ) gate dielectrics have been massively investigated to replace conventional silicon dioxide (SiO2) as the gate dielectric in metal-oxide-semiconductor field-effect transistor

(MOSFET) in the past decades [1-13]. Better performance and reduced cost make the scaling of MOSFETs to consist with the famous Moore’s law [14], which predicts the trend of the quantity of transistors integrated in a chip as shown in figure 1.1[15]. Channel length scaling enhances the operating speed of devices to ensure the excellent controll ability of gates, but short channel effects [16][17] are getting more obvious. Therefore, the thickness of the gate dielectric must become thinner to suppress short channel effects.

A SiO2 was used as a gate dielectric when the invention of MOS technology was applied

till 0.18 µm due to its good integrity and excellent SiO2/Si interface properties since 1960.

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2

dielectric was 3 nm or thicker. But in 1994, the researchers in Toshiba incorporation showed that the devices of well behavior with a 1.5-nm-thick gate oxide were practical as short channel length [18]. However, the significant increase in gate leakage is still suppressed from gate oxide for further work.

As the thickness of SiO2 film is smaller than 2 nm, the gate leakage increases markedly.

Accordingly, the silicon oxynitride (SiOxNy) material replaces SiO2 material effectively as the

major gate dielectric option after 0.18-µm node, and the quantity of incorporated nitrogen increases with decreasing thickness. But SiOxNy reached its thickness limitation about 1.2 nm

until 2003 as shown in figure 1.2 [19]. There is no obvious fabrication progress to apply to gate dielectric scaling. Consequently, high-κ dielectrics may begin to be used for both low operating power (LOP) and low standby power (LSTP) of 45-nm node in 2008.

From Eq. (1-1) [20][21], we can know that the advantages of thinning gate dielectric are not only to suppress short channel effect and maintain threshold voltage, but also enhance the driving current of the transistors. It’s a pity that there are some problems when gate dielectric becomes thinner.

2 ox

,sat eff ,sat

eq

=

(

)(

)

2

D G T D G T

W

I

V

L

t

ε

µ

−

，

≥

−

(1-1)

For example, the thickness of the gate dielectric to 70-nm-node technology is about 10 Å as a few layers of SiO2 molecules. While the extremely thin gate oxide layer is scaled less

than 20 Å, significant leakage current increases because of stress-induced leakage current (SILC) or gate-induced drain leakage (GIDL), and boron penetration occurs for pMOSFETs as shown in figure 1.3 [22]. In addition, the mechanism of gate-leakage current has been led from F-N tunneling changing to direct tunneling. Eq. (1-2) [20] is the relationship between the leakage current of direct tunneling and the thin film thickness of the gate dielectric.

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dielectric dielectric 2

2 *

exp

2

DT B

V

m q

I

t



_

_



∝



_

−



Φ −





_







h



(1-2)

Hence, the leakage current would increase as the thickness of the gate oxide layer becomes thinner, and result in the large consumption of device’s power. Besides, the uncontrollable uniformity of the thickness in fabrication causes the variations of the electric properties. This problem is disallowed in advanced integrated circuit manufacture. Moreover, there are reliability issues such as hot carrier effects, process-induced oxide damage, time-dependent dielectric breakdown (TDDB), electrostatic discharge (ESD) damage and negative-bias-temperature instability (NBTI) for pMOSFETs.

In order to solve these issues, many high-κ materials used to replace gate dielectric of SiO2 were proposed continually such as silicon nitride (Si3N4), silicon oxynitride (SiOxNy),

aluminum oxide (Al2O3) and hafnium dioxide (HfO2), and some high-κ dielectrics reported in

the literatures are listed in table 1.1 [19]. High-κ gate dielectric possesses thicker physical film and thinner equivalent oxide thickness (EOT) so that the problems of the uniformity of an extremely thin gate silicon dioxide layer were unraveled and the leakage current of direct tunneling was suppressed as shown in figure 1.4 [19].

From Eq. (1-3) [20], we can find that after a SiO2 layer is replaced by a high-κ material

(ignoring quantum mechanical and depletion effects from a Si substrate and gate), gate capacitance not only maintains quite high value but also enhances greatly the device’s driving current. high-κ ox ox eq high-κ

C

t

ε

=

(1-3)

Nickel-titanium oxide (NiTiO3) [23] material owns quite high dielectric coefficient,

which is estimated around 40, and appears to be a very promising high-κ gate dielectric for future ultra-large scale integrated devices.

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4

1.2 Requirements for High-κ Materials as a Gate Dielectric

In order to replace gate SiO2 dielectric effectively, the alternative high-κ materials have

to possess some required properties for the next generation. In this section, we are about to discuss the necessary conditions for this issue.

1.2.1 Dielectric Constant and Barrier Height

As previous discussion, high dielectric constant (High-κ) insulator could reduce the gate-leakage current because of its thick enough physical thickness. The range of dielectric constant is better between 20 and 80 due to fringing-induced barrier lowering (FIBL), and the EOT thinner than 1.0 nm is the best. This effect brings about the disadvantages of operating voltage lowering, slow device’s driving speed and over high power consumption. [24]

For normal high-κ gate dielectric layers, the leakage mechanism is dominated by intrinsic properties and affected by extrinsic properties. The intrinsic properties of the insulator include the energy band gap (Eg), the dielectric constant (κ) and the conduction

offset (∆Ec). The extrinsic properties contain physical thickness, film morphology, the

deposition methods, the environmental temperature and the applied electrical field on the insulator. Several mechanisms of basic electronic conduction in insulators are listed in table 1.2 [16]. Consequently, the direct tunneling current is markedly suppressed by increasing physical thickness and the conduction band offset.

1.2.2 Thermal Stability

In the early period, the high-κ metal oxide systems have unstable interfaces with silicon substrate (Si-sub) because the insulators would react with Si to form an unsuitable interfacial layers which will cause the reduced effective oxide thickness and degrade the carrier mobility [20]. Therefore, it is important to realize the thermodynamics of these systems and thereby try to prevent the formations of the interfaces with Si-sub.

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Because Si-sub wafers will endure some high temperature processes after depositing high-κ dielectrics on Si-sub, the possible interfacial reactions between high-κ dielectric and Si-sub are given as the following:

Si + MOx → M + SiO2 (1-4)

Si + MOx → MSix + SiO2 (1-5)

Si + MOx → MSix + MSiOx (1-6)

Si + stable MOx + O2 → stable MOx + SiO2 (1-7)

(M: metal, MOx: high-κ metal oxide, MSix: metal silicide, MSiOx: metal silicate)

Although the interfacial metal-silicon products are usually detrimental to the gate oxide performance, the metal silicate shown in Eq. (1-6) is even helpful in some aspects. Taking HfO2 and HfSiO4 for instance, the interface and crystallization temperature of HfSiO4 are

sharper and higher than those of HfO2, respectively [20][25].

In addition, Eq. (1-7) describes that excess oxygen atoms diffuse through the metal-oxide dielectric to the substrate and react with silicon at high temperature. This reaction produces unsatisfactory interfacial layer more easily in the ultrathin film regime. Hence, in order to precisely control the EOT of the high-κ dielectric and obtain better interface, we have to discover certain high-κ metal oxides which possess excellent thermal stability with Si-sub at high temperature.

1.2.3 Interface Quality

A definite goal of any potential high-κ gate dielectrics is to have a sufficiently high-quality interface with Si channel, as close as possible to that of SiO2. The SiO2 gate

dielectric has a midgap interface state density Dit ~ 2×1010 states/cm2 [16]. However, the most

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6

V without sensitive to temperature, and flat-band voltage shift ∆VFB > 300 mV [20].

Therefore, it is the same important to choose better quality interface like that of SiO2 and

higher capacitance due to high-κ material.

1.2.4 Film Morphology

The works by Kuo-Hsing Kao et al. investigated the film morphology of high-κ dielectric CoTiO3 and identify the relation between thin-film characterization and high

temperature annealing [26]. There is no peak of crystalline CoTiO3 in XRD spectrum

observed before 700°_{C-annealing as shown in figure 1.5. Then, the crystallization of CoTiO} 3

in SPM images starts to appear and the oxide grains grow up with increasing temperature as shown in figure 1.6. Because grain boundaries present as high leaky paths, it is expected to find a material which remains in an amorphous phase even if the film undergoes high temperature processes.

1.2.5 Process Compatibility

There are several investigated methods to form a high-κ gate dielectric as the following: 1) physical vapor deposition (PVD) [27]; 2) chemical vapor deposition (CVD) [28]; 3) molecular beam epitaxy (MBE) [29]; 4) sol-gel spin coating [26].

The mostly used PVD techniques are e-gun evaporator and sputtering. Although the two PVD methods could be operated at normal temperatures for unlimited substrate materials, the poor step coverage is the biggest challenge to be improved for depositing a uniform layer. However, the inevitable plasma damage leads to the surface damage and thereby produces unacceptable interfacial states [20].

CVD briefly contains metal organic chemical vapor deposition (MOCVD), jet vapor deposition (JVD) and atomic layer deposition (ALD). Although most of CVD methods have been proven to possess steeper step coverage, the ALD method seems to be more promising to

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deposit better-quality high-κ gate dielectrics. Furthermore, the throughput and the requirements for instrument are considered particularly, so the ALD method is better than MOCVD and MBE methods [20].

1.3 Sol-Gel Spin Coating Method

In the recent years, many technologies have been proposed to form high-κ gate dielectrics, such as e-gun evaporator, sputtering, MOCVD, ALD, JVD and MBE. However, the sol-gel spin coating method still attracts much attention, and it is used to the high-κ gate dielectric films, memory charge trapping layers and active channel of oxide-based transistors as shown in figure 1.7 [26][30-33].

In the sol-gel processes, hydrolysis, condensation, and polymerization, the step-by-step formation causes a metal-oxide network. And there is an capturing feature of sol-gel spin coating method and an ability to compound into new types of high-κ materials, called “inorganic-organic hybrid” [34].

The sol-gel spin coating method could be executed easily in a normal pressure environment rather than in a high vacuum system, and the spin coating to form the thin-film structure is simpler than initial approaches mentioned because of its more low-priced precursors and instruments. The temperature of this method is low enough to be compatible with plastic substrates, and oxide-based semiconductors have been also applied to be active layers of thin-film transistors (TFTs) as shown in figure 1.8 [35-41].

This study principally makes use of the sol-gel spin coating method to form the high-κ gate dielectrics and we will apply this dip-coating method in the fabrication procedure of the polycrystalline silicon (poly-Si) TFTs.

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8

1.4 Summary of Thin-Film Transistors

Although the concept of a thin-film field-effect transistor was presented as early as 1935 [42], the first functional thin-film transistor (TFT) was reported by P. K. Weimer in 1961 [43]. After that, TFTs have been intensively researched for possible electronic and display applications. The first active-matrix liquid-crystal display (AMLCD) was composed of CdSe TFTs and nematic liquid crystal [44]. Although there are many successful demonstrations of CdSe TFT LCDs, the industry production was retarded until the report on the feasibility of doping amorphous Si (α-Si) by the glow discharge technique in 1975 was introduced [45]. Since then, α-Si TFT LCDs have become the mainstream for mass-produced AMLCDs for several reasons. First, the characteristics of α-Si TFTs are remarkably well matched to the requirements of liquid-crystal driving, since they have a low off current with good on/off ratios. Second, both the gate insulator and the α-Si layers can be deposited in the same plasma-enhanced chemical vapor deposition (PECVD) system, so that contamination of the critical interface can be avoided. Eventually, α-Si TFTs can be made at low temperatures (250°C-350°C), thus allowing the use of inexpensive glass substrates [46].

Even if the α-Si TFTs possess aforementioned advantages, the most serious drawback is the low carrier mobility in the range of 0.5-1.0 cm2/V-s. This makes α-Si TFTs sufficient only for switching devices for each pixel in a display, and cannot meet the desired specifications for high-resolution panels. In addition, the α-Si TFT is not compatible with the CMOS process.

The problem of the low carrier mobility in α-Si TFTs can be got over by introducing polycrystalline silicon (poly-Si) replacing α-Si as a semiconductor layer of TFTs. Besides the higher carrier mobility, there are several advantages of poly-Si TFT LCDs. First, the driver circuitry can be integrated on the display’s substrate to realize the system on panels (SOP). Thus, the size of the total panel and cost, including drivers and related procedures, are

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reduced compared to the α-Si TFT LCDs. Second, the driver contact number of the poly-Si TFT LCD is more than one order of magnitude smaller than that of the α-Si:H TFT LCD. Third, the poly-Si TFT plate has a smaller pixel size and larger aperture ratio in each pixel than that of the α-Si:H TFT plate. Higher mobility means that the pixel charging can be achieved by a smaller-size TFT, so that it contributes more pixel area for light transmission. Finally, TFT LCD with self-alignment and COMS process compatibility can be achieved [47][48].

Because the process of high-temperature poly-Si TFTs is as high as 900°C, the expensive quartz substrates are necessary. Due to the limited profitability of quartz substrate size, most typical applications for high-temperature poly-Si TFT-LCDs are panels for projection displays, because the panel size is limited to small sizes. For low-temperature poly-Si TFTs (LTPS TFTs), the maximum fabrication temperature is below 600°C and hence, low-cost glass substrates could be employed. This would bring about the production of large-area displays such as monitors and televisions [49]. Therefore, LTPS TFTs have attracted much attention due to their increasing application in high-resolution flat displays such as active-matrix liquid-crystal displays (AMLCDs) [50-54], active-matrix organic light-emitting diode (AMOLED) displays [55-58]. In addition, for the recent reported papers, ZnO is presently attracting much attention due to its possibilities for replacing α-Si that has been widely used as the channel layer in conventional TFTs [32][36][37][38].

Among the many barriers to the low-temperature process of LTPS TFTs, the formation of poly-Si films is the most important issue. There are several methods to fabricate a low-temperature poly-Si film, described as the following:

1.4.1 Solid-Phase Crystallization

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10

processes are characterized by specific activation energies. For the SPC of α-Si by homogeneous nucleation, the activation energy of grain growth is less than that of nucleation [60]. Thereby, the amount of the nucleation relative to grain growth decreases with reducing annealing temperature. In order to enlarge the grain size, it is desirable to minimize the nucleation/grain growth ratio, and the SPC is typically done at a low temperature [61]. However, the SPC process is time-consuming about 20 hours for the crystallization of the α-Si film to the poly-Si film. Besides, such poly-Si films have a high density of intra-grain defects which lead to decrease the field-effect mobility and increase the threshold voltage of the TFTs [62].

1.4.2 Metal-Induced Lateral Crystallization

With some metals added to the α-Si films, the crystallization temperature can be lowered to below 600°_{C, and this phenomenon is known as metal-induced crystallization (MIC) [63].}

Metals such as Au, Al, Sb and In, which form eutectics with Si, or metals such as Pd, Ti and Ni, which form silicides with Si, have been added to α-Si films to enhance the nucleation rate. During the MIC process, metal atoms dissolved in α-Si films may weaken Si bonds and enhance the nucleation of crystalline Si [64]. Some results were reported to be effective in lowering the crystallization temperature down to 500°C. However, an undesirable metal contamination at the channel region results in the poor electrical properties of the devices. A new method which can reduce metal contamination, called metal-induced lateral crystallization (MILC), has been reported for Pd, where large grains over several tens of microns are achieved [65]. Moreover, many groups have proposed TFTs to be successful in terms of device characteristics and mass productivity with MILC poly-Si, using pure Ni [66][67], Ge [61] and Ni-Co alloys [68].

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1.4.3 Excimer Laser Annealing

Excimer laser annealing (ELA) is considered to be the most promising method for the fabrication of LTPS TFTs [69][70][71]. The ELA method is performed by melting α-Si with high-power pulsed laser irradiation. The irradiated α-Si film is then cooled and solidified as a crystal. During the melt-growth period, however, the solidification velocity is too high for the film to form nuclei and to grow sufficiently. For this reason, the grain size of the poly-Si film is not large enough. Besides, non-uniformity of grain size and narrow process window make it difficult to achieve uniform TFTs performance.

To realize this, some techniques such as the bridge method [72], low-temperature substrate heating during laser irradiation [73] and two-step laser crystallization [74] have been proposed to reduce the solidification velocity. In addition, for gaining higher mobility, lateral crystallization is one of the techniques used. The laser beam intensity is spatially modified over the α-Si to control the solid/liquid interface, causing lateral crystallization of the film. With this technique, the field-effect mobility of TFTs more than 300 cm2_{/V-s can be achieved}

[75].

1.5 Plasma Treatment

According to Moore’s law, the significant scale of the transistors is going to shrinking quickly. Nowadays in order to satisfy two requirements of high operating speed and high integrated density, introducing high-κ materials will be the best choice to replace the gate silicon dioxide layer in the future generations. Although high-κ materials improve many kinds of problems in reducing the thickness of the conventional gate silicon dioxide layer, oppositely it results several thorny questions to be resolved. The questions are as the following: 1) Low-κ interfacial layers are produced. When high-κ materials are deposited, oxygen diffuses the loose thin films. Then the oxygen would react with Si-sub to form low

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12

quality silicon dioxide and/or metal oxides and limit the EOT scaling down. 2) There are amounts of fixed charges existing in high-κ thin films and resulting in threshold voltage shift to degrade the gate controllability. 3) Carrier mobility degrades. When high-κ thin film is deposited on the Si-sub surface, there are lots of dangling bonds produced from lattice mismatch. For this reason, the electrons moving in the channel are also affected by Coulomb’s scattering, and the driving current degrades. 4) Crystallization temperature is low. The changed phase in high fabrication temperature makes thin films crystallize to increase the probability of leakage current and impurity penetration, e.g. boron penetration. Because of this, many groups suggested to insert a step of surface plasma treatment into the fabrication procedure.

In terms of electrical and optical properties of polycrystalline silicon thin-film transistors (poly-Si TFTs), grain boundaries and intragranular defects exert a profound influence on device characteristics and degrade carrier transport. These defects have been measured by electron spin resonance (ESR) and identified as silicon dangling bonds [76]. In order to obtain device-grade material, it is essential to minimize the dangling-bond density. Commonly, this is achieved by the incorporation of hydrogen which effectively passivates Si dangling bonds and thus improves the electrical properties of the material [77][78]. Afterward several groups proposed an oxygen plasma treatment of poly-Si TFTs which significantly improves the device performance. Furthermore, combinations of H2 and O2 plasma treatments to poly-Si

TFTs were found to be more efficient than just a hydrogen or oxygen plasma [79][80][81]. Besides, the NH3-plasma passivation was employed to enhance both the electrical reliability

and the thermal stability of the poly-Si TFTs.

A hydrogenation process has been utilized to reduce the poly-Si film trap states to improve device performance. However, the poly-Si TFTs characteristics after hydrogen passivation suffer from serious instability issue due to weak Si-H bonds, causing inferior reliability for product applications. Accordingly, the NH3-plasma passivation after gate oxide

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deposition can improve the electrical properties of the poly-Si TFTs because of the passivation effect of hydrogen and nitrogen radicals [82][83][84]. In our study, we will apply the NH3 plasma treatment to our fabrication procedure to compare with the poly-Si TFTs

without this process, and the more detail results and discussion with this treatment will be demonstrated in the fourth chapter.

1.6 Polysilicon Thin-Film Transistors with High-

κ

Gate Dielectrics

As aforementioned in section 1.4, low-temperature polycrystalline silicon thin-film transistors (LTPS-TFTs) have been used for active-matrix liquid crystal displays (AMLCDs) and system on panel (SOP) on glass substrate as pixel switch devices and driving integrated circuits instead of amorphous silicon (α-Si), because the field effect mobility (µFE) in poly-Si

is significantly higher than that in amorphous silicon. So that complementary metal-oxide-semiconductor (CMOS) devices with suitably high driving currents could be achieved in poly-Si TFTs. However, the highest temperature of TFTs fabrication procedure for the application of SOP is limited to the melting point of the glass substrate. Therefore, it is difficult to develop high-performance LTPS-TFTs with low threshold voltage (VTH), low

subthreshold swing (S.S.), low gate leakage current (IG) and high driving current (ID,sat) to

drive the liquid crystal of the large area panel, and these electrical properties have to be necessary urgently to the next generation. In order to enhance the driving current of poly-Si TFTs and break through this challenge, a thinner gate oxide must be used to increase the gate capacitance density. However, a higher gate leakage current would be introduced when the thickness of the gate oxide becomes thinner. Besides, low quality silicon dioxide (SiO2)

deposited by using a low-temperature manufacture instrument, plasma-enhanced chemical vapor deposition (PECVD), is generally employed as a gate dielectric of the traditional LTPS-TFTs. To compare with low quality SiO2, high-κ gate dielectrics could possess better

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14

quality and be more proper to replace the conventional low-temperature SiO2. Many high-k

materials have been used to suppress the gate leakage current and to enhance the transconductance (Gm). Among these dielectric materials, NiTiO3 could be the promising

candidate of the future high-κ gate dielectric because of its high permittivity (κ ~ 40). In the following chapters, poly-Si TFTs with a NiTiO3 gate dielectric prepared by sol-gel spin

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Figure 1.1 Transistor counts for integrated circuits plotted against their dates of introduction. Curve shows Moore's law - the doubling of transistor counts every two years.

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16

Figure 1.2 Trend of gate-oxide-thickness scaling over the past five technology generations from the 0.18-µm to 65-nm nodes.

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Figure 1.3 Measurement and simulation of direct tunneling currents under inversion conditions of nMOSFET’s.

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18

Figure 1.4 Leakage-current values of various high-κ dielectrics at subnanometer EOT. The leakage current was measured at accumulation ( Vfb − 1 V ) in the nMOS devices.

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Figure 1.5 XRD spectrum of spin-on CoTiO3 films. The marked peaks correspond to

crystallized CoTiO3 phases.

(0

1

2 (1

0

4 (1

1

0 )

(1

1

3 (0

2

4 )

(1

1

6 )

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20

Figure 1.6 SPM images of spin-on CoTiO3 films with various thermal treatments at

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Figure 1.7 Transmission electron micrograph of (a) ZnO/ZrO2/SiO2/Si multilayered film

heated at 900°C and (b) ZnO/ZrO2/ITO/glass multilayered film heated at 600°C.

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22

Figure 1.8 Top-gate structure of ZnO-TFT in (a) crosssectional schematic, (b) top view schematic and (c) optical transmission spectra.

(a)

(b)

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Table 1.1 High-κ gate dielectric materials with a dielectric constant reported in the literatures.

Material ε _Material ε _Material ε

Al2O3 8-11.5 LaAlO3 23.8-27 TaON

AlxSiyOz LaLuO3 32 Ta2O5-TiO2

(Br, Sr)TiO3 200-300 LaScO3 22-30 TiO2(rutile) 86-95

BeAl2O4 8.3-9.43 La2O3-SiO2 5-16 TiO2-SiO2

CeO2 16.6-26 MgAl2O4 8.3-9.4 TiO2/Si3N4

CeHfO2 10-20 Pr2O3 14.9 Y2O3 8-11.6

CoTiO3 45-50 PrAlO3 25 YxSiyOz

DyScO3 22 NdAlO3 22.5 ZrO2 22.2-28

EuAlO3 22.5 Sc2O3 13 Zr-Al-O 12-18

GdScO3 22 Si3N4 7 Zr silicate 11-12.6

HfO2 26-30 SmAlO3 19 (Zr, Hf)SnTiO4 40-60

Hf silicate 11 SrTiO3 150-250 Ta2O5-TiO2

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24

Table 1.2 Conduction mechanism in insulator with expression and band diagram.

Mechanism Expression Band Diagram

Schottky Emission

(

)

2_exp B q J T a V kT φ   ∝ _ − _   Fowler-Nordheim Tunneling 2_exp b J V V   ∝ −    Direct Tunneling * d d 2 2 exp 2 2 DT B V m q J t  _ _ ∝ _− Φ − _    h  Frenkel-Poole Emission

(

)

exp q 2 _B J V a V kT φ   ∝ _ − _   Hopping ( Ohmic ) Conduction exp c J V T   ∝ _− _   Ionic Conduction exp V d J T T   ∝ −   

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Chapter 2 Experiment Procedures

In this chapter we will illustrate the device fabrication processes of capacitors and polycrystalline-silicon thin-film transistors (poly-Si TFTs) with figures and list the instruments for material and physical properties measurements.

2.1 Device Fabrication

2.1.1 Capacitors

In this thesis, NiTiO3 films were formed by a sol-gel spin coating method in a controlled

surroundings, where was kept at temperature of 22°C and relative humidity of 43%. In the beginning, (100) p-type single crystal silicon wafers with resistivity in the range of 1-10 Ω-cm were prepared as substrates. Firstly, the bare silicon wafers were cleaned by standard RCA steps followed by a dilute-HF dip to remove the native silicon dioxide. Then, the liquid precursor for NiTiO3 was directly spun on Si substrates at about 3000 revolutions per minute,

and the spin speed was maintained for 30 seconds. However, the precursor elements of nickel and titanium were nickel acetate tetrahydrate Ni(OOCCH3)2‧4H2O and titanium isopropoxide

Ti(OCHC2H6)4, respectively. These two precursors were dissolved in 2-methoxyethanol for

the spin coating method. After the precursor was spun on substrates, in order to remove the solvent, the samples were baked step by step at different curing temperatures in atmosphere on a hotplate as shown in figure 2.1. And the procedure (coating-and-baking) was repeated for 5 times due to for poly-Si TFTs fabrication. Then, the spin-on NiTiO3 films were oxidized at

400°C in N2/O2 ambient with 50-sccm airflow for 10 min. In order to investigate the

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26

treatment, rapid thermal annealing (RTA) was performed. The samples were annealed at temperatures of 500°_{C, 600}°_{C, 700}°_{C, 800}°_{C, and 900}°_{C for 30 seconds in N}

2 ambient.

Photolithography was used to define gate areas and then TaN metal was deposited on the top of the samples by reactive DC-sputtering. Lift-off was performed to fabricate the MIS capacitors. Finally, ohmic contacts were formed by thermal evaporation of 300-nm-thick aluminum (Al) electrode on the backside of the samples. The process flow of a capacitor was shown in figure 2.2.

2.1.2 Polycrystalline-Silicon Thin-Film Transistors

In this section, we will make a description on the process flow of thin-film transistors with sol-gel spin coating NiTiO3 films and the main fabrication steps were summarized as

shown in figure 2.3. In the beginning, all wafers proceeded from using the traditional RCA cleaning to remove any contaminations, native oxide, and atomic scale roughness. Subsequently, a 500-nm thermal oxide grown on 6-inch silicon wafers by using a horizontal furnace was used to simulate the glass substrate of the active matrix liquid crystal display (AMLCD). And then, an undoped amorphous silicon (α-Si) film with a 50-nm thickness was deposited on the 500-nm thermal oxide by using a low-pressure chemical vapor deposition (LPCVD) system in silane (SiH4) ambient with a pressure of 350 mtorr at 560 °C as shown in

figure 2.3(a). After a 24-hour annealing at 600°C by using the conventional solid-phase crystallization (SPC) method due to its low-production cost and good grain-size uniformity, amorphous silicon became to poly-crystalline silicon (poly-Si). Active area region was patterned by photolithography and then source/drain region were formed by using BF2 ion

implantation as shown in figure 2.3(b). The following steps were to spin NiTiO3 material as a

gate dielectric on poly-Si films by using the sol-gel spin coating method for 5 times as the aforementioned step. Then, the spin-on NiTiO3 films were oxidized at 400°C in N2/O2

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samples were just annealed at 500°_{C, 600}°_{C, and 700}°_{C for 30 seconds in N}

2 ambient. A

200-nm-thickness TaN metal was deposited on the top of the samples by reactive DC-sputtering at 600 mtorr with a DC power of 1500 watt and patterned as the gate electrode by photolithography as shown in figure 2.3(c). A 400-nm tetraethoxylsilane (TEOS) oxide film used as an inter-layer dielectric (ILD) layer was deposited by using a plasma-enhanced chemical vapor deposition (PECVD) system at 300°C. Then contact holes were opened and etched by by using a buffered oxide etching (BOE) solution as shown in figure 2.3(d). Aluminum (Al) electrode with 600-nm thickness was deposited by e-gun evaporator, and then the aluminum pads were lithographically patterned. Subsequently, metal pads were etched by using a TCP metal etcher, and thus the poly-Si TFTs with a high-κ NiTiO3 gate dielectric

prepared by sol-gel spin coating method were accomplished as shown in figure 2.3(e). Eventually, an NH3 plasma treatment was performed at 350°C for 30 min for partial samples,

which were the poly-Si NiTiO3 TFTs with a 500°C-RTA treatment after the Al gate electrode

formation in order to compare to the samples without NH3 plasma treatment.

2.2 Material and Physical Properties Measurements

The microstructure of spin-on NiTiO3 films and silicon substrate were investigated by

JEOL JEM-2010F field emission transmission electron microscope (TEM) equipped with Link ISIS-300 energy dispersive X-ray analyzer (EDS). And the TEM EDS with a 0.23-nm electron beam size was used to perform chemical analysis qualitatively.

The property of crystallization of spin-on NiTiO3 film with different annealing

temperatures was identified by PANalytical X’Pert Pro X-ray diffraction system under normal atmosphere. Optical module with X-ray mirrors and a parallel plate collimator was used to perform gracing incident X-ray diffraction (angle of incidence θi ~ 1°). The beam source

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28

operating at 1.8 kW.

Surface morphology of spin-on NiTiO3 film with different annealing temperatures was

obtained by Veeco multimode scanning probe microscope (MMAFM) at normal atmosphere. The highest resolution in X-Y plane and Z direction were about 1.5 nm and few angstroms, respectively. And the tip curvature radius was about 2 nm.

A ULVAC-PHI Quantera high resolution X-ray photoelectron spectrometer (HR-XPS) with 180° spherical capacitor analyzer was used to analyze quantitatively the chemical composition of the dielectrics NiTiO3 prepared by sol-gel coating method.

The capacitance-voltage (C-V) curves and current-voltage (I-V) curves of capacitors were measured in the same probe station by using HP 4284 and Keithly 4200, respectively.

2.3 Equation Derivation and Electrical Parameters Extraction

In this section, we firstly formulate a general drain current for thin-film transistor by using gradual channel approximation (GCA) model, which the variation of the electrical field along the channel is much less than the corresponding variation perpendicular to channel. Hence, the inversion charges density (Q_inv) could be simplified to the 1-D form of Possion’s equation. The current-voltage characteristic of the thin-film transistor could be calculated by estimating the elemental resistance dR and the elemental segment dy of the conducting channel given by

( )

| | DS DS EF inv dy dV I dR I Wµ Q y = = _(2-1)

, where W is the channel width and µ_EF is the field-effect mobility. Then, integrate Eq. (2-1) from source (V=0 at y=0) to drain (V=VDS at y=L). The drain current could be expressed as

0 0 =

∫

DS V L DS FE inv I dy µ W Q dV 0 =

∫

DS V DS FE inv W I Q dV L µ . (2-2)

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Following, we use the charge-sheet approximation model, which assumes that the inversion charges (Q_inv) are located at the silicon surface as a sheet of charges with no potential dropping or band bending across the inversion layer, to derive drain current as

(

2

)

2

(

2

)

= − = − − − − + +

inv S dep ins GS fb B Si B B

Q Q Q C V V ψ V ε qN ψ V (2-3)

, where Q_S is the total surface charge density, Q_dep is the depletion charge density, V_fbis the flat band voltage, the surface potential ψ_S is pinned at ψS=2ψB+V y

_{( )}

, Cins is the gate

capacitance density of insulator layer, ε_Si is the dielectric constant of silicon, and N_B is the effective channel dpoant in active channel of the thin-film transistor. Substituting Eq. (2-3) into Eq. (2-2) and carrying out the integration, the drain current (I_DS) could be presented by

(

)

2 0 2   = =  − −   

∫

DS V DS FE inv FE ins GS TH DS DS W W m I Q dV C V V V V L L µ µ (2-4)

, where the body-effect coefficient m and the threshold voltage V_TH are / 4 1 = + Si B B ins qN m C ε ψ and = +2 + 4 Si B B TH fb B ins qN V V C ε ψ ψ , respectively. (2-5)

When the device works in saturation region, the I_DS is independent on V_DS, which means

(

)

0 = − − = DS GS TH DS DS dI V V mV dV , −   = _{= } _   GS TH DS DS sat V V V V m . (2-6)

Substituting Eq. (2-6) into Eq. (2-4), the saturation current I_{DS sat}_, could be written as

(

)

2 , ₂ − = GS TH DS sat FE ins V V W I C L m µ (2-7)

In m= case, the Eq. (2-4) and Eq. (2-7) could be simplified by 1

(

)

2 , , 1 2   = _ − − _  

DS lin FE ins GS TH lin DS DS

W

I C V V V V

L

µ for linear operation (2-8)

and

(

)

2 , 1 2 = − DS sat FE ins GS TH W I C V V L

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30

Secondly, we will introduce the extractions of the device electrical parameters. An automatic measurement system, ICS software, combined a personal computer (PC), Agilent-4156 semiconductor parameter analyzer, Agilent-4285 precision LCR meter, Agilent E5250A low leakage switch mainframe, and a probe station is used to measure the drain-source current versus gate-source voltage (IDS-VGS) curves and the drain-source current

versus drain-source voltage (IDS-VDS) curves of the fabricated thin-film transistors. The

electrical parameters of thin-film transistors, for examples on the threshold voltage (VTH), the

subthreshold swing (S.S.) and the field-effect mobility (µFE), are also extracted to estimate the

benefits of integrating high-κ NiTiO3 gate dielectric or nitrogen incorporation.

According to the thin-film transistor theory described in Eq. (2-8), in the linear regime,

,

< −

DS GS TH lin

V V V , and the drain current (IDS,lin) could be described as

(

)

, = − ,

DS lin FE ins GS TH lin DS

W

I C V V V

L

µ (2-10)

Thus, the transconductance (Gm) in the linear regime is given by , ∂ = = ∂ DS lin m FE ins DS GS I W G C V V µ L (2-11)

Therefore, the field-effect mobility in the linear regime (µFE,lin) could be obtained as

, ~0.1 1 1 = DS FE lin m V V ins DS L G W C V µ _(2-12)

, where the drain-source voltage (VDS) is usually set at 0.1 V. Because the inversion carriers in

the active channel layer could be easily drained out with enough high carrier mobility at low drain bias, we calculate the field-effect mobility in the linear regime (µFE,lin) for

low-temperature polycrystalline silicon (LTPS) TFT device. The transfer curve of LTPS TFT device, drain current (IDS,lin) versus gate-source voltage (VGS), is measured at VDS = 0.1 V, and

then µFE,lin could be obtained by using Eq. (2-12).

For extraction convenience, the threshold voltage (VTH) is defined as the gate voltage

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current ratio (ION, max/IOFF, min) and the subthreshold swing (S.S.) present the switching and the

gate-controlled capabilities of TFT device, respectively. In this work, the ON/OFF current ratio of LTPS TFT device is defined as that ratio of the maximum on-state current to the minimum off-state current at VDS = 1 V. The subthreshold swing is measured at the inverse of

the maximum slope in the plot of drain current (in denary logarithm) versus gate-source voltage (VGS).

By integrating the depletion charges (Qdep) in active channel with the charge-sheet

approximation , the subthreshold current (IDS,SUB) in the subthreshold region (at a small VDS~

0.1 V) could be derived as the following equation:

2 2 , ₂ exp       =             Si B B i S DS SUB FE ins S B B q N k T n q W I C L q N k T ε ψ µ ψ (2-13)

, where the surface potential ψ_S could be expressed in terms of V_GS 2 = + + Si B S GS fb S ins qN V V C ε ψ ψ . (2-14)

Considering ψ_S ~ 2ψ_B in the subthreshold region, the Eq. (2-14) could be expand to the square-root term around 2ψ_B as

(

)

(

)

4 / 4 2 SiqNB B 1 SiqNB S 2 2 V_GS V _B _S _B V_TH m _S _B fb _C _C ins ins ε ψ ε ψ ψ ψ ψ ψ ψ = + + + + − = + −         (2-15)

, where the body-effect coefficient m is / 4 1 1 = + Si B S = + dep ins ins C qN m C C ε ψ (2-16) and C_dep is the depletion capacitance density. Substituting Eq. (2-16) into Eq. (2-13) yields the subthreshold current as a function of VGS

(

)

(

)

2 , 1 exp −     = −         GS TH S B DS SUB FE ins B q V V k T W I C m L q mk T ψ µ . (2-17)

(45)

32

Consequently, the subthreshold swing (S.S.) could be presented following equation:

1 10 , log . . 2.3 2.3 1 −     =  = =  +      dep DS SUB B B GS ins C d I mk T k T S S dV q q C . (2-18)

If we consider the effective interface trap-state densities N_it =qC_it substituting into Eq. (2-18), the subthreshold swing (S.S.) neglected the depletion charges (Qdep = q × Cdep) could

be rewritten as 1 10 , log . . 2.3 1 ~ 2.3 1 − +       =  =  +   +        dep it DS SUB B B it GS ins ins C C d I k T k T qN S S dV q C q C . (2-19)

Therefore, the maximum interface states density (NSS,max) presents the interface quality

between the dielectric and the active channel layer of TFT device could be calculated from the S.S. without the depletion capacitance as

,max . . ₁ 2.3      =  −         OX SS B C S S q N k T q . (2-20)

In pentacene-based organic TFT device case, because its inversion carriers in the active channel could not be easily drained out the device with a low carrier mobility at a low drain bias, its parameters are usually extracted in the saturation regime (V_DS >V_GS−V_TH) as

(

)

2 , 1 2 = − DS sat FE ins GS TH W I C V V L µ . (2-21)

The Eq. (2-21) could be transposed by VGS as

, 2 = + GS TH DS sat FE ins L V V I C W µ . (2-22)

Hence, the threshold voltage (VTH) could be determined from the maximum slope in the

square-root plot (IDS1/2−VGS) of the transfer characteristic and we fit a straight line to the

IDS1/2−VGS curve at the point extrapolated to IDS = 0. Following, substitute the obtained VTH

from Eq. (2-22) back into Eq. (2-21), and then the field-effect mobility in the saturation regime (µFE,sat) of the organic TFT device could be obtained as

利用凝膠轉塗佈法製備高介電常數鈦酸鎳閘極介電質層於複晶矽薄膜電晶體之研究

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電子物理學系

電子物理學系

電子物理學系

電子物理學系

碩

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利用凝膠轉塗佈法製備高介電常數鈦酸鎳閘極

利用凝膠轉塗佈法製備高介電常數鈦酸鎳閘極

利用凝膠轉塗佈法製備高介電常數鈦酸鎳閘極

利用凝膠轉塗佈法製備高介電常數鈦酸鎳閘極

介電質層於複晶矽薄膜電晶體之研究

介電質層於複晶矽薄膜電晶體之研究

介電質層於複晶矽薄膜電晶體之研究

介電質層於複晶矽薄膜電晶體之研究

Study on Polysilicon Thin-Film Transistors with High-

κ

κ

κ

κ

NiTiO

3

Prepared by Sol-Gel Spin Coating Method

研 究 生：顏榮家

指導教授：趙天生 博士

利用凝膠轉塗佈法製備高介電常數鈦酸鎳閘極介電質層

利用凝膠轉塗佈法製備高介電常數鈦酸鎳閘極介電質層

利用凝膠轉塗佈法製備高介電常數鈦酸鎳閘極介電質層

利用凝膠轉塗佈法製備高介電常數鈦酸鎳閘極介電質層

於複晶矽薄膜電晶體之研究

於複晶矽薄膜電晶體之研究

於複晶矽薄膜電晶體之研究

於複晶矽薄膜電晶體之研究

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學生

學生

學生：

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研究生：顏榮家

指導教授：趙天生博士