Table 4.2: The verification results on ASIC
Design ASIC
A word-based RSA scheme is given in this work. This section shows the hardware implementation results. In this thesis, all of the design in hardware is implemented using RTL (Register- Transfer-Level) Verilog HDL (hardware description language) and synthesized on application-specific integrated circuit (ASIC). The technology of ASIC design is using UMC1 90nm CMOS process. The RTL synthesizer uses Synopsys3 Design Compiler for ASIC. The data throughput of RSA is given by
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The clock frequency is set to 285.7MHz and gatecount is 467k with three Montgomery multipliers. Cycle period is 3.5ns. The cycles of multiplication are about ( n + p)*90% cycles. And The cycles of RSA are about (n+2)*(MM cycles). Where Montgomery method must transport domain between integer and Montgomery domain, So there are two extra MM cycles for transporting. The detail value is shown as table 4.2.
Table 4.3: Comparison with other 1024-bit Modular Multiplier with cell base design
Table 4.3 shows the comparison with other 1024-bit modular multipliers implementations with ASIC design. Our work is not the most outstanding, but our works are scalable designs and [29] is not. Proposed designs can be modify to high radix architecture. The performance would be better than now.
Author [29] [30] Proposed
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Table 4.4: Comparison with other 1024-bit RSA cryptosystem with cell base design
Table 4.4 shows the comparison with other 1024-bit RSA implementations with ASIC design. In contrast to proposed design, the work shows a big area but the throughput is higher. In the nearly future, ROC government will establish 4096 bits RSA for standards. That means high throughput is the first consideration. The area of Mukaida‟s work is much higher than the others, since it is radix-232 and calculates some parameter beforehand. The throughput of proposed work is higher than any others. We add one more Montgomery multiplier to against DPA attack. One Montgomery multiplier‟s gate count is about 130k. And it doesn‟t affect the frequency or throughput.
Initial seed of random number generator is given by user.
Author Mukaida [22]
[21] Chen[25] Lin[24] Proposed
Technology 0.18μ m 0.18μ m 0.18μ m 0.18μ m 90nm
Methodology CRT Montgomery Montgomery Montgomery
Clock
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Chapter 5
Conclusion
In this thesis, a hardware architecture of word-based scalable RSA cryptosystem in GF(p) is given. In order to reduce execution time, a Montgomery modular multiplication algorithm and circuit are proposed. Forwarding circuit solves data dependency hazard of word-based Montgomery multiplication from two cycles to one cycle. Furthermore, bypass algorithm combines redundant shift operation, which shortens latency of processing modular multiplication about 90% of original work. The total cycles of processing multiplication once are about n*90%+(n/p). Proposed Montgomery multiplier architecture is applied in RSA or ECC cryptosystem. This work can be modified to support binary field GF(2n) operation by simply eliminating the carry.
On the other hand, we modify random number generator based on Chaotic map.
Higher passing rate RNG may suite for cryptosystem application. The total RSA architecture includes three MMs and one RNG, it against SPA and DPA without extra multiplication. The total cycles of processing modular exponentiation are n+2 times MM processing cycles. According to implementation result, it is synthesized using 90nm CMOS technology with 467k gates. The clock period is 3.5 ns.
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作者簡介
姓名：陳勇志
學歷：三興國小 信義國中 建國中學
93.9~97.6 國立交通大學電子工程學系 97.9~99.12 國立交通大學 電子研究所