Chapter 2 Material and Method
A. Instrumentation Amplifier
Instrumental amplifier INA2126 was used as the first stage of analog amplifier.
INA2126 consists of 2 channel instrumentation amplifiers into one package. INA2126 owns an ultra low input current and a high common-mode rejection ratio (CMRR) about 90dB. A high CMRR is important in applications that the signal of interest is represented by a small voltage fluctuation superimposed on a (possibly large) voltage offset, or when relevant information is contained in the voltage difference between two signals. Instrumental amplifier INA2126 provided not only the function of gain, but also that of one stage high pass filter by adding a capacitor. The output voltage of the INA2126 is referenced to the voltage on the reference terminal.
INA2126EA/250G4 we selected was DBQ package drawing and about 5mm x 6mm size. The Instrumentation amplifier circuit design is shown in Fig. 2-11 and the simulation of frequency response is in Fig. 2-12.
Fig. 2- 11: Left- the RG decides the gain of preamplifier, and the high pass filter of preamplifier decided by RG and C. Right- block diagram of INA2126
5 80
Fig. 2- 12: Simulation of amplifier’s frequency response in stage 1 B. High Pass Filter
In this thesis, operational amplifiers were used to achieve the function of band-pass filter. The AD8609 is quad micro-power rail-to-rail input and output amplifiers and low dc offset was chosen to be high pass filter. Fig. 2-13 shows one channel High-pass filter circuits. The 3dB cutoff frequency of high pass was decided by passive components R3, R4, C1 and C2; and the other component R1, and R2 are responsible for enhancing magnification. AD8609AR we selected was 14-Lead SOIC package description and about 8.5mm x 6mm size. Fig. 2-14 shows the simulation of amplifier’s frequency response (EEG) in stage 2 and Fig. 2-15 shows the simulation of amplifier’s total frequency response.
2 1
1 R Gain= + R
3 4 1 2
1
H 2
f = π R R C C
Fig. 2- 13: High-pass filter circuits.
Fig. 2- 14: Simulation of amplifier’s frequency response in stage 2.
Fig. 2- 15: Simulation of amplifier’s total frequency response.
2.3.3.2 Multiplexer
As shown forward, for Multi-channels EEG system design, we select INA2126 x 8 and AD8609 x 4 to measure 16 channel bio-signals. The analog information would carry to next stage – analog-to-digital converter (A/D), but the number of A/D is finite.
Hence there was need a multiplexer sequentially pass analog information to A/D. In other words, the major work of Multiplexer is Allocating finite resource to Multi-channels.
In addition, next issue is which stage multiplexer suited to serve. To consider that tiny analog signal mixing noise from environment go through multiplexer may mix other noise more, the amplified analog signal (noise is smaller than real EEG signal) fitted to be the input of multiplexer. Therefore, Multiplexer placed behind front-end circuit and forward A/D of micro-controller.
CD74HC4607 is a 16-to-1 multiplexer, and it can be fabricated to about 8mm x 8mm size (CD74HC4607SM96) by very small package SSOP. We researched the sizes of 2-to-1 multiplexer x 8, 4-to-1 multiplexer x 4, and 8-to-1 multiplexer x 2 were all not smaller than a 16-to-1 multiplexer for the smallest package in existing fabrication procedure. As shown by Fig. 2-16, select pin S0, S1, S2, and S3 and
select-valid pin Inhibit was linked to output pin of micro-controller. Output pin - out was linked to A/D of micro-controller. Multiplexer should achieve passing analog signal from input to output into 250 us in which micro-controller make select pin
“On”. Because the maximum transmission time of CD74HZ4607 is about 300 ns in 25°C temperature, it made no problem for high-speed 16-to-1 Multiplexer CD74HZ4607.
Fig. 2- 16: The outer appearance and block diagram of CD74HC4067
2.3.3.3 Analog to Digital Converter and Micro-controller
For the data acquisition system, it needs a controller to organize the working of ADC and encode the digital data to Bluetooth module by UART port.The MSP430 is particularly well suited for wireless RF or battery powered applications. The MSP430 incorporates a 16-bit RISC CPU, peripherals, and a flexible clock system that interconnect using a von-Neumann common memory address bus (MAB) and memory data bus (MDB) shown as Fig. 2-17. The clock system is designed specifically for battery-powered applications. Dedicated embedded emulation logic resides on the device itself and is accessed via JTAG using no additional system resources. We configure with built-in 16-bit Timer A, a fast 12-bit A/D converter, one
universal serial synchronous/asynchronous communication interfaces (USART) and 4M Hz external oscillator to development our design [14].
Fig. 2- 17: MSP430 Architecture [14]
Timer A triggers Analog to Digital Converter, and buffers the output data of ADC until buffer full. And then all buffer data will be transmitted via USART. The operating flow chart in MSP430F1611 was shown in Fig. 2-18.
Fig. 2- 18: Operating flow chart in MSP430F1611
A. Timer Interrupt
The interrupt function of MSP430F1611 is based on inner timer/counter register,
set first, as shown in Fig. 2-19. When the timer counted to the TACCR0 value, the TACCR0 CCIFG interrupt flag would be set. When the timer counted from TACCR0 to zero, the TAIFG interrupt flag would be set. In our Mobile EEG acquisition module, 4.096MHz crystal oscillator was used as system clock of MSP430F1611, and TACCR0 is set to 1024 for making a rate 4 kHz.
4.096M
T AC C R 0= 1024
4k =
Fig. 2- 19: Timer A up mode for interrupt function of MSP430F1611
Time A uses 4 kHz to control select pin of multiplexer via output pin of MSP430, so the switching rate from one channel to the other one is 2 kHz. When finishing the sequential visit for all channels, total time is 8 ms. In this way, our propose system can implement 125Hz of sampling rate to catch analog signal.
B. Analog to Digital Converter
In this system, for passing the signal through wireless, it needs an analog to digital converter to convert the continuous signal to discrete number. To suit with the filtered and amplified signal from front-end circuit, built in ADC of MSP430 was chosen to be an analog to digital converter.
Fig. 2-20 shows ADC12 Block Diagram. The ADC12 module supports fast, 12-bit analog-to-digital conversions. The module implements a 12-bit SAR core, sample select control, reference generator and a 16 word conversion-and-control
buffer. The conversion-and-control buffer allows up to 16 independent ADC samples to be converted and stored without any CPU intervention [14]. The ADC12 inputs are multiplexed with the port P6 (A0-A7) pins, which are digital CMOS gates. An analog-to-digital conversion is initiated with a rising edge of the sample input signal SHI. The signal SHI will be set by interrupt routine of timer A at 2 kHz. The ADC12 module is configured by three control registers, ADC12CTL0, ADC12CTL1 and ADC12MCLTx. Those registers are set to enable core, select conversion clock, set conversion mode, sample and input channels define. In our system, we used the “one channel, single conversion each” mode. In this mode, the certain channel is sampled and converted once. Fig. 2-21 shows a diagram for sampling time and conversion time of ADC with trigger by timer A. Therefore, the conversion time of ADC is fast enough to fit the requirement of the sampling rate of the whole system. The ADC result of each channel will be 12 bits long in the form of an unsigned integer whose value is: Ax -
Vr-4095*
Vr+ -
Vr-Fig. 2- 20: ADC12 Block Diagram [14]
Fig. 2- 21: Diagram of the sampling and conversion with timer A trigger
Fig. 2- 22: Transmission buffer
When conversion results are written to a selected ADC12MEMx, the corresponding flag in the ADC12IFGx register is set. An interrupt request is generated if the corresponding ADC12IEx bit and the GIE bit are set. After ADC12IFGx register set, the interrupt service routine of ADC started. In the interrupt service routine, we buffered ADC12MEMx. Next, a moving average filter was used to remove 60-Hz power interference, and then filtered signal data was encoded before wireless transmission. Fig. 2-22 shows transmission buffer, and Table 5 shows data format saved in transmission buffer.
Table 5: Data format (channel number)
Header information data
ff 74 (1) high byte (1) low byte (2) high byte (2) low byte …… (16) high byte (16) low byte
C. Moving Average
Moving average, also called rolling average or running average, is usually used to analyze a set of data points by creating a series of averages of different subsets of the full data set. Moving average can be applied to any data set, however, it is most commonly used with time series data to smooth out short-term fluctuations and highlight longer-term trends or cycles. The choice between short- and long- term, and the setting of moving average parameters depends on the requirement of application.
Mathematically, moving average is a type of convolution and is similar to a low-pass filter used in signal processing. The moving average filter is optimal for a common task: reducing random noise while retaining a sharp step response. This makes it as the premier filter for time domain encoded signals.
Given a sequence
{ }
ai iN=1, the output of an n-moving average is a new sequence{ }
si iN n=1− +1 defined as the average of subsequences of n terms. The formula of movingaveraging was shown as followings.
1
Fig. 2-23 shows the results of noise cancellation by using moving average. A function generator was used to generate sin wave, and our portable bio-signal acquisition system was used to record this signal. If our portable acquisition module was close to some electric instruments, the signal recorded from the acquisition module would be easily influenced by noise of 60 Hz power line. In the above figure of Fig. 2-23, it showed that the original sin wave had been contaminated by 60Hz power-line noise. After filtering by using moving average with 2-point moving window, we found moving average could effectively remove power-line noise, as shown in the below figure of Fig. 2-23.
_ 125
_ _ 2.08
60 60
Sample rate
Num of window= = =
Fig. 2- 23: Result of noise cancellation by using moving average [15]
D. UART Interface
In asynchronous mode, USART connected MSP430 to external systems via two external pins, URXD and UTXD. In UART mode, USART transmitted and received characters at a bit rate asynchronously to another device. Timing for each character
was based on the selected baud rate of USART. In our study, the transmitter and receiver used the same baud rate. For initializing UART, RX and TX had to be enable first, and then decided the baud rate of UART and disable SWRST. The required division factor N for determining baud rate was listed as followings:
BRCLK
N =baud rate
Here, BRCLK was 4 MHz, and baud rate was 115200 bit/s. After initializing UART, the micro-controller could transmit data filtered by moving average to BLUE TOOTH module via UART.
2.3.3.4 Wireless Transmission
Bluetooth is a wireless protocol utilizing short-range communication technology to facilitate data transmission over short distances from fixed and/or mobile devices.
The intent behind the development of Bluetooth was the creation of a single digital wireless protocol, capable of connecting multiple devices and overcoming issues arising from synchronization of these devices. In this study, Bluetooth module BM0203 was used. BM0203 is an integrated Bluetooth module to ease the design gap and uses CSR BuleCore4-External as the major Bluetooth chip. CSR BlueCore4-External is a single chip radio and baseband IC for Bluetooth 2.4GHz systems including enhanced data rates (EDR) to 3Mbps. It interfaces to 8Mbit of external Flash memory. When used with the CSR Bluetooth software stack, it provides a fully compliant Bluetooth system to v2.0 of the specification for data and voice communications. All hardware and device firmware of BM0203 is fully compliant with the Bluetooth v2.0 + EDR specification. Bluetooth operates at high frequency band to transmit wireless data, so it can be perfect worked by using a PCB antenna, as shown in Fig. 2-24.
Fig. 2- 24: PCB Blue Tooth antenna [16]
2.3.3.5 Power Management
Power Management circuit in our Mobile EEG acquisition circuitry includes two parts: one is power supply circuit, and the other is charging circuit.
A. Power Supply Circuit
Fig. 2- 25: Power supply circuit
Fig. 2- 26: LP3985 block diagram
In our portable bio-signal acquisition system, the operating voltage VCC was at 3V, and the virtual ground of analog circuit was at 1.5V. In order to provide stable 1.5V and 3V voltage, a regulator LP3985 (Fig. 2-26) was used to regulate battery voltage to 3V. LP3985 is a micro-power, 150mA low noise, and ultra low dropout CMOS voltage regulator. The maximum output current can support 550mA.
Furthermore, the turn-on time can reach 200μs. A voltage divider circuit was used to divide 3V voltage into 1.5V, and a unity amplifier constructed from AD8628 was used to provide a voltage buffer. The total power supply circuit was shown in Fig. 2-25.
B. Charging Circuit
The charging circuit BQ24010DRC had integrated power FET and current sensor for 1-A charging applications. The maximum charging current can arrive at 1A. The battery’s power would be detected automatically by charging circuit and switched to charging mode when battery’s power was not enough. BQ24010DRC also protected battery to avoid over charging or over driving [16]. The charging circuit was shown in Fig. 2-27.
Fig. 2- 27: Left- Charging circuit in our portable bio-signal acquisition system. Right- Block diagram of BQ24010DRC
2.3.4 Implementation of the EEG Acquisition Circuitry
The demand factors of our proposed EEG acquisition circuitry are lightweight, miniature, multi-channels, portable, wireless, and long-time monitoring. All of these are indeed implemented on a board, which is called “16-channel EEG device”. This device is only 50mm x 60mm large finally. Furthermore relative standard EEG measurement system like Neuroscan system, it improves convenience, practicality, and wide application. Real-time operation test verifies this circuit can be used about 10 hours. Hence, it is suitable for general long-term monitoring in daily life for most of users, even through for medical use and for scientific experiments. The outward appearance of implemented circuitry is showed by Fig. 2-27.
In design procedure, we found out the best parameters of circuit by MATLAB simulation. Moreover, the cut-off frequency of high-pass filter is 0.2Hz for physical device different from 0.1Hz we expected. Although a little error in design, the device measures EEG activity of interest is very enough. Besides the cut-off frequency, the other specifications of device are almost same as our design. As Table shown, the specification of 16-channel EEG device is listed. Table 6 shows Specification of implemented hardware system.
Fig. 2- 28: The outward appearance of implemented circuitry
Table 6: Specification of implemented hardware system
Type Mobile and Wireless EEG Acquisition Circuitry
Channel Number 16
Size 50 mm × 60 mm
Weight < 50 g
Power 3V
Power capacity about 10 hours
Battery rechargeable Lithium 3.7V 450mAh
Recharge port Mini USB
Power Supply Rejection Ratio 88 dB
Input impedance 10 GΩ
Input Common Mode Rejection Ratio 90 dB
Input signal range ± 272.7 uV compared to reference potential
Gain 5500
Bandwidth 0.2 Hz ~ 62.5Hz
ADC resolution 12 bits
Sampling rate 125 Hz
Communication interface Bluetooth 2.0
Transmission baud rate 115200 bit/s
2.3.5 EEG Display Program
EEG display program is designed for two purposes: (1) display record EEG data on the frame, (2) save record data to a file. This session explains the method of display program steps by steps.
2.3.5.1 Receive Package and Display A. Package Protocol
For display purpose, we expected the program received transmission digital data package continuously via Bluetooth. The data package format follows MSP430 encoding which explained in Table 5 of session 2.3.3.3 B. which is including one byte of header, one byte of data information, and 16 channel data. The program recognizes out package header through checking receiving data from byte to byte. On the other words, this program owns itself communication protocol, which once finding out common header, begins to decode certain package information and the following fix length of data. Table shows package protocol and function (2-1) shows decode thesis.
_ _
_ 2data value, _ 2data value
Sampling rate= Channel number= (2-1) Table 7: Header of package
Header Data information
f f Sampling rate Channel number Table 8: data information of package
data value 0 1 2 3 4 5 6 7 8 9 10
B. Display Digital Data to Analog Signal
Actual EEG signal= ×Power −Virtual GND potential
12
( _ 3) 0.5
2 data value
= × −
The program already defaults ADC resolution is 12 bits and isn’t adapted by user interface. As for the actual potential value is not influence the method of display.
After the program receive the 0-4096 range of data value, it just plots multi-channels data values in width-required frame, and shows the curve length according to sampling rate from package information and the number of display second from user interface.
2.3.5.2 Save Data as a File
Display program which was installed in the computer continuously receives digital data packages one by one via Bluetooth if it is started. In the beginning, user interface would ask user whether to save data as a file or not. If the save request is set, the program not only displays real-time converted analog signal but also saves received digital data as a TXT-format file simultaneously. In the TXT file, data package is saved as a row value once, and each channel data is saved as column value.
The first column means the first channel data, and the second column means the second channel ones, and so on. From left to right put each channel data in order and the final column means the 16-th channel data or event value if user needs.
Incidentally referring, the program record received event data with the rate of receiving. Program would get event file name and event input comport from user interface. So that every time the program receives one package, it synchronously checks certain input comport whether receiving event information or not. If event
value appears, the program recognizes it and save a value in final column behind 16 columns. However, if event value doesn’t appears, the program just save zero value in this event column. As following, Fig. 2-29 shows data appearance in TXT file.
a Package received once
Event column if needed
certain Channel data received by time
Left to right: Channel 1 to 16
Fig. 2- 29: TXT file contexts 2.3.5.3 User’s Guide
Fig. 2- 30: User interface with opening window
As Fig. 2-30 shown, the 1st row mentions certain Bluetooth module using now.
After opening this program, user can click “Refresh” button to search existing Bluetooth modules in finite distance. The 2nd row asks user that this program is going to display how much time for EEG real-time signal. The 3rd row asks user whether to save receiving data as a TXT file or not. If yes, please select a new file name. The 4th row asks user whether simultaneously receiving event value via a specified comport or not. The 5th row asks user whether to let program automatic checking the synchronization between event and channel data. After finished above request menu, user can click “Beginning” button to start this program. In addition to, to click “Quit”
button stops this ongoing program. Moreover, Fig. 2-31 shows the window once starting to receive EEG data.
Fig. 2- 31: Appearance of display Program within receiving process
2.4 Experiment: P300 and Oddball task
For system verification purpose, we need a standard cognitive experiment to make sure our proposed mobile and wireless system can measure tiny EEG activity even though Event-Related Potential (ERP). Thus, we introduce P300 and Oddball task in this session progressively.
2.4.1 P300
Event-related potential (ERP) refer to averaged EEG responses that are time-locked to more complex processing of stimuli; this technique is used in cognitive
Event-related potential (ERP) refer to averaged EEG responses that are time-locked to more complex processing of stimuli; this technique is used in cognitive