Some algorithms about bu¤er insertion problem have been proposed in [1] -[13].
Some of these methods regard the routing tree as an input, and bu¤er insertion algorithm intends to …nd a minimum delay for this routing tree. Because the input of the algorithm is a tree, we classify these algorithms as tree based bu¤er insertion algorithms. On the other hand, others simultaneous bulid a routing tree and perform bu¤er insertion during buliding routing trees. Although these kinds of approaches always lead to less delay than tree based bu¤er insertion algorithms, most of these algorithms need to spend more time on computing
a better result. Because the algorithms always create a graph for bu¤er insertion, we classify3 these algorithm as graph based bu¤er insertion algorithms. Here we introduce some of algorithms to show the di¤erences. Then we describe the DVB algorithm in [7] for dual-Vdd bu¤er insertion.
1.1.1 Treed base bu¤er insertion algorithms
Almost all the tree based algorithms are based on the algorithm proposed by van Ginneken[1]. van Ginneken’s algorithm deals with a routing tree which has multiple sinks and considers delay minimization only. It traverses a tree with a bottom up approach, and calculates delay with Elmore delay model during traversing a tree. For a tree withnfeasible bu¤er location and bu¤er library has only one bu¤er, there should be2nkinds of bu¤er tree.
But in van Ginneken’s algorithm, a prune technique is adopted such that there will be only nkinds of bu¤er tree and results in a time complexity of O(n2).
For 2 candidates (D1; C1); (D2; C2), where D states the accumlated delay and C states the accumlated load capacitance. IfD1 > D2 andC1 > C2, then(D1; C1)can be pruned.
After [1] has proposed, some algorithms intends to model the delay more accurately, such as [2]. Just like we demonstrate in Figure 1.2, [2] uses a -model and changes the load capacitance part as (Cn; R; Cf). Besides, some of the papers, such as [3] [4] [5], use either a balanced tree for storing the candidates or some aggressive pruning methods to make the algorithm even faster. Recently, [4] has improved the time complexity of a bu¤er insertion algorithm for a 2-pin net from O(n2) toO(nlogn); and toO(nlog2n) for multi-pin nets.
Because tree based algorithms regard routing tree as an input, the routing tree could not be changed during bu¤er insertion stage. And routing algorithms usually intends to …nd a Minumum Reclinear Steiner Tree (MRST) with minimum total wirelength. Therefore, if the routing tree has less feasible bu¤er locations, the bu¤er insertion algorithm can only improve the delay with these locations and will result in a poor delay while comparing with a graph based bu¤er insertion algorithm. Moreover, for a design with voltage island, if the MRST has none of feasible level converter location, the signal integrity can not be maintained and a large leakage current will be generated.
1.1.2 Graph based bu¤er insertion algorithms
For a 2-pin net, Lai et. al. proposes an elegant formulation of the maze routing with
Figure 1.2: [2] uses a -model instead of Elmore delay model and changes the load capacitance capin Van Ginneken’s original candidate as (Cn; R; Cf).
bu¤er insertion and wire sizing problem as a theoretic shortest path problem in [13]. But it still needs to consume much time on solving both maze routing and bu¤er insertion problem for a multiple sink net. Such as [11] [12], the maze routing with bu¤er insertion problem is converted into a graph collection problem. Various kinds of bu¤er routing tree subsets are pre-computed as a table. And the bu¤er routing tree is constructed through a dynamic programming approach with combining these subsets. Although the dynamic programming approaches consume less time, their algorithms still need much time on table computation.
J. Cong et. al. proposed a RMP (Recursively Merging and pruning) algorithm in [9].
Di¤erent from [11] [12], RMP simultaneously bulids the routing topology with considering the bu¤er insertion at the same time. RMP …rst creates a grid graph and solutions with factors of capacitance cap, required arrival time RAT, reachable sink set RE and buf for stating whether a bu¤er which had been placed is …lled into each node in the created graph.
With de…ning the formulation of solution propagation, various kind of solution could be generated during solution propagation. And each solution corresponds to a bu¤er routing tree. Therefore, various kinds of bu¤er routing tree is generated during computation, and the solutions at the source node states all the possible bu¤er trees.
1.1.3 DVB algorithm[7]
DVB algorithm which is the …rst in-depth study on applying dual Vdd bu¤ers to bu¤er insertion. With the restriction of low and high Vdd bu¤er’s ordering, their algorithm
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Figure 1.3: Refer from [7]. DVB algorithm states that to have the delay of case (b) larger than case (a), Cl must be larger than 0.5pF or an equivalent 9mm interconnect wire. Therefore, DVB algorithm restricts the bu¤ers ordering as case (b).
could neglect the level converter. Their algorithm is realized with both tree based and graph based method. And the experimental result shows that their algorithm reduces 18~26%
power consumption while comparing with using signal Vdd bu¤ers for bu¤er insertion. For DVB algorithm with graph based method, their algorithm is similiar to RMP algorithm.
And a time consuming problem is also occurred in their experiment result. That is their algorithm needs more than 20 minutes to perform both routing and bu¤er insertion for a net with 6 sink.
For Figure 1.3, which DVB algorithm states that to have the delay of case (b) larger than case (a), they …nd that Cl must be larger than 0.5pF or an equivalentlly a 9mm interconnect wire. Therefore, they restrict bu¤er’s ordering by only high Vdd bu¤ers could drive a low Vdd bu¤ers, and thus none of level converter is needed in their algorithm.
Alghough, this could reduce the complexity of a dual Vdd bu¤er insertion problem, but the assumption makes the algrotihm not realistical enough. First, for Figure 1.3 (b), if the sink device which Cl states is an high Vdd device, there will still need another level converter between the low Vddbu¤er and Cl, or else a large leakage current occurs at sink device. Under this assumption, we shall need an extra level converter in Figure 1.3(b). Second, if the DVB
algorithm is applied on a design with dual Vdd voltage, and their algorithm inserts both low and high Vdd bu¤ers anywhere in this design. It will make P/G line routing becomes a tough problem. Besides this, most dual Vdd design uses a voltage island ‡oorplan, and a level converter is widely used. Without considering the level converter, it makes the DVB algorithm becomes not realistical.