Prior Arts

The conventional RGB LED backlight module with conventional FCS algorithm, which utilizes many output components and DC-DC converters for providing the different output voltages, is illustrated in Figure 8 [14-16] because the forward voltages of red, green, and blue LED are different to each other from the characteristic of material. Therefore, the cost and footprint area is an drawback in the conventional LED backlight module system. In addition, when the modified FCS algorithm is applied in the LED backlight module, the LCD panel is divided into three sections to display different colors for the small-size panel of the notebooks.

There is only one of three colors or black frame appearing in each section of the LCD panel as shown in Figure 4. As a result, the LED driver with the modified FCS algorithm requires nine

DC-DC converters for driving the notebook’s panel with the advantages of much power saving on the current balance circuit.

Gate Driver

Figure 8. Conventional RGB LED backlight with three DC-DC converters.

In general, the six series LED are applied in the LED backlight module of notebook, and thus LED backlight module would supply 16 V and 21 V for 6 series R-LED and G- or B- LEDs, respectively. Since the bandwidth of the DC-DC converter is limited to the low-pass filter which is composed of the inductor and capacitor, the fast output voltage tracking between 16V and 21V is very difficult in the conventional DC-DC boost converters.

Therefore, the LED with different colors require different supplying voltages [13]. That is, the implementation of the LED driver of the modified FCS algorithm needs nine DC-DC converters for driving the notebook’s panel with the advantages of much power saving on the constant current regulator.

The conventional voltage-mode PWM buck converter is depicted in Figure 9 (a). The power stage is composed of power transistors MP, MN, and low-pass filter which is formed by inductor L and capacitor C_L. The error amplifier with compensated resistor and capacitor

compare the reference voltage Vref with feedback voltage Vfb to generate the error signal Vc for determining the duty cycle of PWM signal V_PWM. In addition, the duty cycle of continuous-conduction mode (CCM) buck converter has a relationship with output voltage and input voltage (V_out/V_in). Thus, the conversion equation is given by

out c L

where VH and VL are upper and lower bounds of the ramp signal VRamp. When the reference voltage V_ref is changed, the output voltage V_out would be varied by changing the duty cycle of PWM signal VPWM as shown in Figure 9 (b). Since a large compensator capacitor is utilized to provide the dominant-pole for compensating the power system. The signal V_c would slowly raise to the steady state and the tracking response of output voltage is slow.

This thesis proposes a DC-DC converter with fast reference tracking to provide the output voltage for overcoming the different color of series-LEDs. The new implementation of the RGB backlight module is depicted in Figure 10 for achieving low cost and high efficiency.

It is obvious that only one DC-DC converters are employed. The hardware cost and volume can be effectively reduced.

Several topologies and control techniques have been proposed to fast reference tracking output voltage. The reference tracking technique in [17] proposes the end-point prediction (EPP) for voltage-mode PWM buck regulator as shown in Figure 11. A voltage adder is required to sum the error signal Vc1 and reference voltage Vref to form the Vc2 and generate the PWM signal. In addition, this technique design that the upper bound of ramp signal V_H is equal to

H in L

V = × b V + V

where b is the ratio of feedback resistor (R_F1 and R_F2). Therefore, the information of reference voltage and

input voltage is acquired to generate the PWM signal for improving the transient response of reference tracking.

However, the transient response of up-tracking still be clamped by the compensation capacitor.

LOAD

(a)

(b)

Figure 9. (a)Conventional voltage-mode PWM buck converter. (b) The transient duty cycle of PWM signal VPWM at reference tracking.

Gate Driver

Figure 10. A high efficiency RGB LED backlight with one DC-DC converter for implementation of conventional FCS algorithm.

r.

Figure 11. Voltage-mode PWM buck regulator with end-point prediction (EPP) technique Another reference tracking technique in [18] is utilized by the hysteretic comparator and limiting current control to improve the transient response of reference tracking as shown in Figure 12.

RF1

Figure 12. System architecture of hysteresis buck converter with current limit control for fast reference tracking.

The up-tracking process can be divided into the following three phases as shown in Figure 13.

1. Inductor current ramp up phase (T1): During the period T1, the average inductor current ramps up from the output (load) current to the maximum allowable current with full duty cycle. The Hysteresis buck converter can generate the full duty cycle. Thus, the inductor current can fast ramp up to maximum current.

2. Maximum current charging phase (T₂): During the period T₂, the inductor current switches between two predefined levels such that the average inductor current is kept at I_max. The maximum current is charging the output capacitor at full speed until the output voltage reaches the predefined value Vout2.

3. Inductor current ramp down phase (T3): When the output voltage reaches the predefined value, the inductor current is then decreased to the new output load current.

The load transient time depends on the control methodology of the converter. The total up-tracking time is T₁+ T₂+ T₃.

The down-tracking process also can be divided into the following three phases as shown in Figure 13.

1. Inductor current ramp down phase (T4): During the period T₄, the average inductor current ramps down from the load current to the minimum current level which is close to zero. The Hysteresis buck converter would not turn on the Power MOSFET M_P. Thus, the inductor current can fast ramp down to minimum current.

2. Maximum current charging phase (T5): During the period T5, the output voltage is discharge by the load current and the down-tracking speed is dominated by the load resistor.

3. Inductor current ramp up phase (T6): When the output voltage reaches the predefined value, the inductor current is then increased to the new output load current. The total down-tracking time is T4+ T5+ T6.

Figure 13. The up- and down- reference tracking process.