Proposed Constant Current Regulator

In generally, the light luminance of LED is controlled by the driving current [8-9].

Therefore, the LED backlight module utilizes the current balance circuit to control the amount of driving current for regulating the constant light luminance of LEDs. The current balance circuit composed of three current regulators is controlled by the signals V_refI, V_clR, V_clG, and VclB from the FPGA as shown in Figure 36. The current regulator utilizes the operation amplifier (OP) and the resistor R to operate as a voltage-to-current converter. Furthermore, the input signals VrefI, which is converted by the digital-to-analog (D/A) converter in the FPGA, determines the value of the driving current in the series connection LEDs. Thus, the voltage

signal VrefI is used to generate the constant current. After the two current mirrors pairs, which are (M_P1, M_P2), (M_N1 - M_N5), the current I_LEDR can be used to drive the 4 brunches of LED and thus the variation of drain-source voltage of these transistors (MN1 - MN5) will not have large influence on the value of current I_LEDR. Moreover, the FPGA uses the three signals V_clR, V_clG, and VclB to turn on/off the R-, G-, and B- LED for achieving the FCS algorithm as shown in Figure 3. Using the R-LED as an example, the transistor M_C1 operates in the cut-off region when the signal VclR is pulled to high level. Thus, the current ILEDR is equal to zero and unable to drive the R-LEDs. In other words, when the V_clR is pulled to low and the transistor M_SR operates in cut-off region, the voltage-to-current converter will start to convert the reference voltage V_refI to current signal I_LEDR for driving the R-LEDs. Therefore, the current balance circuit is used to generate the constant current to drive the LED for constant light luminance.

The FCS algorithm can be achieved by turning on/off the LED according the values of signals VclR, VclG, and VclB. When the current regulator is activated to convert the current, the transistors (M_N1 - M_N5) operated in the saturation region generally stress the drain-source voltage for reducing the power consumption.

Figure 36. The constant current regulator.

Chapter 4

The Proposed Buck-Store

Boost-Restore (BSBR) Technique

4.1 The Buck-Store and Boost-Restore Technique

The output voltage for driving the series-connected R-LED is smaller than that for driving G-LED and B-LEDs. Thus, the output voltage of the boost DC-DC converter needs to switch between two output voltages, which are 9.3V and 12.4V. In order to switch the output voltage between the two values, the reference voltage integrated in the chip needs to switch between 0.92V and 1.22V. The proposal BSBR technique is applied to the boost DC-DC converter for achieving fast and efficient reference tracking performance. The function blocks and waveforms are illustrated inFigure 37 (a). The BSBR technique delivers extra charge and stores it on the capacitor C_BSBR once the output voltage V_out expresses much voltage stress on the constant current generator. As a result, the reference down tracking is sped up and more charge is saved to achieve high efficiency compared to the conventional structure [40]. In other words, the LED backlight module can get higher efficiency due to low voltage headroom of the constant current generator. Furthermore, the BSBR technique recycles the stored charge back to the capacitor CLoad when the FCS technique changes the color of LED from red to green or blue. Therefore, the BSBR technique can efficiently recycle extra charge [33] and enhance the transient response of reference tracking. When the BSBR technique is enabled to store or restore extra charge, the boost converter is disabled to prevent the two

power stages from being influenced by each other. That is, the boost converter is shutdown when the BSBR technique efficiently transfers the charge between the two capacitors C_Load and CBSBR. The architecture of the BSBR technique contains one BSBR power stage and one BSBR controller. The input node of the BSBR power stage is connected to the output node of the boost DC-DC converter. The output node of the BSBR power stage is named as VBSBR. There is a large capacitor C_BSBR connected at the node V_BSBR in order to store extra charge from the output node of the boost DC-DC converter. The stored charge can be utilized to pull the voltage V_out back to a higher level or to drive another sub-block in the LCD system.

Furthermore, the BSBR power stage can regulate the steady output voltage for the sub-block of LCD system when the digital signal EN is triggered from high to low level.

The signal E_ref generated by the LCD timing control system can indicate the display color is. That is, the high- or low-level of this signal represent the output voltage of the boost converter as high- or low-supplying voltage, respectively. The transition of the signal E_ref from low to high indicates the output voltage Vout needs to be raised to high-supplying voltage level. The stored charge should be restored back to the output voltage V_out. On other hand, the transition of the signal Eref from high to low indicates the output voltage Vout needs to be reduced to the low-supplying voltage level. As a result, extra charge should be stored in the BSBR capacitor CBSBR. The signal Eref can be used to determine whether it is the buck-store or boost-restore operation. The signal E_BSBR is a signal to coordinate the two power stages, which are the boost converter and the BSBR power stage, in order to correctly control the two closed loops. The digital signal V_PWM indicates the current comparator output of the PWM generator and it reflects the output voltage information. The signal Vsen is the sensing information of the inductor L current. The signals V_P and V_N indicate the sensing information of the inductor LBSBR current.

PWM Generator

Figure 37. (a)The proposed boost converter with BSBR technique and the timing diagram of the voltage V_BSBR with/without load current requested from another sub-block in the LCD driving system. The BSBR power stage can be simplified as (b) buck-store operation and (c) boost-restore operation.

4.1.1 Architecture of the BSBR Power Stage and Controller

The BSBR technique is composed of the buck-store and boost-restore operations. Extra charge is transferred from the output capacitor C_Load to the capacitor C_BSBR by the buck-store

operation and restored from CBSBR back to CLoad by the boost operation. The reference down-tracking utilizes the buck-store operation to rapidly reduce the output voltage of the boost converter from the high- to low-supplying voltage level. The BSBR controller is enabled to turn on the P-type power transistor M_BP1 first to increase the inductor current. The duty cycle is determined by the closed loop of the BSBR controller. After turning off the MBP1, the BSBR controller turns on the N-type power transistor M_BN1 to decrease the inductor current. In addition, the current-sensing circuit of p-type power transistor MBP1 is utilized to set the maximum delivering current and the current sensing circuit of n-type power transistor MBN1 is used as the zero-current-detector (ZCD) mechanism for avoiding the reversal inductor current releasing to ground. The procedure that the output voltage V_out delivers charge to the capacitor CBSBR for storing extra charge is similar to the operation of a buck converter [28]

that steps down the output voltage V_out to the voltage V_BSBR and the BSBR power stage can be simplified as the buck-store operation illustrated in Figure 37(b). For the reference mechanism, respectively. Thus, VBSBR steps up the output voltage Vout through the operation of the boost converter as shown inFigure 37(c). Therefore, the BSBR technique can rapidly pull down the output voltage Vout from 12.4V to 9.3V and raise Vout back to 12.4V from 9.3V when driving the G-LED and B-LEDs. Furthermore, the BSBR power stage is also designed as a switching converter to regulate a steady voltage at node VBSBR by the simple PFM control when the BSBR technique is disabled.

4.1.2 The Tracking Algorithm of the BSBR

Technique

The BSBR power stage is controlled by the three operation loops (buck-store operation, boost-restore operation, and PFM) to pull down/up the output voltage or regulate the BSBR voltage V_BSBR. Therefore, the tracking algorithm of the BSBR technique is necessary to choose the appropriate operation loops for avoiding incorrect switching sequences. The algorithm is described by the flowchart inFigure 38 starting from the transition of the signal E_ref from high to low or low to high. For the buck-store operation, this algorithm estimates the values of the voltage V_BSBR and the PWM signal V_PWM to decide whether the charge needs to store in the BSBR capacitor CBSBR or not. When all of the controller signals are in the correct state, the BSBR power stage increases the inductor current by means of energy delivering from the output voltage Vout. Hence, the charge is transferred to the capacitor CBSBR every switching cycle. The boost converter is disabled in the meantime in order not to disturb the closed loop of the BSBR power stage.

When the output voltage Vout approaches to the low-supplying voltage (VLow) or the voltage V_BSBR exceeds the predefined voltage V_max, the algorithm ends the buck-store operation loop and the BSBR power stage is controlled by the PFM operation. In succession, the boost converter is enabled to regulate the output voltage V_out. Consequently, the voltage VBSBR is increased due to extra charge stored on the BSBR capacitor CBSBR.

For reference up-tracking response, the algorithm will enable the boost-restore operation loop if the signals V_BSBR and V_PWM are set by the correct values. The stored charge is transferred from the BSBR capacitor CBSBR to the output load capacitor CLoad and thereby steps up the output voltage. Until the voltage V_BSBR is lower than the predefined minimum voltage Vmin or the output voltage Vout approaches to the high-supplying voltage VHigh, the boost-store operation loop is ended and then the output voltage will be regulated by the boost

converter. Furthermore, the algorithm also determines the function of current-sensing circuit in the different power transistors M_BN1 and M_BP1 as ZCD or current limiting mechanism.

Figure 38. The flowchart of the BSBR tracking algorithm.

When the BSBR technique is disabled by the tracking algorithm, the voltage VBSBR is also designed to supply a regulated voltage by PFM operation for another sub-block in the LCD system. Therefore, this voltage should be kept constant to prevent the sub-block in this system from being affected by the voltage variation [8-9]. Therefore, the C_BSBR (10µF) is designed larger than the Cload (1µF) and the voltage VBSBR only rises one-tenth of the output voltage due to the law of the charge conservation (Q ≡ C×V). In this design, the V_BSBR is used to turn on white LEDs. Furthermore, the maximum current supplied by the PFM operation of BSBR controller is about 100mA in this design.

4.1.3 The Efficiency of Charge Transition

The BSBR technique is utilized to transfer extra charge between the capacitors C_Load and CBSBR. The extra charge energy can be expressed as (38).

1

2

W = C ∆ V

The ∆V is the different voltage between high- and low- supplying voltage. During the transforming procedure, part of the energy is consumed by the equivalent on-resistance of power transistors (M_BN1 and M_BP1). The energy stored on the capacitor is also wasted on the feedback resistors (RBF1 and RBF2) during the transition period depending on the FCS frequency. Therefore, the transforming efficiency can be approximated by (39).

_ feedback resistor as shown in (40) and (41), respectively.

2

R_{ds_on} is the equivalent on-resistance of power transistors. I_avg is the average transforming current during up- or down-reference tracking, CLoad is the output capacitance, TFCS is the period of the FCS technique. T_up and T_down are the transient time of up- and down-reference tracking, respectively. According to (40), small Rds_on and Iavg can reduce the energy

consumption of WR_on. However, small Rds_on leads to larger chip area due to large power transistors and thus the value of R_{ds_on} can be decreased depending on the chip area limitation.

On the other hand, small average current Iavg results in longer transient time. Thus, in this proposed design, the maximum transforming current is designed to about 0.5A which is smaller than conventional current-limiting mechanism. In addition, according to (41), large feedback resistors (R_BF1 and R_BF2) and small T_FCS can reduce the value of energy W_VBSBR. However, the period of TFCS depends on the speed of liquid crystal rotation. As a result, a large resistor is chosen to improve the transforming efficiency.

4.2 The Circuit Implementation

4.2.1 The Implementation of the Proposed BSBR Controller

The proposed BSBR controller and its control signal timing diagram are shown in Figure 39. Basically, the operation mode of BSBR power stage can be divided into two parts, which are the PFM operation and the BSBR technique. The BSBR enable circuit is designed to implement the BSBR tracking algorithm as shown in Figure 40. This algorithm utilizes these signals V_fbB and V_PWM to appraise whether the system is suitable for transforming extra charge or not. Therefore, when these two conditions are suitable to enable the BSBR technique, this circuit will generate the signal E_BSBR to enable or disable the boost converter and the PFM operation of BSBR controller. Moreover, the signals Clk and EBSBR produce the signal ClkBSBR

to increase the inductor current of the BSBR power stage for transferring the energy at a fixed frequency. Furthermore, the signal selector utilizes these two signals EBSBR and Eref to determine the operation mode and disable either the ZCD_PMOS or ZCD_NMOS mechanism for avoid incorrect switching. Therefore, this proposed BSBR technique uses these digital signals to determine the function of the BSBR power stage as buck-store (down-reference tracking)

or boost-restore (up-reference tracking) operation. Moreover, VN and VP are sensing signals of power transistor current (M_BN1 and M_BP1). The BSBR technique uses these two signals V_N and VP to decide the maximum delivering current. In normal condition, the voltage VBSBR is regulated by the PFM controller. When the signal V_BSBR is lower than 3.8V, the PFM controller turns on the power transistor MBP1 at a fixed duty to provide energy for regulating the voltage V_BSBR. As a result, the PFM operation can regulate the voltage V_BSBR according to load current condition. On the other hand, the BSBR technique is utilized to transfer the charge between the two capacitors C_Load and C_BSBR. The signal E_ref generated by the timing control system defines output voltage level of boost converter as described in Section III.

Additionally, when the BSBR power stage is controlled by the BSBR technique, the PFM operation will be disabled until the BSBR tracking algorithm ends the loop.

Figure 39. The implementation of the proposed BSBR controller and the control signal timing diagram.

Figure 40. The function block of proposed BSBR Enable circuit.

For the buck-store (down-reference tracking) case, the current-sensing circuits of power transistors MBP1 and MBN1 illustrated in Figure 37(a) are utilized to act as current limiting and ZCD mechanism, respectively. The transistor M_BP1 is turned on and then the inductor current is increased to ramp up. The transistor MBP1 is turned off when the inductor current exceeds the predefined maximum current. After the dead-time period, the transistor M_BN1 is turned on to decrease the inductor current. In succession, the BSBR power stage undergoes the switching activities, turning on and off the transistors M_BP1 and M_NB1 alternately. Hence, extra charge can be safely and quickly transferred to the BSBR capacitor CBSBR. When the signal V_PWM transits from low to high or the V_BSBR is higher than the V_max, the buck-store algorithm loop is ended. The signal ClkBSBR is disabled and the inductor current will not be increased to ramp up anymore. The remaining inductor current is decreased through the power transistor MBN1 to the capacitor. When the reversal of the inductor current happens, the ZCDNMOS is used to turn off the transistor M_BN1 for alleviating the problem of the reverse inductor current flowing to ground. On the contrary, the function of the ZCDPMOS is disabled to avoid the error digital control signal. For the reference up-tracking case, the boost-restore operation is

selected by the BSBR Enable circuit according to the BSBR algorithm. At first, the BSBR turns on the power transistor M_BN1 to increase the inductor and then transfers extra charge to the capacitor CLoad. Hence, the boost-restore technique senses the n-type power transistor M_BN1 to decide the discharging time and uses the ZCD_PMOS to alleviate the boost converter to provide the unnecessary energy to the capacitor CBSBR. When the signal VPWM is triggered to low or the V_BSBR is lower than the voltage V_min, the boost-restore operation is completed.

4.2.2 The PWM Generator of the Boost Converter

The PWM generator is the main circuit of the boost converter as shown in Figure 41.

The LED backlight driver uses the boost converter to provide enough voltage and current to overcome the forward voltage of series-LEDs. This PWM generator translates all signals to current domain [27] in order to compensate the system without any large external compensation capacitors [34], [41]. The Gm amplifier [29] with high bandwidth characteristic is used to convert the voltage difference between V_fb and V_ref to a correct current signal according to the output voltage condition. Therefore, the response of this converter can result in fast load/line transient [32] and reference tracking.

Since the LED driver turns on the series-LED after the liquid crystal being rotated to the correct position according to the image data as discussed in Section I, the PWM generator needn’t increase the inductor current every switching period. Hence, when the timing control system turns on the LED driver and leads to Vfb drop below the reference voltage VH or VL, the signal V_PWM instead of the clock signal enables the pulse control circuit to turn on the power transistor MN1 as described in Figure 37(a).

The reset signal of the PWM signal is determined by three loops. In the normal condition, the current-domain control forms the linear loop composed of G_m amplifier and current comparator to determine the duty ratio. The peak current control uses the current information

of MN1 to turn off the MN1 preventing the chip from being damaged by large current. Besides, the PWM system applies the maximum duty loop to ensure that the inductor current is transferred to the output during a period. In this proposal, the maximum duty is set as high as 80%. Hence, this three control loops can effectively regulate the boost converter. During the BSBR technique operation, the digital signal EBSBR transits to high and prevents the boost converter from being enabled by the pulse signal of the pulse control. There are two conditions that decide the end of the buck-store algorithm loop.

of MN1 to turn off the MN1 preventing the chip from being damaged by large current. Besides, the PWM system applies the maximum duty loop to ensure that the inductor current is transferred to the output during a period. In this proposal, the maximum duty is set as high as 80%. Hence, this three control loops can effectively regulate the boost converter. During the BSBR technique operation, the digital signal EBSBR transits to high and prevents the boost converter from being enabled by the pulse signal of the pulse control. There are two conditions that decide the end of the buck-store algorithm loop.