Chapter 2 Background Description
2.4 Problem Emerge
When we check the M1 lithography on the qualification lot of wafers after the etching step in ET2 etcher, the alignment and overlay different from ET1 etcher is highlighted. The alignment offset from ET2 wafers to scanner for minimizing the overlay error was different from that of the ET1 wafers. It means that the alignment mark shape of ET2 lot may be
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-different from that of ET1, therefore, the detected results from scanner alignment system show some bias. In other words, the M1 overlay baseline of ET2 lots is different from that of ET1 lots. It won’t be manufacturing unfriendly if M1 overlay baseline is still stable for ET2 lots. All we need to do is just to separate the M1 exposure recipe and the feedback system for calculating its alignment offset for ET2 lots in M1 lithography.
In order to verify a stable C1 etching yield from ET2, we start to implement the C1 etching process for wafers by ET2, and also set up the M1 exposure recipe and the feedback system separately for ET2 lots so as to make ET1 and ET2 lots alignment offset not interfere each other. Even so, the ET2 lots still show poor overlay performance and high rework rate.
From overlay data analysis we found that the large overlay baseline variation is the main reason for poor overlay performance. In other words, each lot needs to send a wafer ahead for overlay measurement to get adjusted alignment offset for other wafers, then we can get acceptable overlay performance and less rework rate.
To compare the M1 overlay performance for C1 etching tool ET1 and ET2, the overlay error of ET2 lots is significantly worse than ET1, and the overlay baseline shows a larger variation especially in wafer rotation item for ET2 lots (Figure 2-6). We assume that this abnormal result is attributed to the combination effect from CMP and C1 etching in ET2 tool.
In order to find possible abnormal issues, we study the process flow (Table 2-1) from the film deposition of Contact-1 to the Metal-1 lithography. The variation of alignment mark after the W-CMP and the oxide touch-up CMP may be mainly attributed to the wafer rotation direction. Actually, C1 film deposition, C1 etching, W-CMP, oxide touch-up CMP, and M1 film deposition all possibly affect the alignment mark final shape. From all above, the hypothesis for M1 overlay poor performance on ET2 lots are:
1. The C1 etching process condition in ET2 tool may make the alignment mark shape different from that of ET1 tool.
2. CMP rotary effect combining with the C1 etching in ET2 tool.
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-Chapter 3 Experiment 3.1 Introduction of Experiments Plan
Base on the discussion in Chapter 2, we set up CMP and Etching experiments as follows:
CMP experiments:
1. To correlate the W-CMP and oxide touch-up CMP rotary combination to overlay baseline with lots spilt.
2. To correlate W-CMP over polish time to overlay baseline with lot spilt.
3. To correlate oxide touch-up CMP over polish time to overlay baseline with lot spilt.
Etching experiments:
1. By using the cross section SEM to compare the mark difference between ET1 and ET2 C1 etching wafer.
2. To correlate ET2 over etching to overlay baseline with lots spilt.
3.2 CMP Experiments and Results
3.2.1 CMP rotary direction experiments
To correlate the W-CMP and oxide touch-up CMP rotary combination to overlay baseline, we prepare 5 lots wafers with same spilt to confirm the repeatability of experimental results.
Each lot was spilt into three conditions; the rotary direction combination was CCW/CCW, CCW/CW, and CW/CCW for W-CMP and oxide touch-up CMP, respectively (Table 3-1). The wafer rotation baseline results are shown in Figure 3-1:
Lot 1: The distribution of the wafer rotation baseline is divided into two groups, where
spilt 1 as one group and spilt 2/3 as another group. It shows that both two CMP steps affect the wafer rotation baseline.
Lot 2: The distribution of wafer rotation baseline is divided into three groups that match the distribution of three spilt conditions. It shows that both two CMP steps affect the wafer rotation baseline. Furthermore, the effect induced by W-CMP is more significant than that induced by oxide touch-up CMP.
Lot 3/4/5: These three lots show similar results that are quite different from lot 1 and lot2.The overlay offset wafer rotation item become 2 groups, where spilt 1/2 as one group, and split 3 as another group. This result matches with the distribution of W-CMP rotary direction. From these 3 lots, it shows that W-CMP affects wafer rotation baseline but oxide touch-up CMP doesn’t.
Experimental results from these five lots are divided into three groups (Figure 3-2). We conclude as follows:
1. Either W-CMP or oxide touch-up CMP may possibly affect the wafer rotation baseline.
2. Contact-1 etching step is the main factor affecting the overlay baseline and results in the inconsistence between the rotary direction and the overlay baseline.
There are two polish heads for each CMP tool (Figure 3-3), In order to keep the long term leveling of CMP system, the rotary direction of these two polish heads usually is designed in counter direction, respectively, to cancel rotary momentum. In order to avoid the lithography overlay error induced by polish heads interlace on the same CMP system, wafers in the same lot are put on the same polish head of CMP tool. However, from the experimental
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-results, rotation in counter direction for polish heads on the same CMP system has seriously drifted the overlay baseline. Therefore, it is necessary to keep these two polish heads in same rotary direction to reduce the CMP induced lithography overlay error.
The experimental result of CMP rotary for these five lots are shown in Figure 3-2, the wafer rotation baseline of all wafers ranges around 1.6urad, within the same spilt the range is around 0.6urad. However, this drift is still much higher comparing with ET1 lots that show less than 0.2urad level. To keep the same CMP rotary direction for polish heads is helpful but still not good enough for Metal-1 overlay error control. Because only Contact-1 etching tool is changed during the whole experiment, it is reasonably believed that Contact-1 etching process from ET2 is not optimized. In additional, the subsequent CMP rotary effect further reveals these abnormal results.
3.2.2 W-CMP Over-Polish Experiments and Results
Since the over-polish time may influence the mark shape, we prepare 1 lot wafers for W-CMP process. The overlay baseline vs. the over polish time is listed in Table 3-2. Results are shown in Figure 3-4.
Regular over polish time is 15sec for W-CMP step. However, experimental results show that the over polish time between 11sec to 23sec does not affect the wafer rotation baseline.
3.2.3 Oxide touch-up CMP Over-Polish Experiments and Results
The over-polish time experiment for oxide touch-up CMP is also implemented. We prepare 1 lot wafers for oxide touch-up CMP to correlate the over-polish time with the overlay baseline. The spilt condition is listed in Table 3-3 and the result is shown in Figure 3-5.If the oxide touch-up CMP removal thickness is reduced from 350A (POR remove target)
to 230A, the wafer rotation baseline slightly changes from 0.6urad to 0.73urad.In addition, as the removal thickness is increased from 350A to 480A, the wafer rotation baseline changes from 0.6 to 0.46urad .We also study the wafer X/Y scaling change for this experiment, as shown in Figure 3-5, the 230A/ 480A spilt wafers are in one group, the mean valve is about 0.2ppm which is lager than 350A spilt wafers. From above results, the oxide touch-up CMP will slightly influence the mean valve of overlay baseline. Regarding the range of those overlay baseline items for each spilt, it is not necessary to change the removal thickness of oxide touch-up CMP.
From Figure 3-5, we also observed the interlacing variation in wafer scaling X and Y baseline. To review Contact-1 to Metal-1 process again (Table 2-1), it is believed that wafers in the same lot deposited with dielectric film or Metal-1 film in interlacing chambers induced the interlacing variation in wafer scaling X and Y baseline. The deposited film thickness also influence lithography overlay control if the overall process integration is not optimized.
However, it seems that these interlacing phenomena do not affect the overlay baseline very much. Therefore, we assume that the Contact-1 etching step with different tools plays a major role in the variation of overlay baseline.
3.2.4 The Overlay Performance after Unify CMP Rotary Direction
In order to reveal the main reason causing the variation in overlay baseline, we adjust the rotation of two polish heads in the same direction for each CMP system to eliminate the count direction effect.After modification in rotation direction, as shown in Figure 3-6, the overlay error and overlay baseline variation range of ET2 lots show some improvement but still not good as ET1 lots does. In order to further identify ET2 etcher induced overlay error and overlay baseline variation, wafers are etched by ET1 or ET2 and subsequently by CMP tool with
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-count rotation direction or same rotation direction are prepared. In addition, two separate lithography scanner tool is also used to study the overlay performance for each combination.
Results are showed in Figure 3-7 and Table 3-4, respectively.
From the results in Figure 3-7 and Table 3-4, we can get following conclusions:
1. The overlay error performance of ET1 lots in PH1 and PH2 scanner shows no difference and is irrelevant to CMP rotation direction.
2. The overlay error performance of ET2 lots is much worse than that of ET1 lots in both PH1 and PH2 scanner where the CMP rotary direction period is not fixed.
3. The overlay error performance and wafer rotation baseline variation of ET2 lots are much improved after the CMP rotary direction is fixed.
4. The overlay error performance of ET2 lots in PH2 scanner is better than that in PH1 under the same CMP rotary direction, and its performance is even close to ET1 lot
remarkable.
5. The overlay error performance of ET2 lots in PH2 scanner is better than that in PH1 scanner where the CMP rotary direction is not fixed. Especially, the variation of wafer rotation baseline is around 2 times larger.
6. The overlay error performance of ET1 lots no overused difference after unifying CMP rotary direction, but the variation of wafer rotation baseline is somewhat improved.
3.2.5 Discussion for Scanner Sensitivity on ET2 etcher lots
This phenomenon really interesting, two scanners didn’t show performance difference in ET1 lots with the same or the count CMP rotary direction, but it show degraded performance difference for ET2 lot with the same or the count CMP rotary direction.
The alignment accuracy of scanner can be adversely affected by 3 factors [09] [13][14],
generally knowing as:
(A) TIS (Tool Induced Shift):
This error is attributable to FIA mainly in 2 ways:
--The COMA aberration in the FIA Microscope and/or
--The Aperture stop eccentricity for optical axis in the FIA microscope.
(B) WIS (wafer Induced Shift):
This error is attributable to the deformation of alignment marks on the wafer. These deformations may be different in each shot or wafer or lot.
(C) Interaction between TIS and WIS (TISxWIS). It is not possible to eliminate this error.
The reduction of TIS and WIS, respectively, can significantly reduce this error and have it become negligible.
In this study, ET2 lots show worse mark deformation and then make their WIS be worse than ET1 lots. TIS of PH1 scanner may be worse than that of PH2 scanner, then further make TIS and TISxWIS of PH1 scanner be worse than those of PH2 scanner. Therefore, the overlay performance becomes worse than that of PH2 scanner for ET2 lots. For ET1 lots, its WIS is better than that of ET2 lots, although the TIS of PH1 scanner is worse than that of PH2
scanner. Obviously, the TIS and TISxWIS are not large enough to make PH1 and PH2 scanner show overlay performance difference.
Both TIS and WIS are needed to be improved, but it is difficult to reduce the TIS of alignment system. It is necessary to optimize the process to improve WIS of ET2.
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-3.3 Etching Experiments and Results
3.3.1 Alignment Mark cross section SEM study
The overlay performance of ET2 lots is not good as that of ET1 lots. In order to check the alignment mark, cross-section SEM is applied. The alignment mark obtained from cross-section SEM analysis for ET1 and ET2 is shown in Figure 3-8.
It is shown that the alignment mark depth of ET2 wafers was shallower than that of ET1 wafers around 1000A. This difference induces a larger overlay baseline variation for ET2 wafers because the scanner alignment system is not sensitive enough to detect the wafer deformation properly with shallower alignment marks.
To compare the scanner alignment signal, it also reveals the same information (Figure 3-9). The alignment mark 1 was used for Metal-1 lithography alignment. The alignment signal strength of ET2 was weaker than that of ET1 because the alignment marks of ET2 is
shallower. As we compare these two alignment mark signals (Figure 3-10), we find that the signal strength of ET2 is weaker than that of ET1 for smaller features.
To increase the ET2 over-etching time for Contact-1 etching can make alignment mark become deeper and then improve the Metal-1 overlay for ET2 lots.
3.3.2 ET2 Etcher Over-Etching Experiments and Results
From the cross-section SEM result in Figure 3-8, we prepare two lots of wafers with proper over etching in ET2 etcher to get the same alignment mark depth of ET1, then check the correlation with overlay baseline, yield qualification, and electrical characterization.
The etching conditions for two qualification lots are shown in Table 3-5 and Table 3-6,
both two lots have same total 4 split conditions. The control group is processed in ET1 and the other three experimental groups are processed in ET2 with different etching time. The etching time for all three experimental conditions is designed to get same etching depth as ET1 does. The etching recipe of ET2 is a two step etching process with different gases and pressures. To increase the over-etching time of step 1 etching (Oxide etching) or step 2 etching (SiON etching) can both get deeper alignment mark depth. We prepare three different conditions to get same depth as ET1 does.
Three experimental conditions in ET2 are
Step1:80sec/ Step2:30sec, Step1:85sec/Step2:15sec, and Step1:90sec/Step2:0sec.
The original etching condition of ET2 was Step1:68sec/Step2:30sec.
The overlay baseline result of over-etching experiments are shown in Figure 3-11 and Figure 3-12, it shows that the overlay baseline of all three experimental splits is really closed to that of control spilt. It means that three experimental conditions can make mark depth be similar to that of ET1 wafers. From experimental results we can expect that over-etching can further improve the overlay performance under the same CMP rotary direction.
3.3.3 The Overlay Performance after Implement over etching on ET2
After this 2 lots pass the yield qualification and electrical characterizations, we set up step 1 etching：80sec ⁄ step 2 etching：30sec as the new condition for ET2 C1 etching and then start release lots to trace M1 overlay performance. Where the CMP rotary direction is fixed.
The overlay performance with the new ET2 recipe is shown in Fig 3-13 and Table 3-7. We can get following conclusions:
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-1. The overlay performance and the variation of wafer rotation baseline for ET2 lots with over etching have been further improved. Where the CMP rotary direction is fixed.
2. The overlay performance and the variation of wafer rotation baseline for ET2 lots with over etching are similar to those of ET1 lot.
3. The overlay performance and the variation of wafer rotation baseline for ET2 lots with a new over etching recipe show no difference on PH1 and PH2 scanner.
After Contact-1 over etching recipe on ET2 etcher is applied, the overlay performance of ET2 lots is as good as ET1 etcher lots.
3.4 CMP v.s. Etching Interaction Experiments and Results
3.4.1 Discussion for CMP v.s. Etching Interaction on ET2 lot
In this study, it was found that the overlay performance of ET2 lots is not as good as ET1 lots. Therefore, we fix the CMP rotary direction and increase the over etching of ET2 etcher to solve ET2 etcher induced problems. It also shows that CMP rotation direction does not affect the overlay performance for ET1 etcher lots,
therefore, it is believed that to make ET2 lots get proper alignment mark depth by over etching is more important than to fix the CMP rotary direction.
3.4.2 Experiments and Results for CMP v.s. Etching Interaction of ET2 lot
In order to prove above assumption, we prepare some wafers with different combination of W-CMP and oxide touch-up CMP rotary direction and then implement Contact-1 etching in
either ET1 or ET2 with over etching recipe or without over-etching recipe to check the effects induced by CMP rotary direction and over etching on overlay control. The detail spilt table is listed in Table 3-8 and the result is shown in Fig 3-14.
The wafer rotation baseline for this experiment is as follows：
1. The wafer rotation baseline for slot 1 and slot 6 are very similar. It means that ET1 wafers is not sensitive to CMP rotary direction. It matches with the previous result that before we implement ET2 etcher for Contact-1 etching in production line.
2. The wafer rotation baseline for slot 4,5,9, and 10 are very close to slot 1 and slot6. It means that ET2 wafers with over etching show deeper alignment mark depth, therefore, not sensitive to CMP rotary direction.
3. ET2 wafers without over etching are very sensitive to CMP rotary direction. The wafer rotation baseline for slot2/3 and slot 7/8 are similar to results from spilt 1 and split 3 in
pervious W-CMP and oxide touch-up CMP rotary direction experiment.
The experimental results have proved the assumption that Contact-1 etching step dominates the poor overlay performance. If the alignment mark is not deep enough, CMP rotary direction will enhance the overlay baseline variation and induce a worse result.
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-Chapter 4
Conclusion and Discussion
4.1 Conclusion of Experiments:
In this thesis, we discuss the CMP and the etching conditions induced lithography overlay error. Some important conclusions are summarized as follows
(a) Alignment mark depth is the most important factor influencing the overlay error. If the alignment mark depth is too shallow, the scanner alignment system either can not detect enough signal and then induce the alignment fail, or the alignment result can not well correspond to the wafer deformation and then make the overlay baseline variation too big.
(b) CMP process also plays an important role in overlay control. Especially in the condition of alignment mark not deep enough, the CMP rotary direction significantly influences the overlay baseline variation.
(c) In the condition of shallow alignment mark depth, scanner alignment system induced performance difference will become significant.
4.2 The discussion for alignment and overlay strategy:
In general, we separate the factors influence the alignment accuracy and the overlay error performance into 2 parts：
(A) Wafer Process：Including all wafer process that may influence the mark shape. Film deposition thickness, etching time, and CMP polish time, all possibly influence the step height of alignment mark. CMP rotary direction, erosions and dishing effect, etching uniformity, film deposition uniformity all possibly influence the alignment mark deformation and asymmetry.
In this study, we increase the etching time and fix the CMP rotary direction to improve the
In this study, we increase the etching time and fix the CMP rotary direction to improve the