Flip Flop Latch
QRS Candidate
storage for additional search back for QRSon. After the detection of R peak, the boundary detector can then be reused to detect the QRSend. Fig. 4-3 (a) shows the pre-detection process of QRSon and following search for QRSend after R peak. Fig. 4-3 (b) shows the architecture of the boundary detector consisting of only comparators and state machines.
1.QRSon candidate 1 2.QRSon candidate 2
3.R peak confirmed
5.QRSoff confirmed
4.QRSon confirmed
thrboundary
Fig. 4-3 (a) The pre-search process of QRSon detection and the followed detection of QRSend after R peak. (b) Architecture of the boundary detector
The adaptive THR/WIN update engine generates the peak /boundary threshold for the QRS FSMs and boundary detector and the search window for P/T detection. Upon every successful detection of QRS complex, the thresholds are updated based on the
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signal and noise level. Designed avoiding complex mathematical operations, the multiplier-free engine consists of only adders and comparators and some registers to hold the current value. Fig. 4-4 shows the architecture of the adaptive THR/WIN
Fig. 4-4 The adaptive THR/WIN update engine
The search kernel for P and T wave is shared for the similar detection rules and is only activated after successful detection of QRS complex. For the detection of P and T wave, the scale-4 coefficients located in the search window must be first examined to locate the minimum and maximum point in order to check the wave existence then find the zero crossing point between them. Searching in an iterative approach, large cycles are needed to complete the detection. Optionally, two different implementations can be made. The first using doubled memory storage for saving the coefficients for P and T wave individually. The search is performed at system operating frequency (250Hz). The second implementation uses only half of the memory but operates in a higher operating speed in order to finish the P wave search before saving the T window coefficients.
Because of the low operating frequency, the total power is dominated by leakage.
And among them, the storage element takes the largest percentage of the total power.
The second implementation with less memory is clearly the better solution. With the
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help of asynchronous techniques in Chapter 3, the asynchronous design consumes similar energy as synchronous design but eliminate the additional requirement for high frequency clock. The asynchronous search operates in an event-triggered way and can be shut down when not needed. The asynchronous search kernel also exhibits low latency for power up and down suitable for this application. Fig. 4-5 shows the time diagram showing the shared search kernel for P/T detection and the shot active duty cycle using asynchronous circuit. Additional on-chip tuning circuit proposed in Chapter 3 is also included in the delineator to acquire the best delay line margin to ensure computation efficiency and function correctness.
P window T window
CLK (250Hz) R peak P/T Asycn CE
P detection T detection
<0.05% active duty cycle Scale-4
Fig. 4-5 Time diagram showing the shared search kernel for P/T detection and the shot active duty cycle using asynchronous circuit
A register-based memory of size 100x12bit is designed for this architecture. The decoder in the memory is moved into the asynchronous power domain to reduce the leakage power. By doing so, 4% of memory leakage power can be reduced.
A synchronous-asynchronous interface connects the data links between the synchronous and asynchronous portion. Fig. 4-6 shows the detail of the interface.
Because all the input parameters are ready before the activation of the asynchronous kernel, no complex handshake is required at the input interface. As EN goes high, the loop formed inside the proposed asynchronous handshake circuits, starting the
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iterative search. The search kernel searches the P/T wave by locating the min-max pair and zero crossing points. Every computation that requires iterative computations (e.g.
counter, min-max searching) utilizes the two latches (slave and master) for correct computation. As soon as the wave is found, the VALID wire goes high and triggers the output register. The asynchronous kernel can then be shut down with very little latency reducing the leakage power.
Input Mixed-timing Interface Output Mixed-timing Interface
DELAY HS 1
Fig. 4-6 The input and output interface for the asynchronous P/T kernel
4-2 Implementation Result
The proposed delineator is implemented using UMC 90nm CMOS technology and operates at 250Hz with input ECG of 12-bit resolution. Fig. 4-7 shows the power dissipation with the proposed low power strategies. By reduced wavelet scales and storage optimization in algorithm level, 45% power is saved. In addition, the introducing of event-triggered asynchronous search kernel further reduces half of the memory size and can be power gated reducing leakage power. This results in another 30.3% power reduction. Since the delineator power is dominated by the leakage, the usage of high VT devices with 0.5V voltage scaling suppresses the static power. With optimization on algorithm, architecture, and circuit level, the average power of the
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proposed ECG delineator is 2.56μW. Fig. 4-7 also shows the power distribution, memory is still occupies the most power consumption.
5-wavelet
Fig. 4-7 Power reduction with strategy at different design level
Fig. 4-8 shows the layout photo of the proposed delineator. The area is 250μm×250μm. The asynchronous P/T wave search kernel and the corresponded tuning circuit are separated in different power domains for individual power management.
Fig. 4-8 Layout photo for the proposed cardiac delineator
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4-3 Comparison with State-of-The-Art
Table 4-1 compares the proposed delineator with the state-of-the-art hardware cardiac feature extractor. All the existed designs only provide feature detection of R peaks [14]-[17], while the proposed design provides the detection of all 5 fiducial points (P, QRSon, R, QRSend, T). With the provided features, the syndromes number which can be detected is much more than the syndromes which can be classified using only R peaks (Table 1-1). This includes syndromes with high risk such as Myocardial Infarction. Operating at 0.5V, the average power is 2.56μW, which is fairly small comparing with the previous designs with only R peak detected.
Table 4-1 Comparison of the proposed delineator with the state-of-the-art detector
[14] 2009 ASSCC
[15] 2009 TBCAS
[16] 2010 ISCAS
[17] 2012 TBCAS
This Work
Technology 0.18μm 0.35μm 0.18μm 0.35μm 90nm
Area (mm2) 1.1 N/A 0.68 1.11 0.06
Normalized
Area (mm2) 0.28 N/A 0.17 0.07 0.06
Supply (V) 1.8 3.3 N/A 1.8 0.5
Frequency 1MHz N/A 500Hz 300Hz 250Hz
Power 176μW 2.7μW 2.21μW 0.83μW 2.56μW
Features R R R R
P, R, T, QRSon, QRSend R peak Se (%) 99.63% 99.81% 95.65% 99.31% 99.71%
R peak Pr (%) 99.89% 99.80% 99.36% 99.70% 99.68%
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