In addition to program/erase speed, nonvolatile memory cells have some important functional characteristics, which are used to evaluate the suitability and practicality of the cells under test. These characteristics are divided into two main classes, namely retention and endurance. They are discussed in the following sections.
4-1 Retention
Retention is a measure of the time that a nonvolatile memory cell can retain the charge in the trapping layer. Fig. 4-1 shows the band diagram for illustrating the charge loss paths in SONOS cells. There are two major leakage current components in relating to charge loss, one is the thermionic emission following Frenkel-Poole mechanism, another one is tunneling through either blocking oxide or tunneling oxide.
The Frenkel-Poole emission is due to field-enhanced thermal excitation of trapped electrons into the conduction band of silicon. The trapped charge can be expressed as:
nt(φt,t)=nt(φt,0)•e−tτ (eq. 4-1) where nt(φt,0)is the initial trapped charges, and τ is the time constant. The time constant of Frenkel-Poole emission can be expressed as:
τFP =τ0exp{[φN −q(qE/πε)12]/kT} (eq. 4-2) where φN is the corresponding nitride trap energy, E is the electric field and ε is the high-frequency permittivity.
The tunneling mechanisms include trap-to-band (T-B) tunneling, trap-to-trap
(T-T) tunneling, and band-to-trap (B-T) tunneling. The trapped electrons in nitride can tunnel back to the conduction band of the silicon substrate (trap-to-band tunneling), or to the interface traps between tunneling oxide and channel (trap-to-trap tunneling). In addition, holes from the silicon valence band may tunnel into the nitride traps under the influence of the internal electric field (band-to-trap tunneling). The time constant of tunneling mechanism can be expressed as:
τT =τ0⋅exp(αox⋅tox)⋅exp(αN ⋅tN) (eq. 4-3) where t is the thickness of tunneling oxide, ox t is the distance from trap in nitride to N tunneling oxide. Andτ0 , αox, and αN are different in trap-to-band tunneling, trap-to-trap tunneling, and band-to-trap tunneling.[37]
Fig. 4-2 shows the data retention of single-gated NW-SONOS, and it is far worse than the required ten years retention. In general case, i.e., with single-crystal silicon for th channel and dry oxide for tunneling oxide, trap-to-trap tunneling is normally neglected for a fresh SONOS cell measurement. However, in our case with TFT-SONOS, since there are many interface traps existing between tunneling oxide fabricated by TEOS and poly-Si channel, trap-to-trap tunneling must be considered.
Hence the worse retention capability for TFT-SONOS over conventional SONOS is expected. Nevertheless, as shown in Fig. 4-3, the data retention at programming state is improved by double-gated structure. Data retention with a continued electric field on the trapping layer is also tested. At the programming state, the side-gate is biased at -2V and the source and drain are grounded to accelerate the trapped charges loss.
On the other hand, at the erasing state, the side-gate is biased at +2V and the source and drain are grounded to accelerate the charges tunneling into nitride. The result is shown in Fig. 4-4. The retention capability at programming state of double-gated structure is better than that of single-gated structure, and the erasing state of single gated structure is more easily influenced by electric field than that of double gated
one.
Possible cause of the phenomenon is the location of trapped charges. In equation 4-3, τT is seriously influenced byt . If the distance from the location of trapped N charges to tunneling oxide is larger, nitride will retain the trapped charges longer. In addition, since the nitride layer covers the whole side-gate and no oxide layer stops the charges from diffusing toward the vertical dimension in our structure, the distance from the location of trapped charges to channel edge is important for retention. Based on the assumption, the cause of improved retention ability is due to the top-gate, which can change the direction of electric field toward trapping layer, and cause charges to be trapped deep.
If top-gate can change the direction of electric field toward trapping layer, different VTG will cause charges to be trapped on different locations. Therefore, the retention will also be different. Retention under different VTG, i.e., VTG of 15V, 0V, and floating, is compared in Fig. 4-5, and the result supports the assumption.
In addition, the Vth of single-gated structure (Vth, SG) is the smallest, while the Vth
of double-gated structure (Vth, DG) with 180Å-thick top gate oxide is the largest, as shown in Fig. 4-4. The explanation of this situation is referred from [38]. Fig. 4-6 is extracted from [37], and State C in Fig. 4-6 (c) shows that when Vg2 is less than VthDG, Vth(G1) will be larger than VthDG. Therefore, since VTG is grounded in read state, i.e., VTG is smaller than VthDG, Vth, SG is smaller than Vth, DG. Besides, when Tox2 is thinner,
DE
AB will be larger with the same ΔVg2. Hence, Vth, DG with 180Å-thick top gate oxide is larger than that with 360Å-thick top gate oxide. In physics, VTG is lower than Vth, DG, and the higher VSG is needed to generate sufficient electrons in the channel near the side-gate to turn on the device, so Vth, SG will be higher. In addition, the thicker top-gate oxide will cause the channel control near the top-gate to be lower, so ΔVth
will be smaller.
4-2 Endurance
Endurance is the ability of a nonvolatile memory to endure the damage of numerous cycles of programming and erasing, i.e., the number of erase/write cycles that the memory will retain the required memory window and continue to operate as specified in the data sheet. Since the carriers for programming and erasing have energy, they will cause the degradation of tunneling oxide and trapping layer in every operation. In addition, high electric field stress across tunneling oxide will increase the current density at low electric field. The excess current at low electric field is called stress-induced leakage current (SILC) [39]. SILC is attributed to stress-induced oxide defects, which lead to a trap assisted tunneling. The main parameters controlling SILC are the stress field, the amount of charge injected during the stress, and the oxide thickness.
In general, flash products are specified for 106 erase/program cycles. However, the endurance requirement can be loosened with the increase of memory density for the other applications. Fig. 4-7 shows the endurance requirement of NAND Flash memories [40]. We can see that the endurance requirement is 100k cycles for NAND Flash with 256 MB density. Since for a memory array with higher density, a certain cell in a block has less possibility of being written and erased. This is because the memory operation of an individual cell in the array is repeated only after the entire memory blocks are addressed. This is why the endurance requirement of digital still camera (DSC), the biggest NAND Flash application, has decreased from 10.3K cycles for 128MB to 2.6K cycles for 1GB. The endurance requirement is sufficient for the
user to take 700 photos with 1MB size every day for 10 years.
Figs. 4-8 (a) and (b) show the ID-VG curve of single-gated and double-gated structures with increasing erase/program cycles. It can be seen that the subthreshold swing and memory window of both structures worsen with increasing erase/program cycles. The subthreshold swing worsening is due to the degradation of tunneling oxide, and the memory window closure is due to the degradation of nitride. Figs. 4-9 (a) and (b) show the memory window versus erase/program cycles of single-gated structure and double-gated structure, respectively. The poor endurance is due to the poor quality of TEOS for tunneling oxide and the horn of the channel. The traps are easily generated because of poor quality of TEOS. Besides, high electric field due to the horn of the channel will seriously damage the tunneling oxide.