This section describes the implementation results of the proposed filter bank design and the comparisons between other reported related works. We use PrimePower to do the gate level simulation to evaluate the power consumption.
Table 4-4 summarizes the comparisons between the proposed designs and other reported filter banks in the literature. Note that there is relatively less number of bands in [14] and [16]
respectively. The power performance of the filter banks may greatly increase if more bands are necessary. Moreover, the filter bank in [16] only has 40dB attenuation. The attenuation is usually required to have at least 60dB. Furthermore, the design in [14] and [17] operate at 16 KHz sampling rate, so the highest-frequency band-pass filter can not cover the frequency of 8 KHz which has a prescribed amplification target on it. On the other hand, the design in [17] is complicated, which implements each of the 16 bands with a 109-tap FIR filter. For the purpose of fair comparison within different process technologies, we normalize the power with respect to the sampling rate, the process, the square of supply voltage, as well as the
number of filter bands as described in equation (4-5)
As shown in Table 4-4, we conclude that the proposed 1/3-octave filter bank is the most low power design except the design in [20] and [16]. But the stop-band attenuation in [16] is only 40dB which is much smaller then 60dB stop-band attenuation in other works. Besides, the price the work [20] pay is the long group delay which is up to 78ms and it will largely limit the application of the design. More over, the synthesis bank in [20] will need a lot of memory to synchronize the delay between bands.
Table 4-4 Power comparisons of filter bank for hearing aids
# bands Sampling
Proposed 18 24K 0.09 1.20 104 104
Table 4-5 Overall comparison between [20] & proposed design Max. matching group delay and the power consumption (analysis bank + synthesis bank) is reported in Table 4-5. Compared with [20], the proposed 1/3-octave filter bank has the advantages of low group delay and low power when take synthesis bank into considerations. There are only slight and acceptable degradation in matching capability as verified in Section 3.4.
5 C ONCLUSIONS
This thesis addresses the low-delay low-power filter bank design for advanced digital hearing aids. Due to the high group delay and the high computation complexity, the standard ANSI S1.11 1/3-octave bank is rarely adopted in the literatures, even though it has the advantage of good matching to the famous prescription formula NAL-NL1 and the human hearing characteristics.
We develop a quasi-ANSI S1.11 1/3-octave filter bank design method to meet the group delay constraint. The group delay is largely reduced from 78ms to 10ms compared with the ANSI S1.11 1/3-octave filter bank design in [20]. We also proposed an error minimization method such that the matching capability only has slight and acceptable degradation. The maximum matching error only slightly increases from 0dB to 1.5dB in worst case.
Complexity-effective filter bank architecture is designed by using the IFIR and multirate technique. The implementation of 18-band quasi-ANSI S1.11 1/3-octave filter bank needs
only 7% of multiplications and 26% of storage elements of a straightforward parallel FIR filter bank. We also investigate and apply some lower-power VLSI techniques such as the clock gating and polyphase implementation to save the power consumption. The 18-band quasi-ANSI S1.11 1/3-octave filter bank has been implemented in UMC 90nm CMOS technology. The design consumes only 104μW for processing 18-band, 24 KHz audio signal.
The proposed filter bank is 10ms-group-delay, low-power, and being able to precisely matching the prescribed gains generated by the widely used NAL-NL1 formula.
Our future work is trying to further reduce the power consumption by any other optimizations. For example, we can achieve further power saving by applying voltage scaling technique for two reasons. Firstly, our filter’s delay line is implemented with register chains instead of memory generated from memory compiler in which the supply voltage is fixed. On the other hand, the lower supply voltage will cause the circuits operating slower then origin.
The timing slack of our design is large because the operating frequency is only about 300 KHz in our design and will be benefit to apply voltage scaling technique.
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作者簡歷
莊明勳，1985 年 4 月 29 日出生於台南市。2007 年取得國立清華大學工程與系統科 學系電子組學士學位，並在國立交通大學電子工程研究所攻讀碩士。2010 年在劉志尉教 授指導下，取得碩士學位。本篇論文「適用於數位助聽器之 10 毫秒群延遲且近似於 ANSI S1.11 1/3-octave 規範的濾波器組」為其碩士論文。