• 沒有找到結果。

To promote the injection efficiency of electrons, the feasibility of using channel-initiated secondary electron (CHISEL) programming has been demonstrated in the MONOS devices [4.2]. CHISEL programming conditions and mechanisms are shown in Fig.4-3(a). The hot holes generated near the drain mainly drift toward the substrate and contribute to the substrate current (IB). Some of these hot holes create electron-hole pairs by secondary impact ionization, which are greatly enhanced under a a high electric field by the applying of a reverse substrate bias (VB <0). As a result,

41 

the hot electrons caused by the secondary impact ionization tend to be injected into the MONOS structure and result in a wide distribution of trapped electrons, compared with the case of channel hot electron injection (CHEI) [4.3]. Fig.4-3(b) illustrates the energy band diagram for CHISEL programming operation. Owing to the reverse substrate bias, the conduction band (EC) of the substrate is raised, and the substrate hot electrons can more easily tunnel through the oxide energy barrier (i.e., 3.1eV).

Discrete charge storage memories (e.g., SONOS and nanocrystal) are typically erased using hot holes injection (HHI) [4.4], generated by band-to-band tunneling (BBT) in the channel and drain side overlap region. The HHI erasing conditions and mechanisms are shown in Fig.4-4(a). During the HHI erasing operation, the n-type SONOS device is turned off while maintaining a negative gate bias with positive drain and substrate biases. The energy band diagram [4.5] during the HHI erasing operation is shown in Fig.4-4(b). The increased positive bias in substrate causes a downward shift of valance band of the substrate and also helps promote charge trapping efficiency of the nitride layer [4.6]. My discussion replaced the Si3N4 to HfO2-ZrO2 layer own the same program and erase mechanism to above-mentioned.

We apply low voltage on MoN electrode and erase the MONOS capacitors from -6Volt to 6 Volt, and program the MONOS capacitors from 6Volt to -6Volt, and then raise the external voltage to erase the MONOS capacitors from -7Volt to 7 Volt, and program the MONOS capacitors from 7Volt to -7Volt, continuously to 8Volt. In Fig.4-5, the C-V hysteresis window of 4.6V, 5.2V and 7 V was measured respectively.

Low leakage current exhibits the blocking oxide has good quality to isolate electrons as Fig.4-6.

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Fig.4-1 Cross section view of MoN/SiO2/HfO2-ZrO2/SiO2/Si structure which was not patterned.

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Fig.4-2 Cross section view of MoN/SiO2/HfO2-ZrO2/SiO2/Si MONOS.

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Fig.4-3 Channel-initiated secondary electron (CHISEL) programming mechanism for n-channel MONOS memory device. (a) Programming conditions and related events inside the substrate. (b) Band gap diagram for the programming.

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Fig.4-4 Hot holes injection (HHI) erasing characteristics of N channel MONOS memory device. (a) Erasing conditions and mechanisms. (b) Erasing band gap diagram.   

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Fig.4-5 The measured C-V hysteresis of high-κ HfO2-ZrO2

interactive trapping MONOS capacitor.

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Fig.4-6 The measured J-V characteristics of high-κ HfO2-ZrO2

interactive trapping MONOS capacitor.

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Chapter 5 Conclusions

  Semiconductor flash memory device technology will continue to play an important role in the electronics industry, although its development has been facing a lot of challenges. Conventional FG structure suffers from serious coupling issues that degrade the device characteristics and may eventually limit further device scaling. It thus faces fierce competition from a number of new types of devices, including the MONOS.

In this dissertation, we emphasize on improvement of the trapping layer. If the trapping layer can efficiently catch more charges in a thin film, storage capability may become outstanding. High-κ material of Hafnium oxide (HfO2) and Zirconium oxide (ZrO2) mix together by post-deposition annealing (PDA) process, in chaper3 and chapter4, we see that the interactive structure reveals big memory window, good retention and program-erase function by charge trapping or de-trapping in the high trap density HfO2-ZrO2.

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Chapter 4:

[4.1] S. H. Gu, T. Wang, W. P. Lu, Y. H. Ku, and C. Y. Lu, “Extraction of nitride trap density from stress induced leakage current in silicon-oxide-nitride-oxide-silicon flash memory,” Appl. Phys. Lett., vol. 89, pp.

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[4.2] Souvik Mahapatra, S. Shukuri, and Jeff Bude, “CHISEL Flash EEPROM-Part I:

Performance and Scaling,” IEEE Trans. on Electron Devices, Vol. 49, No. 7, pp.1296-1301, July 2002.

[4.3] Souvik Mahapatra, S. Shukuri, and Jeff Bude, “CHISEL Flash EEPROM-Part II:

Reliability,” IEEE Trans. on Electron Devices, Vol. 49, No. 7, pp.1302-1307, July 2002.

[4.4] Y. Wang, Y. Zhao, B. M. Khan, C. L. Doherty, J. D. Krayer, M. H. White, “ A novel SONOS Nonvolatile Flash Memory Device Using Substrate Hot-hole Injection for Write and Gate Tunneling for Erase,” Semiconductor Device Research Symposium, Vol. 10-12, pp.228-229, December 2003.

[4.5] Luca Larcher, Paolo Pavan and Boaz Eitan, “On the Physical Mechanism of the NROM Memory Erase,” IEEE Trans. on Electron Device, Vol. 51, No. 10, pp.1593-1599,October 2004.

[4.6] Gowrishankar L. Chindalore, Craig T. Swift, and David Burnett, “A New Combination-Erase Technique for Erasing Nitride Based (SONOS) Nonvolatile Memories,” IEEE Electron Device Letters, Vol. 24, No. 4, pp.257-259, April 2003.

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