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Fig. 2-1 shows that it is necessary to extend the actual flash memory device technology lifetime as much as possible. Through decades of development, flash devices are categorized into two types of structures, namely, FG [2.5] and charge trapping structures, as illustrated in Fig. 2-2. For FG devices, owing to the high topography of the gate structure, the interference between neighboring cells by gate coupling becomes an almost unsolvable issue beyond 45nm-node. As a consequence charge trapping flash memory devices such as SONOS is revisited as the succeeding technology to avert interference between neighboring cells.
Before the floating gate (FG) non-volatile memory, the magnetic-core memory[2.7]
has a lot of issues, such as large volume, high power consumption, and high cost.
Therefore, new kind of memory needs to be invented to replace the magnetic-core
memory. In 1967, the first floating gate non-volatile memory was invented by D. Kahng and S. M Sze at Bell Labs [2.8]. FG structure is composed of a POLY1
floating gate inserted between an underlying tunnel oxide and a blocking oxide layer.
A POLY2 layer is deposited on top of the blocking oxide layer to serve as the control gate, as shown in Fig. 2-3. In SONOS structure, in Fig. 2-4, a carrier-trapping layer made up of nitride is inserted between two silicon oxide layers to prevent charge loss.
Such flash cells resemble a standard MOS transistor except that the gate oxide is replaced by an oxide-nitride-oxide dielectric stack [2.9].
The storage material is typically a degenerately doped poly-Si for floating-gate devices and a nitride layer for SONOS devices. The mechanisms of charge storage are different between the two types of devices due to the different storage materials.
Since the floating gate is made up of a conducting material, the stored electrons flow freely inside the floating gate. This raises a reliability issue in that if certain paths for stress induce leakage current (SILC) are created in the tunnel oxide during operation, the stored charges may easily find the path to leak out which in turn lead to poor retention and endurance characteristics. On the other hand, the nitride storage layer in SONOS device contains discrete traps serving as the charge storage sites. The injected electrons are trapped in deep level of the nitride layer and become immobile, so the aforementioned SILC issue can be avoided and better retention and endurance are expected [2.10].
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Programming operation can be achieved by injecting charges into the storage layer, a nitride for the SONOS or a poly layer for the FG type. Channel or substrate hot carrier injections are usually employed for this purpose. On the other hand, erasing
mechanism could be implemented via band-to-band hot holes injection from drain side. For efficiency, both programming and erasing operations need high biases on the gate and drain. The high electric field may provoke potential reliability concerns such as oxide breakdown and generation of excessive SILC. Moreover, high power consumption while the devices are under programming and erasing operations is inevitable [2.11].
The difference between FG and SONOS-type devices lies in the method of charge storage, which is fundamental to issues such as scaling and radiation hardness. The concept of nonvolatile data storage based on a shift in the threshold voltage of the nonvolatile semiconductor memory (NVSM). The threshold voltage has the following expression [2.12]
(Eq.2-1)
where Qss is the fixed charge at Si-SiO2 interface, is the charge in silicon semiconductor, QT is the charge stored in the gate insulator, CI and are the capacitance per unit area and dielectric constant of the gate insulator layer, respectively. Based on Eq.2-1, threshold voltage increases when more electrons are trapped. On the contrary, threshold will be decreased, if QS quantities are reduced.
Therefore we can control QS by means of varying the substrate doping concentration to adjust the threshold voltage of flash devices. The threshold voltage window (Program Vth – Erase Vth) should be maintained at least 1.5V to easily distinguish between “1” and “0” states by peripheral sense amplifier circuits [2.13]. The storage charges will gradually leak away as the storage time progresses because of the existence of different leakage mechanisms. The capability of preserving the charge
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storage is directly related to the data retention and device life time. Therefore the FG device has added a thick oxide layer or ONO (oxide-nitride-oxide) layer above POLY1 to reduce charge loss through the top side while keeping the gate coupling ratio. On the other hand, SONOS must maintain a tunneling oxide thickness of around 2nm or above to prevent the excessive direct tunneling of charges from nitride layer to substrate. When thickness of oxide is smaller than 25Å or extreme big electric field across on the thin oxide, it is easier to happen direct tunneling which is hopeless for ONO structure and it could be eliminate retention. High temperature data retention analysis is usually performed to monitor the variation of programmed threshold voltage as a function of the elapsing time. The measurements are typically performed between 150OC and 250OC to ensure 10-year data retention time. Both programmed and erased operations affect the endurance capability of flash devices.
These procedures should thus be carefully designed and optimized to improve the endurance characteristics. Conventionally for floating-gate devices, channel hot electron injection (CHEI) and hot hole injection (HHI) mechanism are employed to program and erase the device, respectively. CHEI has better speed performance.
Nevertheless, the hot electrons are injected into POLY1 layer from the channel region near the drain, and may cause defects like trapped charges in the oxide and interface states, so the threshold voltage window narrows with program/erase (P/E) cycles. For SONOS devices, channel induced secondary electron injection (CHISEL) can be an alternative approach for programming, while HHI is used for erasing. CHISEL programming method proceeds by negatively biasing the substrate. As a result, more hot electrons and secondary electrons are generated and the programming speed is effectively improved. CHISEL thus provides better programming efficiency than CHEI. However, CHISEL will also result in interface state damage, so that subthreshold swing (SS) and mobility (Gm) are degraded after P/E cycling.
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