This chapter is divided into four parts. The first part is about the process tuning by Schottky diode, including recess depth, recess target, recovery condition, treatment prior to oxide formation. The second part is about the performance of conventional E-mode HEMT device. Recessed E-mode performance is discussed in the third part. And the last part presents the D-mode HEMT device performance on the same wafer.
4-1 Process condition test by Schottky Diode
4-1-1 Recess etching condition
Schottky diode was fabricated to test the stable etching rate and reliable condition of ICP etching. Since the device performance depends on the etching depth, a slow and stable etching rate is preferred. ULVAC-NE550 was used for this experiment, and the condition is as the following: BCl3 = 20 sccm /platen power = 50 W, Pressure = 3 Pa. By using the P-10 analyzer, it was found that the etching rate is 0.05 nm/s, which is very slow and stable.
Additionally, I-V characteristics were also tested to inspect the diode
performance. Fig 4-1 shows the results of Schottky leakage current with etching time. The etching time was increased from 0 to 300s. To clarify the results, Fig. 4-2 plots the leakage current as a function of etching time. The leakage current of the non-etched sample was around 50μA. As etching time was up to 300s, the leakage current was around 3 μA which still remained at the similar current scale with non-etched sample. It could be attributed to the low etching rate which alleviates the surface damage and enhance the reliability of the etching process.
4-1-2 Recess target test for recessed E-mode MIS-HEMT
After the optimum recess etching rate was obtained, the optimized etching depth must be identified. In the experiment, the main purpose of the recess is to etch out the 2DEG channel in the heterojunction layer, therefore, it should have no current at Vg= 0V. Besides, longer time is tested to find out how etching depth correlate to the electron density by C-V test.
After the measurement, we found that at least 700s etching time is required to get the E-mode device. C-V performance as a function of different etching time is shown in Table 5-1. The capacitance of the devices does not show much difference as the etching time increase, which means that all
etching time is applicable as long as it’s longer than 700s. However, from the D-C performance, it is shown that the samples subjected to 1000s and 1200s etching time have high leakage current problem. Based on the leakage current data, 800s etching time was used in this study, which means the 400nm etching depth beneath the gate. Fig. 5-3 shows the C-V curve of the sample with 800s etching. As the voltage increased, the capacitance increased as well since the electrons were accumulated underneath the gate region.
4-1-3 RTA recess recovery condition test
After recess process, the sample was further tested to find out the optimum process condition for damage recovery. Temperature of 400oC was used for 5 min and 10min, and then DC measurement was carried out to identify the trend of leakage current. Furthermore, ideal factor and barrier height were also calculated. Table 4-2 lists the results.
From the comparison between the recessed but RTA-free sample and the sample without recess, it can be found that the leakage current is lower after recess. The result is the same as the results in the leakage current test in section 4-1-1. However, the ideal factor is increased, meaning the forward current performance is worse. After RTA, the 5 min annealed sample posses
ideal factor = 2.1 and the leakage current was 0.728μA. The 10-min annealed sample has ideal factor of 2.16 and leakage current of 0.496μA. The barrier height of all samples are similar. Figs 5-4 and 5-5 shows the trend of the parameters. Therefore, consider both of the leakage current and ideal factor, 10 min RTA was applied in the following experiments.
4-2 Device performance of conventional E-mode HEMT.
The structure of the device is shown in Fig. 3-1. It was dsigned to satify the threshold voltage issue.
The device performances were shown in Fig 4-6 and Fig. 4-7. The maximum ID was 235 mA/mm, and the Gm was 78 mS/mm. Fig.4-7 shows that the threshold voltage of the device was 0.1V, which is not applicable to high voltage electronic applications.
4-3 Device performance of recessed E-mode MIS-HEMT
Figs 4-8,4-9 and 4-10 show the device performances. The maximum ID
was 2 mA/mm, and the transconductance was 0.8 mS/mm. The gm curve didn’t show the highest peak because of the Si3N4 has weak field strength.
Breakdown voltage was larger than 200V, and the threshold voltage was 9V.
The result shows that the recessed MIS-gate structure in conjunction with the
polarization-induced negative charges below the gate effectively enhances the threshold voltage of the AlGaN/GaN/AlGaN MIS-HEMT. Compare to Sharp [28], which has ID= 120 mA/mm, the device in the experiment shows lower forward current. It may due to the different substrate structure. In Sharp’s work, the substrate was Si, however, in this experiment sapphire was used. It is expected that the main current is generated from the heterojunction below, and the different heterojunction condition will cause different electron quantity attracted. The lattice mismatch between the AlGaN with Si and with sapphire is entirely different, hence, the different lattice mismatch will cause the different performance of the devices.
4-4 Device performance of D-mode HEMT device.
The structure is as same as the sample used in recessed E-mode MIS-HEMT.
The maximum current achieved was 280 mA/mm, and the gm was 75mS/mm.
It illustrates that the structure can be applied to D-mode HEMT application.
Table 4-1. Capacitance of the Schottky diode on different recess target.
Etching time 700s 800s 1000s 1200s
Capacitance(F) 1.6E-12 1.62E-12 1.36E-12 1.5E-12
Table 4-2. The comparison of leakage current, ideal factor , barrier height at different RTA condition.
Non Recess RTA free RTA5min RTA10min
Leakage
current(@-30V)
6.94E-04A 9.73E-05A 7.28E-05A 4.96E-05A
Ideal factor 2.47 3.19 2.1 2.16
barrier height 0.91 0.85 0.84 0.87
Fig 4-1. Leakage current of Schotty diode at different recess time.
Fig 4-2. Leakage current trend of Schotty diode at different recess time.
-30 -25 -20 -15 -10 -5 0
Fig 4-3. C-V curve of the 800s etched Schottky diode.
Fig 4-4. Leakage current trend on different RTA condtion.
0 2 4 6 8 10 12