In this section, the electrical characteristics of poly gate SONOS-type memory with HfAlO and Al2O3 for blocking layer were discussed.
3-3-1 Ig-Vg Curves and Memory Window
Fig. 3-2 shows that relationship between gate leakage current Jg (A/cm2) and gate electric field Vg/EOT (MV/cm). We observed the HfAlO blocking layer memories have higher gate leakage current Jg than Al2O3 ones at high electric field (Vg/EOT >8 MV/cm), this is probably because the HfAlO blocking layer memories have more grain boundaries and lower conduction band gap than Al2O3 ones. Because of Hf crystalline temperature lower than Al2O3, the grain boundaries may generate after high PDA temperature. The leakage may pass through these grain boundaries. Another because that HfAlO blocking layer memories have lower band gap than Al2O3 ones, the electrons may tunnel easily through the gap to gate. Fig. 3-3 and Fig. 3-4 show the Id-Vg curves of the Al2O3 and HfAlO blocking layer memories under program and erase operations. We use channel hot electron injection (CHEI) to program and band to band hot hole to erase (BTBHH). All the program condition are Vg= 8V, Vd= 8V with 10 m-sec stress, and the erase condition are Vg= -9V, Vd= 9V with 0.1 sec stress. The Vth of Al2O3 blocking layer after programming shift about 1.5V from the original fresh state, and the HfAlO ones are about 2.4V. After erasing, the Vth shift almost the same as program state-fresh. So the memory windows are about 1.5V (Al2O3) and 2.4V (HfAlO). We also observed that the higher gate leakage current the larger memory window, just like HfAlO ones.
34
3-3-2 Program and Erase Speed
For the SONOS-type flash memory with high-k Al2O3 and HfAlO blocking layer, the program speed are shown in Fig. 3-5~3-8 and Fig. 3-10~3-13. First, we use channel hot electron injection (CHEI) to program all samples and show four different stress conditions: Vg= 7V, Vd= 7V; Vg= 8V, Vd= 8V ; Vg= 9V, Vd= 9V; Vg= 10V, Vd= 10V in Fig. 3-5~3-8. We can obviously observe the line of Al2O3 and HfAlO (700oC PDA) are not going up about 10-5 and 10-6 sec, this is because that the higher PDA temperature ones generate interfacial state to hold memory programming. We also compare the CHEI program speed at the same PDA conditions, as shown in Fig. 3-9 and Fig. 3-10. We found that SONOS-type memories with HfAlO blocking layer program faster than Al2O3
ones about < 1 m-sec, but Al2O3 ones faster than HfAlO ones about > 1 m-sec. This is because that HfAlO ones have higher k than Al2O3 ones, the program speed is faster about < 1 m-sec; but the HfAlO blocking layer memories have more grain boundaries and lower conduction band gap than Al2O3 ones, these maybe generate gate leakage current.
And then, we use FN tunneling to program all samples and show three different stress conditions: Vg= 13V, Vg= 15V and Vg= 17V in Fig. 3-11~3-14. We also fixed the gate voltage Vg= 15V to compare all devices in Fig. 3-15. We observed that program speed of the SONOS-type memory with HfAlO blocking layer are not faster than Al2O3 ones. This is probably because the lower valance band gap and more grain boundaries of HfAlO ones, the FN program speed of Al2O3 ones are more efficacious.
The erase speed of SONOS-type flash memory with high-k Al2O3 and HfAlO blocking layer are shown in Fig. 3-16~3.19. We use band to band hot hole (BTBHH) to erase all devices and show five different stress conditions: Vg= -5V, Vd= 5V; Vg= -5V, Vd= 7V ; Vg= -5V, Vd= 8V; Vg= 10V, Vd= 10V. We found the more Vd erase voltage degree the better erase efficacy, it seems larger Vg voltage degree does not work. We also fixed the stress condition (Vg= -5V, Vd= 9V) to compare all devices in Fig. 3-20. We observed the HfAlO ones are more difficult to erase to initial state, this is because electron back tunneling occur.
35
3-3-3 Data Retention Characteristic
Fig. 3-21 and 3-22 are the data retention characteristic of SONOS memory with HfAlO and Al2O3 blocking layer measured at 25oC. We can observed that these data are not the same with our predict results, so we plot the illustration for charge loss rate in order to analyze clearly what as shown in Fig. 3-23. We can observe that the HfAlO ones loss charge more than 50% after 104 sec stress. Although it seems that the data characteristics of Al2O3 ones are better than HfAlO ones, the data characteristics of Al2O3
ones are still not very good. This is probably because that the valance band gap of Al2O3 is lower than SiO2 to induce leakage current.
3-3-4 Disturbance Measurement
Fig. 3-24 and 3-25 show the gate disturbance measurement of SONOS-type memory with Al2O3 and HfAlO blocking layer for two stress conditions: Vg= 8V and Vg= 10V with Vd=Vs=Vb=0V at erase state for 103 sec stress. The applied gate voltage will attract electrons in the substrate tunneling to the SiNx layer by FN tunneling mechanism and result into Vth increase. We can obviously found that the devices after 700oC PDA perform good characteristic than As-dep. ones. That is probably because that the 700oC PDA temperature condition make the blocking layer thicker than As-dep. ones. Fig. 3-26 shows the comparison of gate disturbance of SONOS-type memory with Al2O3 and HfAlO blocking layer for one stress condition: Vg= 8V with Vd=Vs=Vb=0V at erase state for 103 sec stress. We found the data characteristics of Al2O3 ones are better than HfAlO ones. This is because the valance band gap of HfAlO is lower than Al2O3 ones. We also measure the gate disturbance at program state, as shown in Fig. 3-27 and 3-28. The measurement conditions are Vg= -8V and Vg= -10V with Vd=Vs=Vb=0V at erase state for 103 sec stress. We can find that phenomenon of electron back tunneling occur after 103 sec stress. Fig. 3-29 shows the comparison of gate disturbance of SONOS-type memory with Al2O3 and HfAlO blocking layer for one stress condition: Vg= -8V with Vd=Vs=Vb=0V at program state for 103 sec stress. We can observe there are more grain boundaries in the SONOS-type memory with HfAlO blocking layer than Al2O3 ones, so the disturbance is not better than Al2O3. Fig. 3-30 shows read disturbance measurement of the SONOS-type memories with HfAlO and Al2O3 blocking layer. We applied two
36
stress conditions: Vg= 3V, Vd= 0.5V to Al2O3 ones and Vg= 4V Vd= 0.5V to HfAlO ones for 103 sec. The read disturbance data of HfAlO are not better than Al2O3.
3-4 Summary
In this chapter, we propose the SONOS-type memories with high-k HfAlO and Al2O3 blocking layer. We have shown the electric curves, like Jg-Vg/EOT, Id-Vg, program/erase speed with different mechanism, charge retention, charge loss rate, gate disturbance with program and erase state, and read disturbance. We compare the qualities of the SONOS-type memories with high-k HfAlO and Al2O3 blocking layer, and discuss the facters about them.
37
p-type Si substrate
LOCOS LOCOS
p-type Si substrate
LOCOS LOCOS
p-type Si substrate
LOCOS
LOCOS Tunneling oxide
p-type Si substrate
LOCOS
LOCOS Tunneling oxide
38
39
40
Fig. 3-1 The process flow and the cross-section of the n+ poly gate flash memory.
0 2 4 6 8 10
10-9 10-8 10-7 10-6 10-5 10-4 10-3 10-2
J g(A/cm2 )
Vg/EOT (MV/cm)
Al2O3 700oC PDA Al2O3 As-dep.
HfAlO 700oC PDA HfAlO As-dep.
Fig. 3-2 The relationship between gate leakage current Jg (A/cm2) and gate electric field Vg/EOT (MV/cm).
41
0 1 2 3 4 5 6 programmed, and erased state at different conditions. The memory windows are about 1.5V.
Fig. 3-4 The Id-Vg curves of the HfAlO blocking layer flash memory in the fresh,
programmed, and erased state at different conditions. The memory windows are about 2.4V.
42
10-7 10-6 10-5 10-4 10-3 10-2 10-1 100
Fig. 3-5 The program speed curves of SONOS-type memory with Al2O3 (700oC PDA) blocking layer. (CHEI mechanism)
10-7 10-6 10-5 10-4 10-3 10-2 10-1 100
Fig. 3-6 The program speed curves of SONOS-type memory with Al2O3 (As-dep.) blocking layer. (CHEI mechanism)
43
10-7 10-6 10-5 10-4 10-3 10-2 10-1 100
Fig. 3-7 The program speed curves of SONOS-type memory with HfAlO (700oC PDA) blocking layer. (CHEI mechanism)
10-7 10-6 10-5 10-4 10-3 10-2 10-1 100
Fig. 3-8 The program speed curves of SONOS-type memory with HfAlO (As-dep.) blocking layer. (CHEI mechanism)
44
10-7 10-6 10-5 10-4 10-3 10-2 10-1 100
Fig. 3-9 The comparison program speed curves of SONOS-type memory with Al2O3 and HfAlO (700oC PDA) blocking layer. (CHEI mechanism)
10-7 10-6 10-5 10-4 10-3 10-2 10-1 100
Fig. 3-10 The comparison program speed curves of SONOS-type memory with Al2O3 and HfAlO (As-dep.) blocking layer. (CHEI mechanism)
45
10-7 10-6 10-5 10-4 10-3 10-2 10-1 100
Fig. 3-11 The program speed curves of SONOS-type memory with Al2O3 (700 C PDA) o
blocking layer. (FN tunneling mechanism)
10-7 10-6 10-5 10-4 10-3 10-2 10-1 100
Fig. 3-12 The program speed curves of SONOS-type memory with Al2O3 (As-dep.) blocking layer. (FN tunneling mechanism)
46
10-7 10-6 10-5 10-4 10-3 10-2 10-1 100 0
1 2 3
Program Time (sec) V th shift (V)
HfAlO 700oC PDA Vg=13V Vg=15V Vg=17V
Fig. 3-13 The program speed curves of SONOS-type memory with HfAlO (700 PDA) oC blocking layer. (FN tunneling mechanism)
10-7 10-6 10-5 10-4 10-3 10-2 10-1 100 0
1 2 3 4
Program Time (sec) V th shift (V)
HfAlO As-dep.
Vg=13V Vg=15V Vg=17V
Fig. 3-14 The program speed curves of SONOS-type memory with HfAlO (As-dep.) blocking layer. (FN tunneling mechanism)
47
10-7 10-6 10-5 10-4 10-3 10-2 10-1 100
Fig. 3-15 The comparison program speed curves of SONOS-type memory with all devices. (FN tunneling mechanism with Vg = 15V)
10-7 10-6 10-5 10-4 10-3 10-2 10-1 100
blocking layer. (Band To Band Hot Hole mechanism)
48
10-7 10-6 10-5 10-4 10-3 10-2 10-1 100
Fig. 3-17 The erase speed curves of SONOS-type memory with Al2O3 (As-dep.) blocking layer. (Band To Band Hot Hole mechanism)
10-7 10-6 10-5 10-4 10-3 10-2 10-1 100
Fig. 3-18 The erase speed curves of SONOS-type memory with HfAlO (700 C PDA) o
blocking layer. (Band To Band Hot Hole mechanism)
49
10-7 10-6 10-5 10-4 10-3 10-2 10-1 100
Fig. 3-19 The erase speed curves of SONOS-type memory with HfAlO (As-dep.) blocking layer. (Band To Band Hot Hole mechanism)
10-7 10-6 10-5 10-4 10-3 10-2 10-1 100
Fig. 3-20 The comparison program speed curves of SONOS-type memory with all devices. (Band To Band Hot Hole mechanism with Vg=-5V Vd=9V)
50
100 101 102 103 104
Fig. 3-21 The retention characteristic of SONOS-type flash memory with Al2O3 (As-dep.
and 700oC PDA) blocking layer at 25oC. HfAlO As-dep. retention at T=25oC
Fig. 3-22 The retention characteristics of SONOS-type flash memory with HfAlO (As-dep. and 700oC PDA) blocking layer at 25oC.
51
100 101 102 103 104 HfAlO As-dep. PDA retenrion at T=25oC
Fig. 3-23 The charge loss rate characteristics of SONOS-type flash memory with all devices at 25oC.
Gate Disturb Time (sec) Erase State V th shift (V)
Al2O3 700oC PDA
Fig. 3-24 The gate disturbance characteristics of SONOS-type flash memory with Al2O3
(As-dep. and 700oC PDA) blocking layer. (Erase State)
52
100 101 102 103
Gate Disturb Time (sec) Erase State V th shift (V)
HfAlO 700oC PDA
Fig. 3-25 The gate disturbance characteristics of SONOS-type flash memory with HfAlO (As-dep. and 700oC PDA) blocking layer. (Erase State)
100 101 102 103
Gate Disturb Time (sec) Erase State Vth shift (V)
Vg=8V
Fig. 3-26 The gate disturbance characteristics of SONOS-type flash memory with all samples. (Erase State)
53
100 101 102 103 -1.0
-0.5 0.0 0.5
Gate Disturb Time (sec)
Program State V th shift (V) Al
2O
Fig. 3-27 The gate disturbance characteristics of SONOS-type flash memory with Al2O3
(As-dep. and 700oC PDA) blocking layer. (Program State)
100 101 102 103
-1.0 -0.5 0.0 0.5
Gate Disturb Time (sec)
Program State V th shift (V) HfAlO 700oC PDA
Vg=-8V Vg=-10V
HfAlO As-dep.
Vg=-8V Vg=-10V
Fig. 3-28 The gate disturbance characteristics of SONOS-type flash memory with HfAlO (As-dep. and 700oC PDA) blocking layer. (Program State)
54
100 101 102 103 -1.0
-0.5 0.0 0.5
Gate Disturb Time (sec) Program State V th shift (V)
Vg=-8V
Fig. 3-29 The gate disturbance characteristics of SONOS-type flash memory with all samples. (Program State)
100 101 102 103
Gate Disturb Time (sec) Erase State Vth shift (V)
Vg=3V Vd=0.5V
Fig. 3-30 The read disturbance characteristics of SONOS-type flash memory with all samples. (Program State)
55
Chapter 4
Conclusions
The thesis of “Study on High-k Gate dieletric Hf1-xAlxO for Blocking layer of SONOS Non-Volatile Memory” was proposed. The results of each chapter are summarized as below.
In chapter 2, we discuss the dependence of different Hf1-xAlxO component dielectric on the different annealing temperatures. We used a systematic methodology to extract the best assumption for our SONOS-type memory. We found Al-rich Hf1-xAlxO dielectric have lower interface density, lower gate leakage current, and lower CET than Hf-rich at the same condition. We also found the H1A2 (Hf : Al = 0.11) sample has the lowest leakage current and CET in Al-rich Hf1-xAlxO, and the leakage current as low as Al2O3 at low PDA conditions.
In chapter 3, we replace conventional blocking layer with HfAlO and Al2O3 dielectric on SONOS-type memories. We have shown the electric curves, just like Ig-Vg, Id-Vg, program speed with different mechanism, erase speed, charge loss rate and disturbances. We demonstrate program efficiency of HfAlOblocking layer are better than Al2O3 ones about < 1 m-sec. But program efficiency of Al2O3 blocking layer are better than HfAlO ones about > 1 m-sec, because of large leakage current.
The EBT phenomenon occurs to erasing and gate disturb with program state. All the retention characteristic data are not good, because of large leakage current occurred by lower band gap.
56
57
In order to overcome the retention, large leakage current and electron back tunneling issue, we propose some assumption:
1. Using lower band gap for trapping layer (such as Si) in order to reduce the gate leakage current.
2. Using nanocrystal for trapping layer in order to improve the retention issue.
3. Using metal gate for larger work function in order to reduce EBT.
4. Using tri-blocking layer (such as oxide/high-k/oxide) may improve the retention issue.
58
Reference
Chapter 1
[1.1] Y. King, “Thin Dielectric Technology and Memory Devices”, Ph.D dissertation,Univ. of California, Berkeley, CA 1999.
[1.2] A.J. Walker et al, “ 3D TFT-SONOS Memory Cell for Ultra-High Density File Storage Applications”, 2003 Symposium on VLSI Technology.
[1.3] S.M. Sze, “Physics of Semiconductor Devices, 2nd Edition”, John Wiley &
Sons.
[1.4] B. D. Salvo, C. Gerardi, R. V. Schaijk, S. A. Lombardo, D. Corso, C.
Plantamura, T. Serafino, G. Ammendola, M. V. Duuren, P. Goarin, W. Y. Mei, K. V. D. Jeugd, H. Baron, M. Gély, P. Mur, and S. Deleonibus, IEEE Trans.
Device and Materials Reliability, 4, 377 (2004).
[1.5] Y.-N. Tan, W.-K. Chim, B. J. Cho, and W.-K. Choi, IEEE Trans. Electron
Devices, 51, 1143 (2004).
[1.6] J. Bu and M. H. White, Solid-State Electron. 45, 113 (2001).
59
[1.7] M. L. French, C. Chen, H. Sathianathan, and M. H. White, IEEE Trans.
Compon., Packag. Manuf. Technol., Part A 17, 390 (1994).
[1.8] F. R. Libsch and M. H. White, Solid-State Electron. 33, 105 (1990).
[1.9] C. Lee, S. Hur, Y. Shin, J. Choi, D. Park, and K. Kim, Proceedings of the
Conference on Sol. State Dev. Mat. 162 (2002).
[1.10] S.-H. Lo, D. Buchanan, Y. Taur, and W. Wang, “Quantum-Mechanical Modeling of Electron Tunneling Current from the Inversion Layer of Ultra-Thin-Oxide nMOSFETs,” IEEE Electron Device Lett. 18, 209–211 (1997).
[1.11] D. Frank, R. Dennard, E. Nowak, P. Solomon, Y. Taur, and H.-S. Wong,
“Device Scaling Limits of Si MOSFETs and Their Application Dependencies,” Proc. IEEE 89, 259–288 (2001).
[1.12] G.D. Wilk, R.M. Wallace and J.M. Anthony, High-k dielectrics: current status and materials properties considerations. J. Appl. Phys. 89 (2001), pp.
60
5243–5275.
[1.13] E.P. Gusev, E. Cartier, D.A. Buchanan, M. Gribelyuk, M. Copel, H.
Okorn-Schmodt et al., Ultrathin high-k metal oxides on silicon: processing, characterization and integration issues. Microelectron. Eng. 59 (2001), pp.
341–349.
[1.14] S.M. Sze, Evolution of nonvolatile semiconductor memory: from floating-gate to single-electron memory cell. In: S. Luryi, J. Xu and A.
Zaslavsky, Editors, Future trends in microelectronics, John Wiley & Sons (1999).
[1.15] I. Fujiwara, H. Aozasa, A. Nakamura and Y. Hayashi, 0.13 μm MONOS single transistor memory cell with separated source lines. Pros. IEDM 98 955 (1998), pp. 36.7.1–36.7.4.
[1.16] S. Minami and Y. Kamigaki, A novel MONOS nonvolatile memory device ensuring 10-year data retention after 107 erase/write cycles. IEEE Trans.
Electron Dev. 40 (1993), pp. 2011–2017.
61
[1.17] J. Bu and M.H. White, Design considerations in scaled SONOS nonvolatile memory devices. Solid State Electron. 45 (2001), pp. 113–117.
[1.18] K.T. Chang, W.M. Chen, C. Swift, J.M. Higman, W.M. Paulson and K.M.
Chang, A new SONOS memory using source-side injection for programming.
IEEE Electron Dev. Lett. 19 (1998), pp. 253–255.
[1.19] I. Bloom, P. Pavan and B. Eitan, NROM––a new non-volatile memory technology: from device to product. Microelectron. Eng. 59 (2001), pp.
213–223.
[1.20] H.C. Wann and C. Hu, High-endurance ultra-thin tunnel oxide in MONOS device structure for dynamic memory application. IEEE Electron Dev. Lett.
16 (1995), pp. 491–493.
[1.21] Y.T. Hou,M.F. Li,H.Y. Yu,Y. Jin and D.-L. Kwong, Quantum tunneling and scalability of HfO2 and HfAlO gate stacks. IEEE Electron Dev. Meeting
IEDM (2002), pp. 731–734.
[1.22] Gritsenko VA, Nasyrov KA. Transport and defects in advanced gate
62
dielectrics. Abstract of Conference “Nano and Giga Challenges in Microelectronics”, September 10–13, 2002, Moscow, Russia. p. 131
[1.23] Lee C, Hur S, Shin Y, Choi J, Park D, Kim K. A novell structure SiO2/SiN/
High-k dielectrics, Al2O3 for SONOS type flash memory. Abstract of the 2002 International Conference on Solid State Devices and Materials, 2002, Nagoya, Japan. p. 162
[1.24] Gritsenko VA, Nasyrov KA, Novikov YuN. A new low voltage fast SONOS memory with High-K dielectrics. Abstract of the 12th Workshop on dielectrics in microelectronics, November 18–29, 2002, Grenoble, France. p.
179.
[1.25] Gritsenko VA, Nasyrov KA, Novikov YuN. Unpublished.
[1.26] V. A. Gritsenko, K. A. Nasyrov, Yu. N. Novikov, A. L. Aseev, S. Y. Yoon, Jo-Won Lee, E. -H. Lee and C. W. Kim, A new low voltage fast SONOS memory with high-k dielectric, Solid-State Electronics 47 (2003), pp.
1651-1656
63
Chapter 2
[2.1] D. A. Buchanan, “Scaling the Gate Dielectric: Materials, Integration, and Reliability,” IBM J. Res. & Dev. 43, 245–264 (1999).
[2.2] E. P. Gusev, H.-C. Lu, E. L. Garfunkel, T. Gustafsson, and M. L. Green,
“Growth and Characterization of Ultrathin Nitrided Silicon Dioxide Films,”
IBM J. Res. & Dev. 43, 265–286 (1999)
[2.3] K. Hubbard and D. Schlom, “Thermodynamic Stability of Binary Oxides in Contact with Silicon,” J. Mater. Res. 11, 2757 (1996).
[2.4] E. Gusev, E. Cartier, D. Buchanan, M. Gribelyuk, M. Copel, H.
Okorn-Schmidt, and C. D'Emic, “Ultra High-k Metal Oxides on Silicon:
Processing, Characterization, and Integration Issues,” Proceedings of the
Conference on Insulating Films on Semiconductors (INFOS), 2001.
[2.5] J. Robertson, “Band Offsets of Wide-Band-Gap Oxides and Implications for Future Electronic Devices,” J. Vac. Sci. Technol. B 18, 1785–1791 (2000).
[2.6] D. Frank, R. Dennard, E. Nowak, P. Solomon, Y. Taur, and H.-S. Wong,
64
“Device Scaling Limits of Si MOSFETs and Their Application Dependencies,” Proc. IEEE 89, 259–288 (2001).
[2.7] D. Frank and H.-S. P. Wong, “Analysis of the Design Space Available for High-k Gate Dielectric in Nanoscale MOSFETs,” Proceedings of the IEEE
Silicon Nanoelectronics Workshop, 2000, pp. 47–48.
[2.8] S. M. Sze, Physics of Semiconductor Devices, Wiley, New York, 1981
[2.9] T. Ning, C. Osburn, and H. Yu, “Emission Probability of Hot Electrons from Silicon into Silicon Dioxide,” J. Appl. Phys. 48, 286 (1977).
65
Chapter 3
[3.1] Marvin H. White, Yang (Larry) Yang, Ansha Purwar, Margaret L. French, ” A Low Voltage SONOS Nonvolatile Semiconductor Memory Technology ”,
IEEE transactions on components, packaging, and manufacturing
technology—PART A, VOL. 20, NO. 2, JUNE 1997.
[3.2] Shin-ichi Minami and Yoshiaki Kamigaki, ” A Novel MONOS Nonvolatile Memory Device Ensuring 10-Year Data Retention after 107 Erase/Write Cycles ”, IEEE Transactions on Electron Devices, VOL. 40, NO. 11, NOVEMBER 1993.
[3.3] C. C.-H. Hsu et al., Exf. Ah. SSDM, Tsukuba, p. 140.1992.
[3.4] T. Ohnakado et al., in IEDM Tech. Dig., p. 279.1995.
[3.5] Jao-Hsian Shiue et. al. "A study of interface trap generation by Fowler-Nordheim and Substrate-hot-carrier stresses for 4-nm thick gate oxides," in IEEE transactions on electron devices, vol. 46, NO.8, August 1999.
66
[3.6] O. Takahiro, T. Hiroshi, K. Hayashi, and M. D. K. Kaisha, “Non-volatile semiconductor memory device capable of high speed programming/erasure, U.S. patent no. 5818761,”, Oct. 6, 1998.
[3.7] D. P. Shum et al., “A novel band-to-band tunneling induced convergence mechanism for low current, high density Flash EEPROM applications,” in
IEDM Tech. Dig., 1994, pp. 41–44.
[3.8] C.-Y. Hu. et al., “Substrate-current-induced hot electron (SCIHE) injection: A new convergence scheme for Flash memory,” in IEDM Tech. Dig., 1995, pp.
283–287.
[3.9] T. S. Chen, K. H. Wu, H. Chung, and C. H. Kao, “performance improvement of SONOS memory by bandgap engineer of charge-trapping layer“, IEEE
Electron. Device Lett., vol.25, no.4, pp. 205-207, Apr. 2002.
[3.10] Marvin H. White, Yang (Larry) Yang, Ansha Purwar, Margaret L. French, ” A Low Voltage SONOS Nonvolatile Semiconductor Memory Technology ”,
IEEE transactions on components, packaging, and manufacturing
67
technology—PART A, VOL. 20, NO. 2, JUNE 1997.
[3.11] T. Sugizaki, M. Kohayashi, M. Ishidao, H. Minakata, M. Yamaguchi, Y.
Tamura, Y. Sugiyama, T. Nakanishi, and H. Tanaka, ” Novel Multi-bit SONOS Type Flash Memory Using a Highk Charge Trapping Layer”,
Symposium on VLSl Technology Digest of Technical Papers 2003.
[3.12] Marvin H. White, Dennis A. Adams, James R. Murray, Stephen Wrazien, Yijie (Sandy) Zhao, Yu (Richard) Wang, Bilal Khan, Wayne Miller, Rajiv Mehrotra1, ” Characterization of Scaled SONOS EEPROM Memory Devices for Space and Military Systems ”, IEEE 2004.
[3.13] G. D. Wilk, R. M. Wallace, J. M. Anthony, ”High-k gate dielectrics: Current status and materials properties considerations ”, Applied Physics Review, vol.89, no.10,pp.5243-5275, May 2001.
[3.14] T. Ohnakado et al., “Novel electron injection method using band-to-band tunneling induced hot electron (BBHE) for Flash memory with a p-channel cell,” IEDM Tech. Dig., pp. 279–282, 1995.
68
[3.15] C.-G. Hwang: Proc. IEEE 91 (2003) 1765.
[3.16] K. Kim, J. H. Choi, J. Choi and H.-S. Jeong: VLSI Technology (VLSITSA-Tech), 2005, p. 88.
[3.17] J.-H. Park, S.-H. Hur, J.-H. Lee, J.-T. Park, J.-S. Sel, J.-W. Kim, S.-B. Song, J.-Y. Lee, J.-H. Lee, S.-J. Son, Y.-S. Kim, M.-C. Park, S.-J. Chai, J.-D. Choi, U.-I. Chung, J.-T. Moon, K.-T. Kim, K. Kim and B.-I. Ryu: IEDM Tech.
Dig., 2004, p. 873.
[3.18] M. H. White, D. A. Adams and J. Bu: IEEE Circuits Devices 16 (2000).
[3.19] S.-I. Minami and Y. Kamigaki: IEEE Trans. Electron Devices 40 (1993) 2011.
[3.20] C. H. Lee, K. I. Choi, M. K. Cho, Y. H. Song, K. C. Park and K. Kim: IEDM Tech. Dig., 2003, p. 26.5.1.
簡歷
姓 名 : 顧 春 瑀 性 別 : 男
出生日期 : 中華民國七十一年二月十一日 籍 貫 : 安徽省 懷遠縣
地 址 : 桃園縣桃園市豐林里 11 鄰三和街 74 巷 2 弄 3 號 學 歷 : 國立臺灣大學 地理環境資源學系
( 民國 95 年 6 月 )
國立交通大學 電子研究所固態組 碩士班 ( 民國 97 年 8 月 )
論文題目 : 利用高介電長數 HfAlO 之元素含量做為阻擋層應用在非揮發性 記憶體上之研究
Study on High-k Gate dieletric Hf1-xAlxO for Blocking layer of SONOS Non-Volatile Memory
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