2.3-1 Electrical characteristics of nMOSFETs with different
High-K RTA temperature
The C-V curves in Fig. 2-6 indicate not obvious change of EOT with different
RTA temperature, this means the thickness of high-K dielectric HfO2 was not changed
by post deposition anneal process. In Fig. 2-7 and Fig. 2-8 we also observe both drain
current and transconductance have an apparent increase on the 900 ℃ RTA
temperature sample. Fig. 2-9 and Fig. 2-10 depict the results of driving current and
maximum transconductance versus different channel length. When channel length
becomes shorter, the increase is more apparent.
Fig. 2-11 and Fig. 2-12 show the maximum transconductance versus various
channel width and area. We can see that the 900℃ RTA temperature sample has
obvious increase on maximum transconductance no matter in different channel length,
width and area. The driving current and transconductance of 900℃ RTA temperature
sample are higher than 600℃ RTA temperature sample. This is because the better
densification in 900℃ RTA temperature sample we get. By the way, we can extract
the interfacial trap density by charge pumping method. Fig. 2-13, Fig. 2-14 show the
charge pumping current Icp for device with 600℃ and 900℃ RTA temperature, and
Fig.2-15 shows the comparison of charge pumping current Icp between the devices
with different RTA temperature. And then we can extract the value of Nit by equation
(2-1). Then we get Nit valuesof 1.818x1012cm-2 and 1.197x1012 cm-2 with 600℃ and
900℃ RTA temperature respectively.
Fig. 2-16 shows that mobility versus effective electric field, we find the higher
mobility we get in 900℃ sample. This is also caused by the better performance of
higher high-K RTA temperature for the device. But using split-CV method wouldn’t
calculate short channel device because the capacitance is too small and disturbance is
too large, then we can’t get it by HP4284 LCR meter. Therefore, we only can measure
the large dimensional device.
2.3-2 Conduction mechanism of nMOSFETs with Oxynitride and
HfO
2gate stack
The carrier type involved in the leakage current through HfO2/SiON dielectric
layers have also been investigated for unstressed nMOSFETs, using carrier separation
method [19]. The contributing carrier of the gate leakage current can be separated into
holes and electrons. Fig. 2-17 shows carrier separation results under the inversion
region, and Fig. 2-18 shows carrier separation results under the accumulation region
for N+-gated nMOSFETs with HfO2/SiON gate stack, both with 600℃ and 900℃
RTA temperature. It is found that the source/drain current ISD dominates the leakage
current under inversion region, and the substrate current IB dominates the leakage
under accumulation region. This indicates electrons from S/D that tunnel through gate
dielectric is the dominant component of conduction mechanism under inversion
region , while holes from gate electrode that tunnel through gate dielectric is the
dominant component of conduction mechanism under accumulation region.
This could be explained by band-diagrams shown in Fig. 2-19(a) and carrier
separation experiment shown in Fig. 2-19(b). The substrate current IB corresponds to
the hole current from the gate , while the source/drain current ISD corresponds to the
electron current from Si substrate under inversion region. Hole supply from the gate
conduction band in nMOSFETs is limited by the generation rate of minority holes in
n+ gate. In other words, the probability of carriers from S/D that tunnel through gate
dielectric is strongly affected by tunneling distance and barrier height [20]. Because of
the asymmetry of the HfO2/SiON band structure, it is more difficult for holes from
gate to tunnel through gate dielectrics compared with electrons from the channel. In
nMOSFETs, electron current from the channel is the predominant injection current
under stressing. The leakage component under accumulation region can also be
explained by band-diagrams shown in Fig. 2-20(a), and the current component flow in
carrier separation experiment is shown in Fig. 2-20(b).
In Fig. 2-21 and Fig. 2-22 , the gate current Ig as a function of Vg for the
HfO2/SiON layer is measured from temperature up to 125℃, both under inversion
region and accumulation region for two samples. We obtain the leakage current is
temperature dependent that increases with increasing temperature. It implies that the
conduction mechanisms of current must be trap-related like schottcky emission, i.e.,
trap-assisted tunneling (TAT), Frenkel-poole emission, etc.
The gate leakage current for devices with HfO2/SiON gate stack is composed of
two types of current, i.e., hole current and electron current. To determine the
conduction process in the HfO2/SiON dielectric, Frenkel-poole (F-P) plots are fitted
for hole current and electron current, respectively, for both samples.
The current from Frenkel-poole emission is of the form:
exp(2 B)
⇒ intercept gives the Barrier height ( B
B
permittivity, εinsis HfO2 dielectric constant, kB is Boltzmann constant , and T is the
temperature measured in Kelvin.
As shown in Fig. 2-20 and Fig. 2-21, are both under inversion region and
accumulation region, excellent linearity for each current characteristic has been
observed for two samples. This tendency indicates that both samples exhibit the
Frenkel-Poole conduction mechanism for the gate leakage current. Both the electron
and hole conduction mechanisms are the same, and the result agree well with the F-P
conduction mechanism.
2-4 Summary
In this work, we show the initial electrical properties of the device with different
high-k RTA temperature. We found the 900℃ sample has the perfect performance
about the higher driving current, higher transconductance, and higher mobility
compared to 600℃ sample. In C-V curve, the EOT is almost equivalent for both
sample, it seems the EOT was not changed by a higher PDA temperature process. We
use carrier separation to verify that devices with different high-K RTA temperature,
we found gate leakage current is the same with both devices. And conduction
mechanism is Frankel-Poole emission.
Table. 1 SIA’s NTRS Projections [13]
Tech. Generation (nm) 100 70 50
Min. VDD (V) (desktop) 1.2-0.9 0.9-0.6 0.6-0.5 µprocessor (Gate Length) 70nm 50nm 30nm
Tox equivalent (nm) 1.5-2 <1.5 <1.0 Nominal Ion @25℃
(µA/µm) (NMOS/PMOS)
600/280 600/280 600/280
Max. Ioff @25℃ for sub-nominal device (nA/µm)
3 3 10
Fig. 2-1 Gate leakage current vs. EOT for high k gate stack with poly-Si and metal gates.
․ Standard LOCOS Isolation
․ RCA clean and HF-last dip
․ Chemical Oxide Growth : H2O2 for 20min
․ Nitridation in NH3 ambient (120mTorr and 700℃ for 30min)
․ MOCVD of 30 nm HfO2
․ PDA 600℃, 900℃ 30sec in O2 ambient
․ PDA 600℃ 30sec in N2 ambient
․ Poly-Si deposition 200nm and pattering
․ Spacer formation, S/D extension, S/D implant
․ Dopant activation : 950℃ , 30sec
․ Passivation layer : SiO2 500nm
․ Metallization : Al-Si-Cu 900nm
․ Forming gas sintering : 400℃ , 30min
Fig. 2-2 The process flow of nMOSFETs with HfO2/SiON gate stack.
Fig. 2-3 Schematic cross-section of nMOSFETs with HfO2/SiON gate stack.
Si
FOX FOX
S D
Fig. 2-4 Basic experimental set-up of charging pumping measurement for nMOSFETs.
S
HP
GPIB 9-substrate
n+
Source
n+
Drain
n+ poly-Si e
-h+
HP 81110A Pulse Generator
(a)
(b)
Fig. 2-5 Configuration for (a)gate-to-channel, and (b)gate-to-substrate capacitance measurement.
P
+P
+P
+N
P
+P
+P
+N
-3 -2 -1 0 1 2 3 0.2
0.4 0.6 0.8 1.0 1.2 1.4
EOT 2.62nm 2.61nm
L/W=50/ 50um 600oC 900oC
Capacitance ( uF/cm 2 )
Vg(V)
Fig. 2-6 C-V curves for nMOSFETs.
-2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
Fig. 2-7 Id-Vg & Gm-Vg characteristics of devices with different RTA temperature.
0.0 0.5 1.0 1.5 2.0 2.5 3.0
Fig. 2-8 Id-Vd characteristics fro devices with different RTA temperature.
0.5V 1V 1.5V Vg-Vt=2V
0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2
Fig. 2-9 Compared Idlinear with channel length for device with different RTA temperature.
Fig. 2-10 Compared Gmmax with different channel length for device with different RTA temperature.
0 2 4 6 8 10
Fig. 2-11 Compared Gmmax with channel width for device with different RTA temperature.
0.5X10 1X10 2X2 2X10 10X10 50X50100X100 0
Fig. 2-12 Compared Gmmax with area for device with different RTA temperature.
0.0 0.5 1.0 1.5 2.0 2.5 3.0
Fig. 2-13 Charge pumping current for device with 600℃ RTA temperature sample.
0.0 0.5 1.0 1.5 2.0 2.5 3.0
Fig. 2-14 Charge pumping current for device with 900℃ RTA temperature sample.
0.0 0.5 1.0 1.5 2.0 2.5 3.0
Fig. 2-15 Compared charge pumping current for device with different RTA temperature.
Fig. 2-16 Compared electron mobility with effective field for device with different RTA temperature.
0 2 4 6 8
Fig. 2-17 Carrier separations with 600℃ RTA temperature sample under (a) inversion (b) accumulation region.
0 1 2 3 4 5 6 7 8
Fig. 2-18 Carrier separations with 900℃ RTA temperature sample under (a) inversion (b) accumulation region.
(a)
(b)
Fig. 2-19 n+-gated nMOSFET with HfO2/SiON gate stack under inversion region (a) band diagrams, and (b) Schematic illustration of carrier separation
experiment.
NMOSFET
n
+Gate
HfO
2e
-I
SD(-)
h
+I B(-)
P-Sub
Interfacial layer
n
+n
+n
+Vg(-) Hole
injection
Electron current Electron
injection (+)I
SD(+)I
BP
Inversion layer(a)
(b)
Fig. 2-20 n+ -gated nMOSFET with HfO2/SiON gate stack under accumulation region (a)band diagrams , and (b)Schematic illustration of carrier separation experiment.
NMOSFET
n
+Gate
HfO
2e
-ISD(+)
h
+I B(+)
p-Sub
Interfacial layer
n
+n
+n
+Vg(+) Hole
injection
Electron current Electron
injection (-)I
SD(-)I
BP
Inversion layer0 1 2 3 4 5 6 7 8
Fig. 2-21 Gate leakage current versus gate bias for device with 600℃ RTA temperature.
0 1 2 3 4 5 6 7 8
Fig. 2-22 Gate leakage current versus gate bias for device with 900℃ RTA temperature.
Chapter 3
Reliability characteristics of nMOSFETs with Oxynitride and HfO
2gate stack
3.1 Introduction
One of the main constraints for scaling down MOSFET’s dimensions is the
device instability. Degradation of MOSFET’s can be caused by hot carrier stressing
[20] ~ [24], Fowler-Nordheim tunneling injection [25] ~ [29] and the bias temperature
stressing (BTS) [30] ~ [38]. In this chapter, we discuss about the latter one. In CMOS
technology, the BTI issue is a very important reliability issue. Although the BTI issue
is one of the earliest identified reliability problems, it has received relatively less
attention. However, recent experimental results [36] have shown that the BTI can still
make a considerable contribution to the degradation of small size MOSFET’s.
However, in early research, the NBTI issue on SiO2 dielectric caused more significant
degradation than PBTI does. While the NBTI includes both interface state generation
and positive charge formation in the gate oxide, the PBTI only exists in the form of
donor-like interface state generation. These donor-like interface states are localized
symmetrically near the source and drain junctions and are negligible in the middle of
the channel [39].
will cause the threshold voltage shift with stressing time. This phenomenon in high-k
dielectric films with metal gated transistors has been identified as one the critical
reliability issues that must be solved to implement high-k based CMOS transistors
[40]. Previous reports in the literature on metal gate HfO2 based MOSFETs [41] ~ [43]
have observed that nMOS devices show significantly higher threshold voltage (Vt)
instability as compared to pMOS devices. This is contrary to observations in
conventional gate oxide films. In conventional gate oxides, nMOS under positive bias
temperature instability (PBTI) stress shows little or no threshold voltage degradation
and hence is not a reliability concern. However, pMOS under negative bias
temperature instability (NBTI) stress posses a continued reliability problem as the
gate oxide is scaled thinner. In this study of HfO2 based poly gate MOSFETs, PBTI is
the major issue that must be solved to meet the required reliability specifications.
3.2 Measurement setup
Constant voltage stress (CVS) is method to evaluate the reliability of devices as
it causes threshold voltage to shift with electrical stressing. A constant voltage stress is
applied to device gate from Vg=2V~3V, while source/drain and substrate are grounded.
We measured Id-Vg and charging pumping during stress intervals. Id-Vg measurements
are used to evaluate Gm variation and threshold voltage shift and charging pumping
measurements are used to obtain interface density generation. Moreover, the total trap
density which consists of interface trap density and bulk trap density is calculated
from threshold voltage shift before and after stress. It expresses as follows
total th/ G
N C V qA
∆ = ∆
and bulk trap density also can be calculated as follows
bulk total it
N N N
∆ = ∆ − ∆
Positive bias temperature instability (PBTI) is an important reliability issue as it
causes the threshold voltage to shift with electrical stressing at elevated temperature.
To evaluate device degradations due to the bias temperature stress (BT), the gate
electrode of the device was subjected to stress condition with negative bias (3V)
varying from 25℃ to 125℃, while the drain/source and substrate were all grounded.
The detail process is the same as CVS process, except temperature variation. Fig. 3-1
shows the experimental framework of our measurements.
3.3 Reliability of device with different High-K RTA temperature
3.3-1 CVS of devices with different High-K RTA temperature
Fig. 3-2 (a) and Fig. 3-2 (b) expresses Id-Vg characteristics before stress and
after stress at 25℃. We observe that there are both Vth shift after stress on 600℃
sample and 900℃ sample. This means that interface state generation plays no
significant role, rather, charge trapping in the bulk dielectric is the primary
mechanism leading to CVS issues in high-k dielectrics. Vth shift of the 600℃ sample
is found to be slightly larger.
The threshold voltage shift (ΔVth) is measured with respect to the Id-Vg
characteristics with different high-K RTA temperature are shown in Fig. 3-3 in linear
scale. The threshold voltage shifts toward negative gate voltage (ΔVth > 0), thus
implying that net negative charges are trapped in the gate dielectric layer as devices is
measured. It is clear that 900℃ sample always shows smaller ΔVth than the 600℃
sample under different stress voltages as shown.
To further gain insights into the degradation mechanism during voltage stressing,
the interface state generation, ΔNit, is plotted as a function of the stress time in Fig
3-4 (a) 600℃ sample ,and (b) 900℃ sample ,respectively. We found that 900℃
sample has lower shift of ΔNit, there is an excellent reliability performance especially
under CVS=3V.
Fig. 3-5 shows the overall comparison between both sample under CVS
measurement at 25℃. We can see the 900℃ sample shows the less threshold voltage
shift and less interface trap density shift compared to 600℃ sample.
3.3-2 PBTI of devices with different High-K RTA temperature
Fig. 3-6(a) and (b) expresses Id-Vg characteristics before stress and after stress at
125℃. Compared Fig. 3-2 (a) and (b), we found that there is observable change in
ΔVth at high temperature, compared to that at room temperature, indicating that ΔNit
increases with increasing temperature. This phenomenon is consistent with our results
as shown in Fig. 3-8.
Fig. 3-7 compared the PBT-Stress-time dependence of threshold voltage shift for
HfO2/SiON gate stack device with different high-K RTA temperature. A significantly
smaller Vth shift is observed for the 900℃ sample under the BT stress, Vg=3V at
25℃ and 125℃. Such phenomena can be attributed to the better thermal stability of
oxynitride interfacial layer under higher PDA temperature annealing. This indicates
that the Vth degradation could be more severe for the devices under BT stress at high
temperature [44]. The exponential value is temperature dependent relative to bulk trap
generation. Fig. 3-9 shows the overall comparison between both sample under PBTI
measurement. We can see the 900℃ sample shows the less threshold voltage shift
and less interface trap density shift under 75℃ compared to 600℃ sample.
We found Vth degradation during PBTI stressing is serious in 600℃ sample
than 900℃ sample. According to Wang Hsin Chih’ paper, we found that interface
states are not the main reason of threshold voltage shift. This indicates that charge
trapping in bulk is the main reason of threshold voltage shift [45]. The research has
pointed out that amount of bulk traps is one to two order higher than amount of
interfacial traps [46].
3.4 Summary
In this work, we found the 900℃ sample has less degradation than 600℃
sample. From CVS measurement, the value of is ΔNit larger than traditional SiO2
dielectric, but we still have the stable ΔNit after stress 1000s. We found the higher
high-K RTA temperature makes a better performance to reduce ΔVth. And the
exponential value of ΔVth is voltage dependent. From PBTI measurement, the
exponential value of ΔVth is voltage and temperature dependent. As a result, we can
confirm that charge traps in the bulk of HfO2/SiON gate stack are related to the
instability about threshold voltage shift and interface state shift. We can expect a
continuous distribution of charge trapping cross sections, instead of a discrete-value
capture cross section, in HfO2 high-K film [47]. Our experimental also shows that
electron trapping is dominant in DC stress.
Fig. 3-1 Basic measurement method for (a) CVS (constant voltage stress), and (b) PBTS (negative bias temperature stress).
n+
CVS for gate electrode CVS = 2, 3V
CVS for gate electrode CVS = 3V
Change T
T=25、75、125℃
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
Fig. 3-2 Id-Vg characteristics for n+-gated nMOSFETs before and after stress 1000s at 25℃ (a) 600℃ sample, and (b) 900℃ sample.
Vth
Vth
10-1 100 101 102 103 104 40
45 50
T=25oC 600oC sample
Vg=2V Vg=3V
∆ Vth(m V )
Stress Time
(a)
10-1 100 101 102 103 104
10 20 30 40
Vg=2V Vg=3V T=25oC 900oC sample
∆ V th (m V)
Stress Time (s)
(b)
Fig. 3-3 Threshold voltage shift as a function of stress time, stressed at 25℃, Vg=2~3V in linear scale (a) 600℃ sample, and (b) 900℃ sample.
10-1 100 101 102 103 104
Fig. 3-4 Interface trap density shift increase as a function of stress time (a) 600℃
sample, and (b) 900℃ sample.
1 10 100 1000
Fig. 3-5 Compared of CVS measurement for devices with different RTA temperature (a) threshold voltage shift (b) interface trap density shift as a function of stress time.
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
Fig. 3-6 Id-Vg characteristics for n+-gated nMOSFETs before and after stress 1000s at 125℃ (a) 600℃ sample, and (b) 900℃ sample.
Vth
Vth
10-1 100 101 102 103 104
Fig. 3-7 Threshold voltage shift as a function of stress time under BTS at different stress temperature, Vg=3V in linear scale (a) 600℃ sample, and (b) 900℃
sample.
10-1 100 101 102 103 104
Fig. 3-8 Interface trap density shift as a function of stress time under BTS at different stress temperature, Vg=3V (a) 600℃ sample, and (b) 900℃ sample.
0.1 1 10 100 1000 10000
Fig. 3-9 Compared of PBTI issues for device with different RTA temperature (a) threshold voltage shift (b) interface trap density shift as a function of stress time.
Chapter 4
Conclusion and Future Work
4.1 Conclusion
Oxynitrides with high nitrogen concentration distributed close to the surface
were investigated. We propose an alternative approach for forming a high-nitrogen
ultrathin oxynitride gate dielectric is demonstrated.
In this thesis, the effect of high-K RTA temperature on the HfO2 gate stack were
investigated. Several important phenomena were observed and summarized as
follows:
First, we have investigated its basic electrical properties. According to the initial
electrical properties of the devices indicated the higher high-K RTA temperature has
the better performance. The gate leakage current is analyzed by the carrier separation
measurement, and can be explained by the band structure of the gate stack. The
source/drain current ISD that correspond to the electron current dominates the leakage
under inversion region, while the substrate current IB that indicated the hole current
dominants the leakage current under accumulation region. All leakage current can be
categorized by fitting to be of Frenkel-Poole type.
Secondly, we have studied the CVS and PBTI mechanisms of polysilicon gate
and HfO2 gate dielectric with 600℃ and 900℃ high-K RTA temperature. ΔVth is
primarily caused by the charge traps in the HfO2 dielectric, not by the interfacial
degradation. The higher high-K RTA temperature is effective in densifying the HfO2
gate dielectric and showed the better performance.
4.2 Future Work
There are many issues and measurement skills that we can’t discuss completely.
We list some goals for future work as follows.
1. HRTEM is used to verify real thickness and estimate value of the
dielectric constant for HfO2/SiON gate stack.
2. SIMS analysis is used to prove nitrogen exist on the surface close to the
gate dielectric.
3. In actual CMOS circuit operation, AC gate bias with specific frequency
and duty cycle is usually utilized. Therefore, AC stress with Dynamic AC
stress application is more realistic and can provide additional insights into
the trapping behavior.
4. Fast transient pulsed Id-Vg measurement is also used to evaluate
charge-trapping phenomena precisely.
References
[1] M. Koyama, K. Suguro, M Yoshiki, Y. Kamimuta, M. Koike, M. Ohse, C. Hongo and A. Nishiyama, “Thermally stable ultra-thin nitrogen incorportated ZrO2 gate dielectric prepared by low temperature oxidation of ZrN,” in IEDM Tech, Dig., pp.20.3.1-20.3.4, 2001.
[2] E. P. Gusev, D. A. Buchanan, E. Cartier, A. Kumar, D. DiMaria, S. Guha, A.
Callegari, S. Zafar, P. C. Jamision, D. A. Neumayer, M. Copel, M. A. Gribelyuk, H. Okorn-Schmidt, C. D Emic, P. Kozlowski, K. Chan, N. Bojarczuk, L. –A.
Ragnarsson and Rons, “Ultrathin high-gate stacks for advanced CMOS devices,”
in IEDM Tech. Dig., pp. 20.1.1-20.1.4, 2001.
[3] W. Zhu, T. P. Ma, T. Tamagawa, Y. Di, J. Kim, R. Carruthers, M. Gibson and T.
Furukawa, “HfO2 and HFAlO for CMOS: thermal stability and current transport,”
in IEDM Tech. Dig., pp. 20.4.1-20.4.4, 2001.
[4] L. Kang, K. Onishi, Y. Jeon, Byoung Hun Lee, C. Kang, Wen-Jie Qi, R. Nieh, S.
Gopalan, R Choi and J. C. Lee, “ MOSFET devices with polysilicon on single-layer HfO2 high-dielectrics,” in IEDM Tech. Dig., pp. 35-38, 2000.
[5] Rino Choi, Chang Seok Kang, Byoung Hun Lee, K. Onishi, R. Nieh, S. Gopalan, E. Dharmarajan and J. C. Lee, “High-quality ultra-thin HfO2 gate dielectric MOSFETs with TaN electrode and nitridation surface preparation,” in IEDM Tech.
Dig., pp.15-16, 2001.
[6] Z. J. Luo, T. P. Ma, E. Cartier, M. Copel, T. Tamagawa and B. Halpern, “Ultra-thin ZrO2 (or silicate) with high thermal stability for CMOS gate applications,” in Symp. on VLSI Technology, pp. 135-136, 2001.
[7] International Technology Roadmap for Semiconductor, 2004.
[8] See http://public.itrs.net/for most recent updates to the International Technology Roadmap for Semiconductors.
[9] Institute of photo electron in Tatung University.
[10] C. S. Kang, H. Cho, R. Choi, Y. Kim, C. Y. Kang, S. J. Rhee, C. Choi, M. S.
Akbar, and J. C. Lee, “The electric and material characterization of HfO2 gate dielectrics with TaN-gate electrode,” IEEE Trans. Electron Devices, vol. 51, pp.
220-227, Feb 2004.
[11] C. S. Kang, H. Cho, K. Onishi, R. Choi, Y. H. Kim, R. Nieh, J. Han, S. Krishnan,
[11] C. S. Kang, H. Cho, K. Onishi, R. Choi, Y. H. Kim, R. Nieh, J. Han, S. Krishnan,