To verify the chip design, we first measured the small signal S-parameters. Fig. 3.1
shows the on-wafer measurement data, which show a 20 dB gain and 17 dB input
and output return loss- this is consistence with EM post-simulation data.
1 2 3 4 5 6 7 8
-40 -30 -20 -10 0 10 20
S11 S22 S21
Symbol:measured data Line: modeled data
d B
Frequency (GHz)
Fig. 3.1. Measured and simulated gain and return loss for CMOS PA.
Fig. 3.2 shows the measured RF power results of the amplifier. The output power
at 1 dB compression (P1dB) increases with increasing bias voltage from conventional
1.8, 2.5 to 2.75 V. Such increase of desired higher output RF power is consistent with
- 22 -
simulation. Under 2.5 V bias operation, a P1dB of 20.8 dBm and power gain of 20 dB
are measured with 30% PAE. The P1dB increases to 21.5 dBm at higher 2.75V bias
condition with still compatible 19.6 dB power gain and 29.6% PAE.
Good adjacent channel power ratio (ACPR) is an important linearity factor for PAs.
Fig. 3.3 shows the measured ACPR with standard W-CDMA π/4 QPSK modulation on
different bias voltage. Here the ACPR improves with increasing operation voltage
from 1.8, 2.5 to 2.75V monotonically. At the 2.75 V bias voltage, an ACPR of -56 dBc
at 0 dBm output power or -30 dBc at 20 dBm output power was measured, which is
competitive to the data of the power amplifiers designed for better linearity [15]. In
addition, IP3 point is an important factor, the Fig.3.4 ~ Fig.3.6 show up the IP3 point
with different supply voltage. The output IP3 point of 1.8V, 2.5V and 2.75V is 22dBm,
26dBm and 36dBm. So it shows that the linearity increases with larger supply
voltage.
- 23 -
-10 -5 0 5 10
8 10 12 14 16 18 20 22
24 measurement 2.5V
measurement 2.75V simulation 2.5V simulation 2.75V
Output Power (dBm)
Input Power (dBm)
Power-Added Efficiency (%)
Gain (dB)
0 10 20 30 40 50 60
Fig. 3.2. Measured and simulated RF output power, gain and PAE of designed PA using high breakdown voltage asymmetric-LDD MOSFETs.
-10 0 10 20
-60 -40 -20
ACPR (dBc)
OUTPUT POWER (dBm) VDD =1.8V
VDD = 2.5V VDD = 2.75V
fi Fig. 3.3. Measured ACPR of designed PA using high breakdown voltage
asymmetric-LDD MOSFETs.
- 24 -
-12 -10 -8 -6 -4 -2 0 2 4 6 8 10 12
-50 -40 -30 -20 -10 0 10 20 30
O U T P U T P O W E R ( d B m )
INPUT POWER (dBm)
fund IM3 IM5
Fig. 3.4 measurement data of third order inter modulation with 1.8V supply voltage.
-12 -10 -8 -6 -4 -2 0 2 4 6 8 10 12
-50 -40 -30 -20 -10 0 10 20 30
O U T P U T P O W E R ( d B m )
INPUT POWER (dBm)
fund IM3 IM5
Fig.3.5 measurement data of third order inter modulation with 2.5V supply voltage.
- 25 -
-30 -25 -20 -15 -10 -5 0 5 10 15 20
-100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 10 20 30 40
O U T P U T P O W E R ( d B m )
INPUT POWER (dBm)
fund IM3 IM5
Fig. 3.6 measurement data of third order inter modulation with 2.75V supply voltag
Chapter 4
COMPARISON
The die photo of fabricated CMOS PA is shown in Fig. 2.16, which has a chip area of
1m×1.1m. Table 4.1 summarizes the performance comparison with reported CMOS
PA [10]-[16]. The fabricated PA using high breakdown voltage asymmetric-LDD
MOSFETs shows the large P1dB of 21.5 dBm, high gain of 20.4 dB, and good 29.6%
PAE at 2.4 GHz. Those power performances are better than other reported designs
shown in Table 4.1, with added merits of simple single-ended design, using standard
foundry technology and compact on-chip matching.
- 26 -
Table 4.1 The comparison table of Asymmetry MOS and conventional PAs.
Ref. Freq.
(GHz) voltage Pout (dBm) Gain (dB) PAE (%)
Width/Pow er density
by P1dB(W/m
m)
Matchin g
technolog y
[10] 5 1.8 19.2@1dB 7.1 17.5 1.28mm/0.065 On chip 0.18um [11] 5.2 1.8 17.4/15.4@1
dB 15.1 27.1 0.6mm/0.058 On chip 0.18um
[12] 5.8 1 20.5@1dB ~8 27
(Drain) 9.6mm/0.012 On chip 90nm
[13] 2.4/5.2 1.8 9.7@2.4GHz 19.5@5.2GHz
3.7@2.4GH z 24@5.4GHz
15.3@5.2
GHz 1.92mm/0.046 On chip 0.18um
[14] 3.7~8.
8 1.8 19
15.6@1dB 8.24 25 0.96mm/0.038 On chip 0.18um [15] 2~2.45 2.5 16.3@1dB 18 --- 4.2mm/0.01 Off chip 0.13um
[16] 2.4 2.5 20@1dB 11.2 28 0.96mm/0.1 Off chip 0.25um
This
work 2.4
2.5 22.7
20.8@1dB 20 30
2mm/0.071 On chip 0.18um
2.75 23.2
21.5@1dB 19.6 29.6
- 27 -
Chapter 5
CONCLUSION
We have designed an asymmetric-LDD MOS transistor which has ~twice drain
breakdown voltage to the conventional one. Besides, the power amplifier has been
designed by single ended on chip design and fabricated by TSMC 0.18um 1P6M
process without any process modification. The excellent power performance shows
20dB power gain, and 20.8dBm P1dB compression power and 22.7dBm saturate
output power with 30% PAE under 2.5V bias operation. And 20.4dB power gain,
21.5dBm P1dB compression power and 23.2dBm saturate output power with 29.6%
PAE under 2.75V bias operation. -41dBc ACPR at 15dBm output power, ~36dBm OIP3
with 2.75V supply voltage. The output power and linearity increase with larger
supply voltage, and PAE and power gain saturate at 2.75V. This research
demonstrated that the asymmetric-LDD MOS transistor successfully implemented on
a CMOS power amplifier with wonderful performance even with on chip matching
design. This design method has great opportunity to be future trend and realize SOC
of PA.
- 28 -
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