Chapter 2 Cable Discharge Test
2.3 S UMMARY
In this chapter, two kinds of the typical cable discharge tests have been introduced and discussed. One is to investigate the CDE robustness in Ethernet local area network (LAN), and another one is to measure CDE discharge waveforms of unshielded twisted pair (UTP) cables. The first kind of test result reveals how the influence of CDE can be reduced by way of IC design and process technology. From the second kind of test result, the pulse width of all discharge currents of these UTP cables is approximately ~475 ns. This pulse width provides us a way to find the efficient component-level measurement method for investigating CDE robustness of I/O devices in IC products.
Table 2.1
The descriptions for process technologies and IC designs of different types of Ethernet transceivers.
Type Process Technology IC Design
LXT970 0.6μm Single-Port
LXT974A 0.6μm Four-Port
LXT970-EPI 0.6μm (EPI) Single-Port
LXT974B 0.6μm Twisted-Pair Port
LXT9763 0.35μm Six-Port
Fig. 2.1 The test setup used to measure and analyze CDE in an Ethernet network [3], [4].
Fig. 2.2 The CDE voltage levels of Ethernet transceivers under different IC designs and process technologies [3], [4].
Fig. 2.3 Cable layout of unshielded twisted pair (UTP) [5, [6].
Fig. 2.4 Charging point [6].
Fig. 2.5 Discharging point [5], [6].
(a)
(b)
Fig. 2.6 Cable discharge waveforms when (a) unused pairs connected together and grounded and (b) unused pairs floating [5].
Chapter 3
Long-Pulse TLP (LP-TLP) Measurement Setup
3.1 TRADITIONAL TRANSMISSION LINE PULSING (TLP)SYSTEM
In order to reduce design cycle time for ESD protection circuits, the transmission line pulsing (TLP) system has been proposed to measure the snapback I-V characteristics and the secondary breakdown current (It2) of CMOS devices [10]-[12].
The measurement setup for the traditional TLP test is illustrated in Fig. 3.1. The TLP system provides a single and continually-increasing voltage pulse to the device-under-test (DUT). The pulse width is as short as 100 ns to simulate the HBM
ESD stress, as shown in Fig. 3.2. The relationship between the secondary breakdown current (It2) and the HBM ESD level (VESD) can be approximated as
VESD ≈ (1500 + Rdevice) × It2, (3.1) where Rdevice is the snapback turn-on resistance of the device-under-test. Because the relation between the secondary breakdown current and the HBM ESD level of protection devices is a linear function, the TLP system has been widely used to evaluate the component-level HBM ESD robustness of CMOS devices [13]-[15].
3.2 NEW LONG-PULSE TRANSMISSION LINE PULSING (LP-TLP) SYSTEM
3.2.1 Measurement setup of the proposed LP-TLP
By using the excellent characteristics of TLP system, the long-pulse transmission line pulsing (LP-TLP) system is proposed to evaluate CDE behavior of silicon device
and integrated circuits in this thesis. The proposed LP-TLP system with two kinds of long pulse widths (500 ns/1000 ns) is evidently different from the traditional TLP system with a short pulse width of 100 ns. The LP-TLP system with a pulse width of 500 ns is consistent to the pulse width (~475 ns) of CDE in Fig. 2.6 (a). Thus, the LP-TLP system can be utilized to examine the damage situation on the DUT under CDE stress. Fig. 3.3 sketches the measurement setup for the proposed LP-TLP test.
Besides, the actual measurement setup is shown in Fig 3.4. The measurement setup includes a diode, a load resistance (RL), a 50-m transmission line (or a 100-m transmission line), two switches (SW1 and SW2), a high-voltage DC supply, a current probe, a voltage probe, and an oscilloscope.
The diode and the load resistance (RL) are defined as the polarization end to absorb the reflection wave. The principle of LP-TLP operation is described as follows.
In the initial state, the switch SW1 is short-circuit and the switch SW2 is open-circuit.
Through high-voltage resistance RH, the high-voltage DC supply provides the transmission line with a fixed voltage. The switch SW1 is open-circuit and the switch SW2 is short-circuit in the next state. The stored energy on the transmission line transfers to the DUT by the electromagnetic wave, and then the current and voltage pulses on the DUT are measured by the oscilloscope to obtain the first group data of the LP-TLP measured I-V curve. Afterward, the switch SW1 returns to short-circuit and the switch SW2 reverts to open-circuit. Through the high-voltage resistance RH, the high-voltage DC supply provides the transmission line with a higher fixed voltage.
The second group of current/voltage data is measured by repeating the aforementioned steps. The foregoing procedures are continuously duplicated until all I-V characteristics are measured. However, a permanent damage happens when the DUT is over-heated. With the aid of LP-TLP system, the secondary breakdown point of semiconductor devices under CDE stress can be measured.
3.2.2 Verification on LP-TLP with a Load of 50-Ω Resistor
A 50-Ω resistor is used as the DUT to verify that the LP-TLP system can generate a long current pulse similar to cable discharge waveform. The LP-TLP measured current waveforms are shown in Figs. 3.5(a) and 3.5(b). When a 50-m transmission line is charged to 450 V, 640 V, and 880 V by the high-voltage DC supply, it will generates the corresponding LP-TLP currents of 6 A, 9 A, and 12 A into the 50-Ω resistor at DUT, respectively. So, the amplitude of current pulse is obviously increased while the charged voltage provided by the high-voltage DC supply is increased. Furthermore, the pulse width of these three current waveforms is 500 ns when the length of transmission line is 50 m, so the proposed LP-TLP system with a long current pulse width has been proven. If the length of long-pulse transmission line in the LP-TLP setup is 100 m, the generated current waveform has a pulse width of 1000ns, as shown in Fig. 3.5(b). Hence, it suggests that the LP-TLP pulse width is a function of the cable length of transmission line.
3.2.3 Verification on Gate-Grounded NMOS (GGNMOS)
A gate-grounded NMOS (GGNMOS) device, which has been widely used as the on-chip ESD protection device in CMOS ICs, is regarded as the DUT to demonstrate that LP-TLP system can accurately measure its snapback characteristics and secondary breakdown current (It2). The 500-ns LP-TLP measured I-V characteristic of GGNMOS with a device dimension of W/L= 240 μm/0.3 μm is shown in Fig. 3.6.
In addition, Figs. 3.7(a)-(f) exhibit the time-domain I-V waveforms of GGNMOS device at the corresponding points marked in Fig. 3.6. The I-V curves of GGNMOS device will shift from the initial point (A) to the trigger point (B) as the high-voltage DC supply continuously provides the higher energy. After passing through the trigger
point (B), the I-V curve will enter the snapback region because the parasitic lateral BJT in the GGNMOS device is turned on. The point C and the point D are the initial point and the middle point in snapback region, respectively. Subsequently, the curve will reach the critical point (E) called the secondary breakdown point of GGNMOS device. Furthermore, the corresponding current of secondary breakdown point is named the secondary breakdown current (It2). If the high-voltage DC supply further raises the charged voltage, the I-V curve will reach the point F into the secondary breakdown region, which causes the permanent damage on the GGNMOS device.
Here, the failure criterion of silicon devices is defined when the leakage current of DUT exceeds 1 μA after the 500-ns LP-TLP stress. From the measured results, the 500-ns LP-TLP system can efficiently measure the snapback characteristics of GGNMOS device under CDE-like stress. Fig. 3.6 shows that the 500-ns LP-TLP measured trigger voltage is 5.9 V, the snapback voltage is 4.3 V, and the It2 is 2.3 A.
The 1000-ns LP-TLP measured I-V characteristic of GGNMOS with a device dimension of W/L= 240 μm/0.3 μm is shown in Fig. 3.8. Besides, Figs. 3.9(a)-(f) show the time-domain I-V waveforms of GGNMOS device at the corresponding points marked in Fig. 3.8. Similarly, the 1000-ns LP-TLP system can measure and analyze the secondary breakdown characteristic of GGNMOS device. Fig. 3.8 shows that the 1000-ns LP-TLP measured trigger voltage is 5.9 V, the snapback voltage is 4.3 V, and the It2 is 1.7 A. From the aforementioned tests, the 500-ns (1000-ns) LP-TLP system can be used to effectively observe the CDE robustness of DUT.
3.3 SUMMARY
A new proposed LP-TLP system with two kinds of long pulse widths (500 ns/1000 ns) is utilized to investigate the phenomenon of CDE event on IC products.
The snapback I-V characteristics and the secondary breakdown current (It2) of devices in CMOS ICs can be measured through the proposed LP-TLP system.
Moreover, the proposed LP-TLP system can successfully observe the CDE robustness of DUT.
Fig. 3.1 The measurement setup for the traditional TLP test.
Fig. 3.2 The 100-ns TLP current waveforms on a 50-Ω resistor under different charged voltages.
Fig. 3.3 The measurement setup for the proposed LP-TLP test.
Fig. 3.4 The actual measurement setup for the proposed LP-TLP test.
(a)
(b)
Fig. 3.5 The (a) 500-ns and (b) 1000-ns LP-TLP current waveforms on a 50-Ω resistor under different charged voltages.
Fig. 3.6 The 500-ns LP-TLP measured I-V characteristic of GGNMOS device.
(a) (b)
(c) (d)
(e) (f)
Fig. 3.7 (a)-(f) The measured time-domain I-V waveforms of GGNMOS device at the corresponding points marked in Fig. 3.6.
Fig. 3.8 The 1000-ns LP-TLP measured I-V characteristic of GGNMOS device.
(a) (b)
(c) (d)
(e) (f)
ig. 3.9 (a)-(f) The measured time-domain I-V waveforms of GGNMOS device at the corresponding points marked in Fig. 3.8.
F
Chapter 4
Dependence of Layout Parameters on CDE Robustness of CMOS Devices
4.1 NMOS/PMOS IN A 0.25-μmSALICIDED CMOSPROCESS
In order to design area-efficient CDE protection circuits, the CDE robustness of protection devices is considered as strong as possible in per unit layout area. To optimize the layout area, the layout spacings are the major considerations for designing strong CDE robustness devices. The main layout factors to affect the CDE level of CDE-protection devices are the channel width (W), the channel length (L), the finger width (Wf) of each finger, th spacing from source contact to poly-gate ote: the SAB layer is the silicide-blocking layer to block the silicided diffusion on the drain regions). Moreover, the descriptions for different layout parameters are shown in Table 4.1. When the dependence of CDE current paths on the layout parameters are well comprehended, CDE protection devices can be optimized to perform higher CDE robustness.
In this section, the dependence of these five layout factors on the CDE level of the gate-grounded NMOS (GGNMOS d gate-VDD PMOS (GDPMOS) are
understand the difference between the CDE level and the HBM ESD level, the long-pulse
the transmission line pulsing (TLP) used to measure the second breakdown characteristics of devices.
e
edge (Z), and the SAB width (X), which are illustrated in Fig. 4.1 (n
) an
practically investigated through fabricated silicon chips. To clearly
transmission line pulsing (LP-TLP) and techniques will be
The proposed LP-TLP and the conventional TLP measured data are compared the dependence on layout parameters as follows.
4
to find
.1.1 Channel Width
T leakage
urrents, and the turn-on resistances of GGNMOS devices with different channel widt
on resistances of GGNOS devices with different widths of 240 μm, 300 μm,
edge (Z), the distance from drain he 500-ns LP-TLP measured I-V characteristics, the corresponding
c
hs, but with the same channel length and unit-finger width, are shown in Fig. 4.2.
From the measured results, all GGNMOS devices with different channel widths have distinct snapback characteristics. In addition, the It2 of the GGNMOS device is linearly increased with increasing the channel width. The It2 levels of GGNOS devices with different widths of 240 μm, 300 μm, 360 μm, and 600 μm under the proposed 500-ns LP-TLP test are 2.3 A, 2.9 A, 3.3 A, and 5.1 A, respectively. But, the turn-on resistance of GGNMOS device in snapback region is decreased with increasing the channel width. Here, the turn-on resistance is defined as the voltage variation over current variation before second breakdown in the 500-ns LP-TLP measured I-V curve. The turn-on resistance can be expressed as
Rdevice ≡ ∂VDS/∂ID (4.1) The
turn-360 μm, and 600 μm under the proposed 500-ns LP-TLP test are 2.05 Ω, 1.66 Ω, 1.36 Ω, and 0.87 Ω, respectively. The dependence of the It2 levels of GGNMOS and GDPMOS devices on the channel width under the traditional 100-ns TLP and the proposed 500-ns (1000-ns) LP-TLP tests is shown in Figs. 4.3(a) and 4.3(b), respectively. The unit-finger width (Wf) of GGNMOS and GDPMOS devices in the finger-type layout is kept at 30 μm. For both GGNMOS and GDPMOS devices, the channel length (L), SAB width (X), the clearance from SAB to poly-gate edge (Y), the spacing from source contact to poly-gate
diffusion to guard ring edge (G) are drawn as 0.3 μm, 3 μm, 0.3 μm, 0.75 μm, and Fig. 4.3(a), these It2 levels of GGNMOS devices are linearly incre
to the DUT device, which causes a w
2μm, respectively. In
ased while the channel width is increased. Besides, the It2 levels of GGNMOS devices under the traditional 100-ns TLP test are much higher than those under the proposed 500-ns (1000-ns) LP-TLP test. For instance, the It2 of GGNMOS device with a channel width of 360 μm under the traditional 100-ns stress is 5.3 A, but that with the same device dimension and layout style under the proposed 500-ns and 1000-ns LP-TLP tests are only 3.4 A and 2.4 A, respectively. Similarly, while the channel width is increased, the It2 levels of GDPMOS devices under the traditional 100-ns TLP and the proposed 500-ns (1000-ns) LP-TLP tests are all increased, as shown in Fig. 4.3(b). Furthermore, under the same device dimensions and layout style, the It2 levels of GDPMOS devices under 500-ns (1000-ns) LP-TLP stress are evidently lower than those under the traditional 100-ns TLP stress. Attributed to the longer LP-TLP pulse width, the stronger energy is injected in
eak robustness of the device under CDE stress.
4.1.2 Channel Length
The relations between the channel length and the It2 levels of GGNMOS and GDPMOS devices under the traditional 100-ns TLP and the proposed 500-ns (1000-ns) LP-TLP tests are illustrated in Figs. 4.4(a) and 4.4(b), respectively. The layout style and other parameters are all kept the same (W=360 μm, Wf=30 μm, X=3 μm, Y=0.3 μm, Z=0.75 μm, and G=2 μm), but only the channel length is different in this investigation. From the measured results in Fig. 4.4(a), when the GGNMOS device has a shorter enough channel length under the traditional 100-ns TLP test, the efficiency and performance of the parasitic lateral BJT in the GGNMOS device is significantly improved [16], [17]. Therefore, the GGNMOS device with a short
channel length (0.25 μm) can sustain much higher HBM ESD level than that with a medium channel length of ~0.35 μm. However, the GGNMOS device with a shorter channel length under the proposed 500-ns LP-TLP test has a lower It2, especially in a channel width of 0.25 μm. The It2 levels of GGNMOS devices under the proposed 1000-ns LP-TLP test are the lowest and not obviously varied with different channel lengths. Similarly, the It2 levels of GGNMOS devices under the traditional 100-ns TLP test are still higher than those under the 500-ns (1000-ns) LP-TLP test.
On the contrary, the GDPMOS device with a shorter channel length has a lower It2 under the traditional 100-ns TLP test and 500-ns (1000-ns) LP-TLP test, as shown in Fig. 4.4(b). Even if the GDPMOS device with a minimum channel length of 0.25 μm, their It2 levels under the traditional 100-ns TLP test and the 500-ns (1000-ns) LP-TLP tests are only 2.2 A, 1.18 A, and 0.95 A, because the turn-on efficiency of lateral p-n-p BJT in the GDPMOS device is not improved. From this experimental investigation, the selection of MOSFET for ESD and CDE protection is quite different
CMOS process.
in the 0.25μm salicided
4.1.3 Unit-Finger Width
In the I/O cell layout of CMOS ICs, a large-dimension device is traditionally drawn with multiple fingers in a parallel connection. If the finger width (Wf) of every finger is shorter, more fingers must be used to form the same large-dimension device.
The large-dimension device with different numbers of unit finger and unit-finger width can cause different ESD and CDE performances, even though the devices have the same channel width (W) and channel length (L) dimensions. The more multiple fingers of a large-dimension device are hard to be uniformly turned on during the ESD and CDE stresses, hence it may result in different ESD and CDE levels. To verify this issue, both the GGNMOS and GDPMOS devices with the fixed channel
width (W)/channel length (L) of 360 μm/0.3 μm but different unit-finger widths are investigated under the traditional 100-ns TLP and the 500-ns (1000-ns) LP-TLP tests.
The tested results are shown in Fig. 4.5(a) and Fig. 4.5(b).
From the measured results, the It2 of GGNMOS devices of W=360 μm under the traditional 100-ns TLP stress is decreased from 5.61 A to 4.46 A as the GGNMOS devic
tness of GGNMOS and GDPMOS devices is much worse than their HBM ESD robustness under the same layout factor of the
e is drawn with the finger number from 8 to 24. When the GGNMOS device is drawn with the finger number from 24 to 8, the It2 levels of the GGNMOS devices of W=360 μm under the proposed 500-ns (1000-ns) LP-TLP stress are increased from 2.94 A to 3.39 A (2.22 A to 2.56 A). Similarly, the more finger number in the GDPMOS device leads to slightly lower ESD and CDE robustness. From the above-mentioned analysis, it implies that the finger-type GGNMOS and GDPMOS devices with a shorter finger width cannot be uniformly turned on during ESD and CDE stresses. Moreover, the CDE robus
unit-finger width.
4.1.4 Spacing from Source Contact to Poly-Gate Edge
The relationships between the spacing from the source contact to the poly-gate edge (Z) and the It2 levels of GGNMOS and GDPMOS devices under the traditional 100-ns TLP and the proposed 500-ns (1000-ns) LP-TLP tests are investigated in Fig.
4.6(a) and Fig. 4.6(b), respectively. In this investigation, all the layout style and other spacings are kept the same (W=360 μm, L=0.3 μm, Wf=30 μm, X=3 μm, Y=0.3 μm, and G=2 μm), but only the spacing Z is varied from 0.25 μm to 2 μm in the test chips.
From the experimental results, the spacing Z varied from 0.25 μm to 2 μm only causes a slight variation on the It2 from 5.14 A to 5.25 A (2.12 A to 2.47 A) in the GGNMOS (GDPMOS) device under the traditional 100-ns TLP stress. Under the
proposed 500-ns LP-TLP stress, the It2 of GGNMOS (GDPMOS) is increased from 2.88
e of the It2 levels of GGNMOS and GDPMOS devices on SAB width (X) under the traditional 100-ns TLP and the proposed 500-ns (1000-ns)
ectively. The layout style and other
A to 3.34 A (1.13 A to 1.39 A) as the spacing Z is increased from 0.25 μm to 2 μm. However, the GGNMOS device with a shorter spacing Z under the proposed 500-ns LP-TLP stress has a lower It2 current, especially in the spacing of 0.25 μm. In addition, it also results in a little increase on the It2 from 2.3 A to 2.74 A (0.9 A to 1.16 A) of GGNMOS (GDPMOS) device under the proposed 1000-ns LP-TLP stress when the spacing Z varies from 0.25 μm to 2 μm. Only a little efficiency of the spacing Z can change the turn-on path of the parasitic lateral BJT owing to the source diffusions of MOSFET are connected with the bulk of MOSFET. Therefore, the spacing Z has no obvious impact on the ESD and CDE robustness of MOSFET.
4.1.5 SAB Width
The dependenc
LP-TLP tests is shown in Figs. 4.7(a) and 4.7(b), resp
clearances are all kept the same (W=360 μm, L=0.3 μm, Wf=30 μm, Y=0.3 μm, Z=0.75 μm, and G=2 μm, but only the SAB width is different in this investigation. In Fig. 4.7(a), the It2 of GGNMOS device under the traditional TLP stress is increased as the SAB width is increased from 1.5 μm to 2 μm. Because the silicide blocking on the drain region introduces ballast resistance, it could limit ESD currents to flow through the channel surface of MOSFET. On the contrary, while the SAB width is increased from 2 μm to 5 μm, the It2 of GGNMOS device under the traditional 100-ns TLP test is decreased from 5.6 A to 4.1 A. Due to large increase of the SAB width (i.e. add too much silicide blocking), the power consumption along the ESD current path increases, resulting in a higher thermal stress and consequently a significantly lower It2. From the 100-ns TLP measured results, the maximum It2 of
GGNMOS device is with the SAB width of 2 μm. Under the proposed 500-ns (1000-ns) stress, the It2 trend of GGNMOS device is similar to the case under the
GGNMOS device is with the SAB width of 2 μm. Under the proposed 500-ns (1000-ns) stress, the It2 trend of GGNMOS device is similar to the case under the