With the receiver ADC sampling clock phase and frequency offset, the received data is showed in Fig. 3-2. In Fig. 3-2(a) with the assumption of ADC sampling phase offsetε, the dash linexRrepresents the sampled data while theoptrepresents the optimal sampled data. The sampled data all space a fixed time interval to the optimal sampled data. In Fig. 3-2(b) with the assumption that DPR has been done and there is
only sampling frequency offsetζ , the sampled data is represented by the dash linesxR, while again the optimal sampled data is represented byopt. The sampled data space a increasingly time interval to the optimal sampled data. We see that as the symbol index increases, the timing error increases, and this will make the adjusted optimal sampling phase drift away. So we apply DFR to recover the optimal sampling frequency.
ε ε ε ε
x
Rx
Rx
Rx
RFig.3-2(a), Sampling phase offset
Ts
ζ 2ζTs 3
Ts
ζ
x
Rx
Rx
Rx
RFig.3-2(b), Sampling frequency offset
(WPAN) [1] and portable devices. In the interpolation approaches, however, received signals are sampled by Nyquist or even higher rate, resulting in large ADC circuit power and dominating the overall system power dissipation. It is shown in Fig. 3-3 that ADC power is about twice as the sampling rate is doubled.
Fig.3-3, The relation of ADC’s power consumption to its sampling speed.
The conventional interpolation method is shown in Fig. 3-4, where the input signal is assumed to be converted to baseband by a free running oscillator. The clock phase
Φestimation is done by using the up-sampled data, followed by the interpolation coefficientsCkis updated by the estimated clock phase. A data buffer is needed to store I and Q samples to wait for interpolation [3]-[4].
Data
Fig. 3-4, Block diagram with receiver with interpolations to solve symbol timing error.
Using the interpolation method, not only the sampling timing can be extracted but also the noise interference can be averaged by the interpolation filter. However the major drawback of that is to use 2 times up sampling rate, because it will brings almost 2 times of the ADC power which is not suitable in low power applications.
To meet the system power limitation and reduce the power consumed in an ADC circuit, a dynamic phase recovery (DPR) is proposed to drive the ADC circuits sampling in the symbol rate with the aid of a phase-tunable clock generator (PTCG), which search the best sampling phase in the received signals. To maintain the searched clocking phase without drifting due to clock frequency offset, a dynamic
The overall system power reduction is made from preventing using over-sampling ADC by adopting a phase and frequency tunable clock generator. The power consumption of these two features is compared in Fig. 3-5. From reference [14] under 90nm process, an ADC with sampling rate 5MHz is about 1.1mW. Doubling the sampling rate will increase its power consumption to around double. However, according to the implementation under 90nm process, the power consumption of a phase-frequency tunable clock generator (PFTCG) is about only 77uW. We can see that they differ by an order amount. So the power reduction is guaranteed.
0 500 1000 1500 2000 2500 3000 3500
1 2 3
po w er(uW )
10MHz sampling rate ADC
5MHz sampling
rate ADC PFTCG
Fig. 3-5, Power consumption of ADC and PFTCG under 90nm CMOS technology.
3.3 Dynamic phase recovery
ADC clock sampling phase offset will result in worse system performance, thus the dynamic phase recovery (DPR) is applied to recover clock sampling phase. Since we want to keep the ADC sampling rate as the same as symbol rate and also reconstruct the received data with optimal sampling phase, a phase tunable clock generator is required to dynamically adjust the ADC sampling clock phase. The repeated preamble can be used to search the optimal sampling phase. Suppose the transmitter pulse response and receiver analog prefilter are considered as an equivalent response
( ) T( ) R( )
f t = f t ∗ f t ………(3-1)
and let f nε[ ]= f n[( −ε) ], 0Ts ≤ ≤ε 0.5,
ε
represent the ADC clock sampling phase offset. The optimum sampling phaseεopt is defined that makes a maximum ratio of signal to inter-symbol interference power ratio (SIR), as written in equation (3-2).2
2 2
=
∑
. Equation shows that with the optimum sampling phaseε , a opt maximumE x{| R,ε | }2 is obtained. So we may rewrite equation (3-4) as2
arg max( {| , | })
opt E xRε
ε = ε ……….(3-5)
Since the expect valueE{.}is impossible to get realistically, the power calculation can be done by averaging of finite samples. We use the maximum-absolute-squared-sum (MASS) search of the initial preamble, which is to search for the maximum of the sum of the absolute squared value of the data. Each OFDM symbol of the preamble is sampled using different sampling phases
ε
, provided by the phase-tunable clock generator (PTCG), then choose the phase that results in the maximum-absolute-squared-sum to be the sampling phaseε
ˆ. Moreover, the carrier frequency offset caused by the carrier frequency mismatch between transmitter and receiver will not affect the absolute value, because it only makes the received signal phase rotation in time domain, as shown in equation (3-6)[ ] [ ] (
2)
R R S
ˆx n =x n exp j⋅
π
⋅ ⋅ ⋅f n T ………...(3-6) where f is the carrier frequency offset andT
S is the symbol period. Therefore the MASS search can be started as soon as the packet detection is done. In order to increase the estimation accuracy, the comparison can be done more than once. For example, we can first choose half of the applying phase with maximal absolute valuesearch, and then perform it again on the searched phases in last step and so on.
3.4 Dynamic frequency recovery
Although dynamic phase recovery adjusts the sampling clock phase, the drift amount due to sampling clock frequency offset still increases. The most significant effect of sampling clock frequency offset is the phase rotation to received subcarriers as written in equation (3-7).
2 S
u
j ( kl )T T
l ,k l ,k l ,k ;l .k l ,k
Y =e π ζ ε+ X sinc( k )H
π ζ
+Nζ +W ………...(3-7)whereH is channel frequency response at k-th subcarrier,l ,k T is the useful data u portion,W is the additive white Gaussian noise and thel ,k Nζ;l ,kis additional noise due to clock sampling frequency error at l-th symbol and k-th subcarrier. Clearly, the phase error is proportional to the symbol index, subcarrier index and sampling clock frequency offset. However, the decision-directed phase recovery method is incapable of recovering the increasing phase error when the drift amount becomes large.
Dynamic frequency recovery not only directly compensates the phase error of data
zero.
Based on measuring the phase difference between the pilots, the phase error is
u wherePl,Im is the received data on pilot position at l-th symbol and Im-th subcarrier which is also the pilot index. In order to estimate clock frequency offset, we use the least squares algorithm [7] which can track the residual carrier frequency offset and clock sampling frequency offset. The clock sampling frequency offset can accurately estimated as equation (3-10)
,1 ,2 ,
: phase error on l OFDM symbol, M pilot subcarrier
( ) where [ ] is the least square solution.
ated residual CFO, C1,l is the estimated clock frequency offset.
…..………(3-10)
C is the estimated sampling clock frequency offset in equation (3-9). 1,l
1,l 2 s
u
C l T
π ζ
T= ………...(3-11)
Then, the estimated sampling clock frequency offset at l-th symbol can be easily calculated by equation (3-12).
ˆ 1,
2
u
l l
S
T C
T l
ζ = π × × ………(3-12)
Because the additional noise Nζ;l,k due to clock sampling frequency offset and the inter-channel interference (ICI), the result of clock sampling frequency offset estimation is not very stable. And from equation (3-11), we can see that the calculation resultC is proportional to the sampling clock frequency offset1,l ζ , and is increasing with the OFDM symbol indexl as shown in Fig. 3-6. Thus in order to increase the estimation accuracy and prevent burst errors, we solve the least square equation again to extract the sampling clock frequency offsetζ .
1,l
C
The overall system receiver block diagram with dynamic phase-frequency recovery is shown in Fig. 3-7. After packet detection, the dynamic sampling phase is turned on to adjust the ADC sampling clock to the optimal phase, and the dynamic sampling frequency estimation is also turned on after data processed through the FFT. The Timing error detector performs MASS search while the Frequency error detector performs least squares algorithm. The ADC sampling clock is controlled by PTCG and FTCG, showed in Fig. 3-8.
& compensation PN code de-spreading
FFTFFT EqualizationEqualization QPSK de-mapping
Fig. 3-7, Receiver block diagram with dynamic phase and frequency recovery.
TS
TS
Fig. 3-8, The function of PTCG and FTCG.
3.5 The structure of phase-frequency tunable clock generator
The PFTCG architecture is shown in Fig. 3-9. The reference clock is generated by the crystal oscillator circuit. The PFD detects the difference of frequency and phase between the reference clock (REF_CLK) generated by crystal oscillator circuit and the DCO (digital clock oscillator) output (FB_CLK). DCO is composed of several delay cells, and they constitute several delay paths, as shown in Fig.3-10. The UP and DOWN signals indicate that the controller adjusts the DCO control code to select the delay path, thus, a frequency-tunable ability is reached. For generating the multiphase clock signal, different phase is extracted in the delay path, too. (By selecting the output position) [6].
PFD Controller
DCO
REF_CLK
UP LOCK DOWN
FB_CLK
DCO_CODE
PHASE 7 ...
Frequency Offset Estimated
MUX OUT_CLK Phase _ Select
Fig.3-10, Digital control oscillator.
The PFTCG control flow is illustrated in Fig. 3-11. After the system reset, the DCO is tuned by the PFD to catch up the speed of the reference clock. The tuning time will last for a fixed period, then the LOCK signal gets high. Afterwards, the DCO is continuously tuned by the estimation of sampling frequency offset which was done by pilot-aided phase recovery.
Buffer Buffer Buffer Buffer
MUX
0
MUX
MUX
MUX
IN
ON[0]
ON[1]
ON[M-1]
ON[M]
……
……
OUT
Fig. 3-11, The control mechanism of the PFTCG.
Update DCO Code System Reset
Reset DCO Reset PFD
PFD
Calculate DCO Code
UP DOWN LOCK
Calculate &
Update DCO Code Tune DCO
by Phase Recovery
CHPTER 4 Simulation Result
4.1 Simulation on AD/DA resolution
The simulation environment that contains MT-CDMA baseband transceiver and channel model is established by high-level language. Simulation of optimal AD/DA resolution will find a optimal AD/DA word length with the trade-off between error rate performance and hardware complexity. As the word length increases, the computation resolution will also increase and the transmission performance will be better while in the same time more hardware or power consumption is needed.
Transmission without any quantization error provides an ideal referenced performance for simulation of the fixed-point transceiver. Fig. 4-1 shows the PER curves of different transmitter DAC resolution. Here we choose DAC word length to be 5 because the performance loss is only 0.5dB at PER=1% which is in the acceptable region. In another way, the simulation of different receiver ADC word length to the overall PER performance is shown in Fig. 4-2. We choose the word
length to be 6 for the SNR loss is only 0.2 dB at PER= 1% compared to the floating point case.
choice
Fig.4-1, PER comparison of different DAC word length
choice
4.2 Simulation on PER performance with carrier frequency offset and sampling clock offset
Carrier frequency mismatch between transmitter and receiver leads the received data be distorted, so a compensation scheme is needed to recover the original signal.
In our developed system, the CFO estimation is divided into two steps to increase the estimation accuracy: one is coarse CFO estimation and the other is fine CFO estimation. Then use the estimation result to compensate the received data and in Fig.4-3, the simulation of PER with 112 kHz carrier frequency offset is shown. The performance loss is about 0.7dB compared to 0 kHz carrier frequency offset when PER reaches 1%.
Fig. 4-3, PER with 112 kHz carrier frequency offset.
Sampling clock offset influences the received sampled data, and the offset timing interval will even increase and it may make some data lost. Especially in our developed system, 31-point PN code spreading is performed, so every data symbol is spread to 31 symbols. The timing offset is increasing among the 31 symbols making the de-spread data be largely distorted. Existing frequency offset method is pilot-aided data calibration [7]. It is to estimated data phase rotation caused by sampling frequency offset, and to compensate the data by subtract the estimated phase error.
Fig. 4-4 shows the simulated PER with different sampling clock offset with the reference recovery method [7]. In the simulation result, we can see that the performance loss of 50ppm sampling clock offset compared to no frequency offset case is still 1dB at PER=1%, so the reference method is not very robust.
1dB
4.3 Simulation on dynamic phase recovery
In chapter 3, we have discussed the sampling clock phase offset. Worse sampling phase will lead to large performance degradation. We want to examine on how the sampling phase offset influences the system performance, so by dividing the sampling timing to 8 different phases with equivalent interval noted by
{ 0.5, 0.325, 0.25, 0.125,0,0.125,0.25,0.325}
ε = ± − − − ………...(4-1)
The simulation was done with the assumption of these phases, and is shown in Fig.
4-5. Because of the symmetry of these sampling phase offsets, we only show 5 phases in Fig. 4-5. It can be inferred that positive offset and negative offset with the same amount will result in the same performance. The simulation result tells that as the phase offset increases, the PER gets worse. The worst case isε =0.5, and the performance loss is about 2dB at PER=1% compared to no phase offset.
Fig. 4-5, PER with different sampling clock phase offset.
The proposed dynamic phase recovery is to do maximum absolute value search of the initial preamble with different sampling phases provided by a phase-frequency tunable clock generator. According to the proposed method, optimal sampling phase will provide maximal signal power, so we calculate the maximum absolute value of the sampled data while changing the sampling phase, and choose the phase that result
different amount of sampling phase offset is simulated. Here we choose the acceptable sampling phase offset to be 1/16 which means we need an 8-phase tunable clock generator to do the optimal phase searching.
choice
Fig.4-6, SNR loss with different sampling phase offset.
The simulation result on probability distribution of phase searching is shown in Fig. 4-7 with a 8-phase tunable clock generator and at SNR=5dB. Here we calculate 128-point absolute square sum and the comparisons are performed three times. First we pick up the top four with maximal absolute square sum, then two of the four, then one of the two. Finally the optimal sampled phase can be decided.
Noted that the estimation accuracy will be affected by noise as shown in Fig. 4-8, the probability of adjusted phase result under SNR=3dB and 10dB is simulated. We can see that in the SNR=10dB condition, there is about 13.4% more probability lies in the
region that phase offset is zero, while comparing with SNR=3dB condition.
ε
Fig. 4-7, Probability distribution of adjusted phase using maximal absolute square sum search at SNR=5dB.
ε
Fig. 4-8, Probability distribution of adjusted phase under SNR=3dB and 10dB.
From the simulation results showed above, we can see that most of the probability distribution of phase adjustment lies in the region that makes the better packet error rate. And the overall system performance applying the proposed dynamic phase recovery method is also simulated. It is shown in Fig. 4-9. PER of perfect case (sampling phase offsetε =0) is also drawn in the same plot as a comparison.
Originally with the best and worst sampling phase offset, there is about 2.05dB SNR loss. After applying the dynamic phase recovery, through a phase searching and tuning scheme, the resulting SNR when PER equals to 1% can be reduced for 1.9dB.
Fig. 4-9, PER with the proposed dynamic phase recovery.
4.3 Simulation on dynamic frequency recovery
In the dynamic frequency recovery method, the sampling frequency offset is estimated by pilot symbol phase rotation in each OFDM symbol. According to
least square equation is solved two times, one is aiming at a single OFDM symbol, and another is at several OFDM symbols with the estimated result of last step. Fig.
4-10 shows the simulation result of sampling frequency adjustment while using the proposed dynamic frequency recovery. We assume the initial sampling frequency offset be 50ppm. Here the frequency tuning is done once 8 OFDM symbols. In the realistic application, the training packet might have to be sent in advance to get the better sampling frequency. And the overall system performance is also simulated with the proposed dynamic frequency recovery, and is shown in Fig. 4-11. With the proposed dynamic frequency recovery, packet error rate of 50ppm sampling frequency offset case can be kept close to the case of no frequency offset, and there is about 0.2dB SNR loss when PER equals 1%.
convergence
Fig. 4-10, Sampling frequency tuning with the dynamic frequency recovery.
0.8dB
Fig. 4-11, PER with the proposed dynamic frequency recovery.
In the end, the simulation of both dynamic phase and frequency recovery with 50ppm frequency offset and random phase offset is shown in Fig.4-12. Comparing with the no sampling offset case, there is about only 0.25dB SNR loss when PER=1%.
And the overall power comparison designed by 90nm CMOS process is shown in Fig.
4-13. The overhead of the proposed design includes the extra hardware of dynamic phase and frequency recovery and a phase-frequency-tunable clock generator. By replacing the 2 times over-sampling rate receiver ADC circuit with the proposed design, about 46% ADC power can be reduced.
Fig. 4-12, PER with the proposed dynamic phase and frequency recovery.
0 1000 2000 3000 4000 5000 6000
power(uW)
1 2
PFTCG(77uW,1.28%) DPR+DFR(140uW,2.33%) ADC[14]
46%
proposed conventional
90nm CMOS technology Supply voltage: 1V
2X
ADC 1X
ADC
Fig. 4-13, Power comparison of the proposed method to the conventional design.
CHPTER 5 Conclusion and Future Work
5.1 Conclusion
A multi-tone CDMA system is established for wireless body area network application. By using the advantage of orthogonal frequency division multiplexing (OFDM) and code division multiple access (CDMA), the proposed system is very robust to the frequency selective multipath fading and noise interference. Packet error rate can be kept under 1% when SNR>=3dB. The carrier frequency offset up to 112
SNR, so we proposed a dynamic phase recovery method to estimate the phase offset and directly adjust the ADC sampling phase. With the proposed method, the performance loss when there’s phase offset to the perfect case can be kept smaller than 0.15dB SNR.
Sampling clock frequency offset also influences the system performance. The performance loss with 50ppm frequency offset is about 1dB SNR. So a dynamic frequency recovery is also proposed to resist sampling clock frequency offset. It uses pilot sub-carriers of each OFDM symbol to estimate sampling frequency offset and directly adjust the ADC sampling frequency. With the proposed method, there is about 0.8dB SNR improvement under 50ppm frequency offset case.
Considering both the sampling phase and frequency offset, with the proposed dynamic phase and frequency recovery method under 50ppm frequency offset and random phase offset case, there’s only 0.25dB SNR loss to the perfect case. Using dynamic phase recovery can prevent using over-sampling rate ADC in the receiver side. This will induce about 46.38% of ADC power reduction. Using dynamic frequency recovery improves system performance because it deals with the ADC
Considering both the sampling phase and frequency offset, with the proposed dynamic phase and frequency recovery method under 50ppm frequency offset and random phase offset case, there’s only 0.25dB SNR loss to the perfect case. Using dynamic phase recovery can prevent using over-sampling rate ADC in the receiver side. This will induce about 46.38% of ADC power reduction. Using dynamic frequency recovery improves system performance because it deals with the ADC