Settling Errors of Integration Phase

4.2 Settling Errors of Integration Phase

As was mentioned above chapter, there are three settling conditions depending on the absolute value of V_S. The full slewing case is not considered here because it is not significant. Note that VS at end of each integration interval can be written as

 

expression, and we draw it in Fig. 4.2:



Fig. 4.2 nonlinear transfer function of (4.3)

To approximate (4.3), we apply least square method and neglect the even terms by

reasons of symmetry of Fig. 4.2. Then (4.3) can be approximated by maximum value of VS, so that the sum of the squares of the distances of those points from the p_i(V_S) is minimum. The sum of the squares is solution of follow equations.

[ ]

distribution with standard deviation _V V_ref ^B

S ≈1 ⋅.4 /2

σ σσ

σ (second-order). There, the

probability density function (PDF) of V_S is

2 )

Nevertheless, since the integral interval is 0~VH, the PDF of VS should be modified as

2 )

Then (4.8) is normalized and weighting function can be expressed as

2 )

Taking into account the PDF of VS in any specific interval, then (4.6) is revised as:

[ ]

[ ]

Then the values of the coefficients computed to be:

×

In order to validate (4.11), we apply least square to the VS in three cases. In case one, behavior simulation was carried. In case two, equation (4.11) is used. In case three, the weighting function W(VS) is not considered. The parameters used in case one are B = 3-bits, OSR = 120, SR = 40V /µs, and GBW = 100MHz. Fig 4.3 and Table 4.1.

show the V_S and coefficients obtained in three cases. The case applying Gaussian distribution shows a good fit when compared to the one by simulation. In Fig 4.4, the fitting results in three cases are illustrated, and the case with Gaussian distribution is closer to the simulated one than another case. Note that the VL in this case is 0.1681 and the probability of nonlinear operation is respectively 0.35, 0.34, and 0.9 in three cases. This result shows that applying Gaussian distribution to VS plays a crucial role in calculating settling noise.

-0.80 -0.6 -0.4 -0.2 0 0.2 0.4 0.6

1000 2000 3000 4000 5000 6000 7000 8000 9000

-0.80 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8

2000 4000 6000 8000 10000 12000

-2 -1.5 -1 -0.5 0 0.5 1 1.5 2

0 200 400 600 800 1000 1200 1400

(a) Behavioral model (b) With Gaussian distribution (c) No Gaussian distribution Fig. 4.3. Distribution of V_S obtained in three different cases

TABLE 4.1

Coefficients obtained in three different cases

Behavioral model

With Gaussian distribution

No Gaussian distribution

α1 0.958 0.94 835.67

α 1.239 3 1.609 -1532.7

α 19.677 5 16.357 567.25

-2 -1.5 -1 -0.5 0 0.5 1 1.5 2 -8000

-6000 -4000 -2000 0 2000 4000 6000 8000

Vs

settling error

Behavioral model

with Gaussian distribution no Gaussian distribution

Fig. 4.4. Settling error versus V_S in three different cases

-3 -2 -1 0 1 2 3

0 500 1000 1500 2000 2500

angle of Vs (radians)

Numbers

Fig. 4.5. The distribution of angle of V_S

With coefficients

α α α α

₁,

α α α α

₃ and

α α α α

₅ in (4.4), the next step for calculating settling noise power is to determinate the PSD of V_S ³ by using the PSD of V_S. From (3.16), the height of the power spectral density of VS can be expressed as

) ( 2

) sin(

12 2 )

(

^{i f}

s s LSB

e

e

f f f

f V

h ππππ _×

^θθθθ

 

 



= 

_(4.12)

where θθθθ represents the angle of h_e at a particular frequency f. In previous chapter, the angle of PSD of VS is not considered. However, the angle of PSD of VS should be included in the computation of the PSD of V_S ³ and V_S ⁵ so that correct results can be obtained. In Fig. 4.5, simulation result shows that the angle of VS is close to a uniform distribution. Therefore, θθθθ is considerably assumed to be an arbitrary value in 0~2π. To find out the PSD of VS 3

, we firstly try to generate the PSD of square of VS as shown in Fig. 4.6. The discussion is divided into when f = 0 and when f ≠ 0. When f

= 0, h_e2(0) means sum of square of VS in time domain. From Parseval’s theorem, we get

f df f f

V f

n V h

s

s

f f

s s LSB s

S e

∫

∑

−



 





 



 

 



= 

=

2 2

2 2 2

2

) sin(

12 2 1

] [ )

0 (

ππππ (4.13)

(a) Included f = 0

(b) Not included f = 0 Fig. 4.6 Height of PSD of square of V_S

When f ≠ 0, by applying circular convolution, we can express the height of PSD of square of V_S as

1

Then it become clear that we cannot correctly compute the magnitude of h without _e2

taking into account the angle of h_e^. To demonstrate this idea, the integration of the convolution can be emulated as summing together arbitrarily large number of complex numbers A1, A2, A3… as is illustrated in Fig. 4.7.

(a) A result of convolution

(b) Sum of overlap part of (a) Fig. 4.7 Integration of the convolution

Since all of these complex numbers have different angles, we cannot simply add together their magnitudes, which would be the case if the angle of h is not included _e

in the convolution. Fortunately, because θ is arbitrary, the angles of A1, A2, A3… are zero and then the expected value of (4.15) results as

2

...

defined as

{ }

Then we can follow the above technique to obtain expected value of VS 3

Fig. 4.9 and Fig. 4.10 respectively compare the expected values of VS 3

and VS 5

with corresponding simulation results. Then the expected value of the height of spectral density of settling noise of integration phase can be defined as

{ h ( f ) }

₁

E { h

₁

( f ) }

₃

E { h

₃

( f ) }

₅

E { h

₅

( f ) }

Fig. 4.9 Comparison of the expected value of V_S ³ with the behavior simulation result

10³ 10⁴ 10⁵ 10⁶ 10⁷ 1

2 3 4 5 6 7 8 9 10x 10^-4

frequency (Hz)

Amplitude

Fig. 4.10 Comparison of the expected value of VS 5

with the behavior simulation result

So the settling noise in base band fB

± of integration phase can be obtained by integrating (4.19) as

{ h f } E { h f } E { h f } df E

P

^B

B

f

f e e e

∫

− + +

= _{1 1 3 3 5 5} ²

2 (

α α α α

( )

α α α α

( )

α α α α

( ) )

εεεε (4.20)

Then the total settling noise power can be computed as

2

1 ε

ε

ε

P P

P = +

_(4.21)

In order to demonstrate our analytical models, we use our model to predict the system behaviors shown in Fig. 4.1, and the results are provided in Fig. 4.11. These result show our models are very accurate. Notice that

α3

α α

α ^and αααα₅ ^are 8.9725×10⁻⁸ and 10 7

1274 .

5 × ⁻ in Fig. 4.11 (a), and are 0.04887 and 0.06023 in Fig. 4.11 (b).

These values mean that too serious nonlinearity may result in larger α3

αα

α ^and αααα₅^{, and}

we can find out from (4.19) that larger α3

αα

α ^and αααα₅ would arise affection of V_S ³ and

VS 5

, and more high frequency noise will be reflected into base band.

10⁴ 10⁵ 10⁶ 10⁷ -180

-160 -140 -120 -100 -80 -60 -40 -20

Frequency (Hz)

Power Spectrum Density (dB)

(a) SR=100 V/us, GBW=100 MHz

10⁴ 10⁵ 10⁶ 10⁷

-100 -90 -80 -70 -60 -50 -40 -30 -20 -10

Frequency (Hz)

Power Spectrum Density (dB)

(b) SR=30 V/us, GBW=55 MHz

Fig. 4.11 Settling noise of integration phase under different SR and GBW values

Note the low frequency regions of VS 3

and VS 5

in Fig. 4.9 and Fig. 4.10 are absolutely flat, and this means that the in band noise power will increase if the αααα₃ and αααα₅ in (4.11) increase. Therefore, the nonlinearity of settling will make an amount increase on noise power. It is worth noting that settling noise is highly dependent on the high frequency noise. Due to the noise shaping nature, the high

frequency amplitude of V_S is great and will lead to large settling noise. In order to provide insight on how settling noise is related to αααα₃ and αααα₅, we show behavior simulation with OSR = 100 , f_in = 100kHz, GBW = 80MHz, and for several different SR. The result is listed in Table 4.2. It is clear from Table 4.2 that when SR decreases, nonlinear effect would increase, resulting in much larger αααα₃ and αααα₅. Accordingly, settling noise increases significantly.

TABLE 4.2

The effect of SR on settling noise

SR (V/µs)

α3

α

αα αααα₅ Settling noise (dB)

40 2.4523×10⁻³ 2.8582×10^{−3 -69.967}

60 4.5034×10⁻⁵ 8.0204×10^{−5 -83.272}

80 2.0764×10⁻⁶ 1.1864×10^{−5 -92.784}

100 8.5082×10⁻⁷ 3.466×10^{−6 -100.851}

As we indicated in the above definitions of second order, we could extend such methodology easily for first, high order module. It must further be noted that we pointed out in the previous chapter, the quantizer nonlinearity will result in the presence of idle tones and pattern noise in the modulator output spectrum, these effects will lead to imperfect curve fitting in comparison to modulator output spectrum, especially in first order module. Therefore, a possible solution to this problem is to include, usually at the quantizer input, a non-periodic signal as pseudo-random noise. With this technique, called dithering [11], it is possible to partially decorrelate the quantization error and the input, and yield the good fitting result. Since the fitting procedures are certain similarities between second order and

high order modulator output spectrum in Fig. 4.12, Fig. 4.13. Furthermore, we derive the expected value of the height of spectral density of VS 2

, VS 3

{ }

Power Spectrum Density (dB)

(a) SR=200 V/us, GBW=200 MHz

10⁴ 10⁵ 10⁶ 10⁷ -120

-110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10

Frequency (Hz)

Power Spectrum Density (dB)

(b) SR=60 V/us, GBW=70 MHz

Fig. 4.12 Settling noise of integration phase under different SR and GBW values (first-order)

10⁴ 10⁵ 10⁶ 10⁷

-220 -200 -180 -160 -140 -120 -100 -80 -60 -40 -20

Frequency (Hz)

Power Spectrum Density (dB)

(a) SR=200 V/us, GBW=200 MHz

10⁴ 10⁵ 10⁶ 10⁷ -100

-90 -80 -70 -60 -50 -40 -30 -20 -10

Frequency (Hz)

Power Spectrum Density (dB)

(b) SR=60 V/us, GBW=70 MHz

Fig. 4.13 Settling noise of integration phase under different SR and GBW values (third-order)

In general, the higher-order Σ∆ modulator are found to offer improved performance, but when SR and GBW of OTA are not large enough, the performance of the higher-order Σ∆ modulator may be worse than the lower-order Σ∆ modulator.

Our model is used to show this phenomenon in Fig. 4.14. Typical ideal output PSD for three modulators are shown in Fig. 4.14 (a), we can find out that second, third-order PSD higher at high frequency and lower at low frequency than first-order PSD. However, when SR and GBW of OTA decrease, nonlinear effect becomes significant. Since second, third-order Σ∆ modulator have much larger noise power at high frequency, a large quantity of high frequency noise would be reflected into base-band, resulting in approximate settling noise power in the base-band for second-order Σ∆ modulator , and even excess settling noise power for third-order one. Fig. 4.14 (b) illustrating a typical such situation.

10³ 10⁴ 10⁵ 10⁶ 10⁷ -250

-200 -150 -100 -50 0

Frequency (Hz)

Power Spectrum Density (dB)

First Order Second Order Third Order

(a) SR=200 V/us, GBW=200 MHz

10³ 10⁴ 10⁵ 10⁶ 10⁷

-150 -100 -50 0

Frequency (Hz)

Power Spectrum Density (dB)

First Order Second Order Third Order

(b) SR=60 V/us, GBW=70 MHz

Fig. 4.14 Comparison of settling noise of first, second and third order Σ∆ modulators

It is worth noting that the previous literatures have been discussed as OSR increases, the settling noise power will rise dramatically and degrade the performance of Σ∆ modulator. Therefore, first order module might be a more efficient architecture than second and high order module. Our model can be applied to compute the minimum SR and GBW required so that the second or high order settling noise

power would not exceed the first order quantization noise power P_Q. That is, only when SR and GBW are larger than the required minimum values, then it is justified to employ second or high order modulator in stead of first order one. The results are summarized in Table 4.3. Table 4.3 indicates that as OSR increases, the bigger SR and GBW of second or high order modulator are needed to cope with the settling noise power.

TABLE 4.3

MINIMUM SR AND GBW REQUIRED W. R. T.OSR

OSR

P_Q of Fist Order Σ∆modulator

(dB)

Second Order

SR ) / (V µs

Second Order GBW (MHz)

Third Order SR

) / (V µs

Third Order GBW (MHz)

16 −41.744 ≥6 ≥5 ≥12 ≥10

32 −50.775 ≥12 ≥12 ≥24 ≥30

64 −59.805 ≥25 ≥33 ≥52 ≥55

80 −62.713 ≥35 ≥45 ≥64 ≥74

100 −65.620 ≥46 ≥53 ≥85 ≥100

120 −67.995 ≥51 ≥65 ≥98 ≥119

160 −71.744 ≥71 ≥90 ≥135 ≥150

5.

Derivation of Sigma-Delta Modulators Settling Distortion

Settling problem will produce not only the in-band noises but also the distortions in the Σ∆ modulator output spectrum, called settling distortions. These distortions introduced by an SC integrator are mainly due to voltage-dependent behavior of capacitors and switches, and nonlinearities associated to the gain of the amplifier as well as its settling behavior that we have been discussed in chapter 3. In this chapter, we analyze incomplete charge transfer in an SC integrator to obtain analytical models to represent harmonic distortion as function of SR, GBW of OTA. On the other hand, the nonlinearities in the front-end integrator are considered only due to it directly affecting the overall modulator linearity. When referred to the modulator input, nonlinear effects in the remaining integrators will be attenuated by the gain of the integrators.

The effect of the SR and GBW are related to each other, and may be interpreted as a nonlinear gain. Consider the SC integrator operates in the integration phase. As mentioned around (3.6), (3.7) in chapter 3, the evolutions of the output node during the n-th integration period are given by

1. Linear settling: ₂

1

1 ⋅ ⋅ττττ

< SR

V_S a :

nT T t

nT e

V a T nT V t V

nT T t

S O

O = − + ⋅ ⋅ − − < <

+

−

−

), 2 1

( )

( )

( ²

2) (

1

ττττ (5.1) 2. Partial slewing: SR V_S

a ⋅ ⋅ ₂ <

1

1 ττττ :

+

⋅ +

−

⋅ +

−

= ) sgn( )

( 2 ) ( )

( _{O O S}

O T V

nT t SR T nT V t V

O slope of output becomes less than SR, which result

= ¹ −τ₂ SR

V

t_O a ^S (5.3) Note that (5.1) and (5.2) at end of each integration interval can be rewritten as

)

Which is the integrator gain, and we show a plot of the expression (5.6) in Fig. 5.1. It is worth noting that distortions are produced at the modulator output when OPAs operate in the partial slewing region, because we can find in that region, the integrator gain is a function of integrator input VS.

Fig. 5.1 nonlinear transfer function of (5.6)

The curve fitting technique applied in chapter 4 will be used again to acquire analytical model of settling distortion. From (5.4), (5.5) and (5.6), we rewrite the equation of front-end integrator output as

S And (5.7) can be described with the following form

... indicates the coefficients of nonlinear DC transfer characteristic of Σ∆ modulator contain enough information to calculate the harmonic distortions when a realistic input signal is applied. Therefore our immediate work is to obtain the nonlinear DC transfer characteristic from the input X to output Y . In order to determine the nonlinear DC transfer characteristic, we use a DC input signal X is applied to the modulator input, and consider 1-bit quantizer case, we can find out the signal Y will be either one or minus one. Let us denote the probability that Y equals one with the symbol “P ”, then the probability that Y equals minus one is “1−P”, and since for a stable modulator [33] , the output of the first integrator cannot grow without limit, the average increment of V has to equal zero, this means that _O

From (5.10), the expected value of Y is given by characteristic. Therefore, we use these coefficients and let modulator input

)

And the K-th harmonic distortion is obtained as

1 characteristic of Fig. 5.1. Then (5.6) can be approximated by

The p_i(V_S) should be fitted through all the points in 0~V_H, where V_H is defined as A_VS, and have been discussed in (3.19), so that the sum of the squares of the distances of those points from the p_i(V_S) is minimum. Since the input signal is sinusoid and is uniformly distributed in - AVS ~ AVS, the weighting function is not needed here.

Therefore, the sum of the squares is

[ ]

_S solution of follow equations.

[ ]

[ ]

Then the coefficients were expressed as



Applying (5.11), (5.12), (5.13) and (5.17), the third and fifth settling distortions at the modulator output are

2 behavior will operates linearly and has no distortion at output node.

In order to verify the result in (5.18), (5.19), we use MATLAB-SIMULINK to construct a second-order Σ∆ modulator with a multi-bit quantizer. The behavioral settling model in [15] is employed. We assume that SR = 50V/µs, GBW = 70MHz, R

= 300Ω , OSR = 100, f = 100KHz and _B C = 2pF, and a 100KHz sinusoidal input _S signal is used. After performing FFT to the output data of the Σ∆ modulator, we obtain the simulated PSD which is shown in Fig. 5.2. It shows that HD3 is -79.69dB and HD5 is -82.51dB. The theoretical harmonic powers calculated from (5.18), (5.19) are HD3 = -80.64dB and HD5 = -83.7dB. These simulated and theoretical results are very close, and these values confirm that our settling distortion model is reasonably accurate.

10³ 10⁴ 10⁵ 10⁶ 10⁷ -120

-100 -80 -60 -40 -20 0

X: 5e+005 Y: -82.51

Frequency (Hz)

Power Spectrum Density (dB)

X: 3e+005 Y: -79.69

Fig. 5.2 Output spectrum of a second-order Σ∆ modulator with settling harmonic distortion

In order to provide insight on how settling distortions are related to circuit and system parameters, we further analyze the 3^rd and 5^th harmonic powers as follows:

Settling

HD3 (dB) = 20 log )

2 4

( 1 ²

1 3

Ain

α αα α αα αα

Settling

HD5 (dB) = 20 log )

216

( 1 ⁴

1 5

Ain

α αα α αα αα

(5.20)

The（5.20）appears that αααα₁, αααα₃ and αααα₅ are functions of T, GBW, R,_CS and SR.

Furthermore, due to these non-idealities of OTA such as GBW, and SR limitations will be dramatically affect the harmonic distortions, we put more emphasis on relationships between SR, GBW and the settling distortion. Fig 5.3 shows SR versus HD3 with GBW=65MHz, R = 300Ω , OSR = 100, fB= 100 KHz and Cs = 2pF, and a 100 KHz sinusoidal input signal. Similarly, Fig. 5.4 shows GBW versus HD3 with

confirm that our settling distortion model is reasonably accurate.

30 35 40 45 50 55 60 65 70 75 80

-160 -140 -120 -100 -80 -60 -40 -20 0

SR (V/us)

HD3 (dB)

Fig. 5.3 SR versus HD3

50 100 150 200 250

-200 -180 -160 -140 -120 -100 -80 -60

GBW (MHz)

HD3 (dB)

Fig. 5.4 GBW versus HD3

In general, harmonic distortion less than -110dB can be ignored because it is below the noise floor of modulator output spectrum. From（5.20）, Fig. 5.3 and Fig. 5.4, we can obtain the minimum required SR and GBW w. r. t. the specific OSR. The results are summarized in Table 5.1. It is clear from Table 5.1 that as OSR increase, SR increase dramatically so that the effect of settling distortion can be contained.

TABLE 5.1

Minimum SR and GBW required w. r. t. OSR

OSR SR (V /µs) GBW (MHz)

10 ≥7 ≥10

20 ≥13 ≥16

32 ≥23 ≥20

64 ≥36 ≥29

80 ≥50 ≥40

100 ≥66 ≥53

120 ≥78 ≥68

140 ≥85 ≥72

6.

Simulation Results and Validation

In this chapter, we demonstrate the validation of our models that have been introduced in the previous chapter. The second-order single-loop modulator in Fig. 3.1 is used in order to evaluate the proposed models. We use the HSIPCE simulation as shown in Fig. 6.1 and Fig. 6.2, and the related parameters were: fB= 100 KHz, OSR

= 100, C_S = 2pf, C_i = 4pf, and a 100 KHz sinusoidal input signal. Additional parameters are used in the simulation of Fig. 6.3 are listed in Table 6.1. Fig. 6.3 shows the settling noise and distortion obtained by proposed model and simulated output by transistor-level and behavior model. The theoretical noise power by previous model is obtained by adding the previous settling noise power to the theoretical quantization noise power. The output shows a good agreement between the transistor-level modeled and presented modeled modulator.

Fig. 6.1 Circuit-level schematic of spice simulation

Fig. 6.2 Quantizer of spice simulation

10³ 10⁴ 10⁵ 10⁶ 10⁷

-100 -90 -80 -70 -60 -50 -40 -30 -20 -10

Frequency (Hz)

Power Spectrum Density (dB)

Behavioral model Spice model Our model

(a)

10³ 10⁴ 10⁵ 10⁶ 10⁷ -120

-110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10

Frequency (Hz)

Power Spectrum Density (dB)

Behavioral model Spice model Our model

(b)

Fig. 6.3 Comparison of our theoretical result with transistor-level and behavior simulation result

TABLE 6.1

SIMULATION PARAMETERS IN FIG.6.3

Parameters Fig. 6.3 (a) Fig. 6.3 (b)

SR (V /µs) 40 50

GBW (MHz) 65 70

Pn (dB) Behavior: -48.433 (dB) Spice: -50.935(dB) Analytic: -52.757 (dB)

Behavior: -63.439(dB) Spice: -58.862(dB) Analytic: -66.227(dB) HD3amplitude (dB) Behavior: -51.82 (dB)

Spice: -53.09 (dB) Analytic: -53.713 (dB)

Behavior: -67.72(dB) Spice: -68.95(dB) Analytic: -69.676(dB)

As we indicated in the above chapter, the ratio of the signal power to the power of the noise and the distortion components (SNDR) plays a large role in design of Σ∆

modulators. Therefore, it is worth to find the domination between the power of the noise and the distortion. We show the result in Fig. 6.4, and we can observe that the noise energy is dominant over the energy of the distortion. These results are entirely consistent with the previous study [7].

10 15 20 25 30 35 40 45 50 55 60

-160 -140 -120 -100 -80 -60 -40 -20

SR (V/us)

Noise and Distortion (dB)

HD3(OSR=80) HD5(OSR=80) Pn(OSR=80) HD3(OSR=100) HD5(OSR=100) Pn(OSR=100)

Fig. 6.4 SR versus HD3, HD5 and Noise

Notice that increasing SR and GBW will reduce nonlinearities of settling problem and increase SNDR, but will also increase analog power consumption and the design challenges. On the other hand, multi-bit quantizer can reduce the slew rate requirement, since a multi-bit structure makes the output feedback signal closer to the input signal.

7.

Conclusions and Discussions

While considerable attention has been paid in the past to research issues related to the settling problem of Σ∆ ADCs, a literature on issues of the analytical model of settling noise of Σ∆ ADCs has never derived in the literature, and designer only implemented through time-domain behavior simulations due to its complex dynamic behavior. In this paper, we express an analytical model with nonlinear slewing behavior to adequately estimate the Σ∆ ADCs in-band noise power as a function of Σ∆ modulator system parameters, and add more insights to supplement the findings of the settling distortion model that have been presented in [20-21]. Once the system parameters such as OSR, GBW, and SR are known, the models give the expect value of PSD, and predict the powers of harmonics. Both behavior simulations and HSPICE circuits are employed to verify these analytical models, and the results show that our analytical models are sufficiently accurate. Measurement results suggest that for low order Σ∆ ADCs with high OSR and low Bit-number the settling problem will be bigger than other nonlinearities and becomes the dominant nonlinearities.

References

[1] J. Candy, "A Use of Double Integration in Sigma Delta Modulation," Communications, IEEE Transactions on [legacy, pre - 1988], vol. 33, pp. 249-258, 1985.

[2] B. P. Brandt, D. E. Wingard, and B. A. Wooley, "Second-order sigma-delta modulation for digital-audio signal acquisition," Solid-State Circuits, IEEE Journal of, vol. 26, pp.

618-627, 1991.

[3] B. E. Boser and B. A. Wooley, "The design of sigma-delta modulation analog-to-digital converters," Solid-State Circuits, IEEE Journal of, vol. 23, pp. 1298-1308, 1988.

[4] B. DelSignore, D. Kerth, N. Sooch, and E. Swanson, "A monolithic 20 b delta-sigma A/D converter," in Solid-State Circuits Conference, 1990. Digest of Technical Papers.

[4] B. DelSignore, D. Kerth, N. Sooch, and E. Swanson, "A monolithic 20 b delta-sigma A/D converter," in Solid-State Circuits Conference, 1990. Digest of Technical Papers.

在文檔中 模組化在單迴路積分三角類比數位轉換器中積分器充放電雜訊與諧波失真模型 (頁 38-74)