Derivation of Sigma-Delta Modulator Settling noise Power Model
In this section, models of settling noises which appear at ΣΔ modulator output will be derived and expressed in noise power form. This derivation is divided into sampling phase and integration phase.
3.1 Settling Errors of Sampling Phase
From (15) and (17), we can get magnitude of NTF(z) in frequency domain. By calculating the sum of in-band noise power, settling error of sampling phase can be acquired.
3.2 Settling Errors of Integration Phase
As discussed in section II, there are three settling conditions depending on the absolute value of VS. The full slewing case is not considered here because it is not significant. Note that VS at end of each integration interval can be written as
⎪⎩
where β =exp(−Ts/2τ2) and VL =SRτ2/ a1
From（3.2）,the settling error of integration phase can be calculated as following expression:
⎪⎩
To approximate (3.3), we apply least square method and neglect the even terms by reasons of symmetry of (3.3). Then (3.3) can be approximated by
(3.4)
The pi(VS) should be fitted through all the points in that specific interval so that the sum of the squares of the distances of those points from the pi(VS) is minimum. The sum of the squares is
With above method, the determination of coefficients in （3.4） for q to be minimum becomes the solution of follow equations.
[ ]
Note that (3.7) only takes into account the nonlinear curve in (3.7), whereas errors derived from the distribution of VS are omitted. This may lead to a worse estimation of settling noise, especially in the case of small VL. The distribution of VS in (3.6) is
assumed to be uniformed distributed in the specific integral interval. Nevertheless, the distribution of VS should be defined as Gaussian distribution and the weighting function that indicates the probability of VS in the specific interval must be considered so that (3.6) should be de revised as:
[ ]
where W(VS) represents the weighting function of VS. Since the settling noise is highly depends on the distribution of VS, the probability of VS in the specific interval must be defined. As discussed in section II, the VS can be assumed to be Gaussian distribution and the relation between standard deviation σVS and quantizer levels 2B can be approximated by
vs ref
where VH is defined as 2Vref. Then (3.11) is normalized and the weighting function can be expressed as
2 )
Taking into account (3.11), (3.8) can be re-written as
[ ]
Then the values of the coefficients are:
In order to validate (3.12), we apply least square to the VS in three cases. In case one, simulations was carried for a ΣΔ modulator with 3-Bits, OSR = 120, SR = 40V /μs, and GBW = 100MHz and the VS was obtained. The coefficients,α1,α3, and , can be determined by applying least square method to above VS and compare with the ones obtained by another two cases, with Gaussian distribution, and no Gaussian distribution. Fig. 3.1 and Table 3.1 show the VS and coefficients obtained in three cases. The case applied Gaussian distribution show a good fit when compared to the one by simulation. In Fig 3.2, the fitting results in three cases were illustrated and the case with Gaussian distribution is closer to the one simulated than another case. Note that the VL in this case is 0.1681 and the probability of nonlinear operation is respectively 0.35, 0.34, and 0.9 in three cases. This result shows that applying Gaussian distribution to VS plays a crucial role in calculating settling noise.
α5
TABLE 3.1
Coefficients obtained in three cases
Behavioral model
with Gaussian distribution
no Gaussian distribution
α1 0.958 0.94 835.67
α 1.239 1.609 3 -1532.7
α 19.677 16.357 5 567.25
-2 -1.5 -1 -0.5 0 0.5 1 1.5 2
-8000 -6000 -4000 -2000 0 2000 4000 6000 8000
Vs
settling error
Behavioral model
with Gaussian distribution no Gaussian distribution
Fig. 3.2. VS versus settling error in three cases
-2 -1.5 -1 -0.5 0 0.5 1 1.5 2
0 200 400 600 800 1000 1200 1400
Fig. 3.3. The distribution of angle of VS
With
α
3 andα
5 , the next step of calculating settling noise power is the determination of the P.S.D of VS 3 by using the P.S.D of VS.(2.16) is used to destruct a signal in frequency domain on Matlab to represent it as VS.
The height of the power spectral density of VS in frequency domain can be expressed
where α represents the angle of VS. In Fig. 3.3, simulation result shows that the angle of VS is close to a uniform distribution. Therefore, α is considerably assumed to be a arbitrary value in 0~2π. To demonstrate the P.S.D of VS 3, we will begin by considering the square of VS. Since the P.S.D VS has been verify in above discussion, we can use modulation of DTFT Theorems and apply circular convolution to realize square of VS. We can expressed the height of the power spectral density of the square of VS in frequency domain as
In order to compute the expect value of (3.13), we express (3.13) as a sum of different absolute value with a arbitrary value:
+ ...
2
...
2
2
+ B + C +
A
(3.15)Then the expect value of the height of spectral density of square of VS can be defined as
Fig 3.4 shows that the expect value of (3.16) and behavior model simulation with
= 20MHz, Bit = 1.
frequency (Hz)
Fig. 3.4. the expect value of (3.16) and the behavior model simulation result
However, when f is zero α , β,and γ are all zero and the expect value is on longer
( )
879sin . simulation results by behavior model.103 104 105 106 107
frequency (Hz)
Fig. 3.5 The expect value of VS 3 and the simulation result by behavior model
103 104 105 106 107
frequency (Hz)
Amplitude
Fig. 3.6 The expect value of VS 5 and the simulation result by behavior model
Then the expect value of the height of spectral density of settling noise of integration phase can be defined as
5 5 3 3 1
)
1( f h
eh
eh
eh = α + α + α
(3.18)So the settling noise in base band± fBof integration phase can be obtained by integrating (38):
(3.19)
df f h f
h f
h
P
BB
f
f e e e
∫
−+ +
=
1 1 3 3 5 5 22
( α ( ) α ( ) α ( ))
ε
Then total settling noise is
2
1 ε
ε
ε
P P
P = +
(3.20)Note the low frequency region of third and fifth power is absolutely flat and means that the in band noise power will increase if the α3 and α5 in (3.11) increase.
Therefore, the nonlinearity of settling will make an amount increase on noise power.
It is worth noting that settling noise is highly dependent on the high frequency noise.
Due to the noise shaping nature, the high frequency amplitude of VS is great and will lead to large settling noise.
4.
Derivations of Sigma-Delta Modulators Settling Distortion
In analysis of settling noise, the input of integrator, VS, is define as a function of quantization noise and (13) is used to derivate settling noise. However, the VS in this section is defined as a sinusoid and the quantization noise is ignored.
The technique applied in section 3 will be used to calculate settling distortion.
Since the input signal is a sinusoid and the distribution is uniformed distributed in - ~ , the weighting function would not be considered and the coefficients were determined by (25). Then the coefficients were expressed as
AVS AVS
where AVS has defined in (2.19). Note that the validation of the calculation is
VS
L A
V < , otherwise, the settling will operate linearly and has no distortion at output node. VS ≤VL can be further derived as:
GBW RC GBW SR
OSR f BW
A in S
⋅
⋅
⋅
⋅ +
× ≤
⋅ ×
⋅
⋅
⇒ π
π π
2 2 1 5 . 0 2
2 1 2
SR RC GBW
GBW f BW
A OSR
S in
5 . 0 2
1 2 2
2 1
2 + ⋅ ⋅
⋅
⋅ ×
⋅
⋅
⋅
≥
⇒ π
π π (4.2)
Assumingfin=BW,R= 300Ω, CS =2×10−12F, it leads to the following equation:
⎟⎠
⎜ ⎞
⎝
⎛ + ×
⋅
≥
10−10
2 6 1 SR GBW OSR
π π
(4.3)
We then plot（4.3）as shown in Fig. 4.1 which shows that OSR is inverse proportional to SR and is almost independent to GBW.
Fig. 4.1 3D plot of（4.3）
Fig. 4.1 indicates that if we design SR and GBW above the curve with desired OSR, the modulator would have no harmonic distortion. It shows that the op-amp slew rate needs to be at least 200V/us, then the modulator can have no harmonic distortions with OSR larger than 15. Although op-amps operate in linear region can have no harmonic distortion, it may consume more power dissipation (because large slew rate).
Therefore, there has a trade off between power consumption and harmonic distortion.
In general, one can choose smaller slew rate to let power consumption lower and have negligible harmonic distortions.
In order to verify the result in （4.1）, we use SIMULINK to build a second-order modulator with a multi-bit quantizer. The behavioral settling model in [11] is employed. We assume that SR = 70
ΣΔ
s
V/μ , GBW = 100MHz, R = 300Ω , OSR = 16,
= 1MHz and = 2pF, and a 1MHz sinusoidal input signal is used. After performing FFT to the output data of the modulator, we obtain the simulated P.S.D which is shown in Fig. 4.2 It shows that HD3 is -115.1dB and HD5 is -119.9dB. The theoretical harmonic powers calculated from（4.1） are HD3 = -116.4dB and HD5 = -120.3dB. The simulated and theoretical results are very close, and this confirms that our settling distortion model is reasonably precise.
fB
CS
ΣΔ
106 107
-250 -200 -150 -100 -50 0
X: 3e+006
Y: -115.1 X: 5e+006
Y: -119.9
frequency (Hz)
Power Density (dB)
Fig. 4.2 Output spectrum of a second-order ΣΔ modulator with harmonic distortion
In order to provide insight on how settling distortions are related to circuit and
⎟⎟
⎠
⎞
⎜⎜
⎝
⎛
⎟⎟
⎠
⎞
⎜⎜
⎝
= ⎛
2 4 log 1 20 ) ( 3
3 3 VS settling
dB A
HD α
=20
[
logα3 +log(2AωT)3−log4 2]
=20logα3 −60logOSR+30.095 （4.4）
15 . 48 log
100 log
20 ) (
5 dB = 5 − OSR+
HD settling α
From （4.4） we can see that OSR can effectively influence settling harmonic powers.
The（4.4）reveals that α3 and α5 are functions of T, GBW, R, and SR. In order to place much more emphasis on relationship between GBW and the settling distortion, Fig 4.3 shows HD3 with SR=50V/us, R = 300
CS
Ω , OSR = 16, fB= 1MHz and Cs = 2pF, and a 1MHz sinusoidal input signal. Similarly, Fig. 4.4 shows SR vs. HD3 with GBW=50MHz.
50 100 150 200
-160 -150 -140 -130 -120 -110 -100 -90 -80
GBW (MHz)
HD3(dB)
Fig. 4.3 GBW v.s HD3
10 15 20 25 30 35 40 45 50 -160
-140 -120 -100 -80 -60 -40 -20 0
SR(V/us)
HD3(dB)
Fig. 4.4 SR v.s HD3
The simulated and theoretical results are very close, and this confirms that our settling distortion model is reasonably precise.
In general, harmonic distortion less than -110dB can be ignored because it is below the noise floor of modulator output spectrum. From（39）, Fig. 4.4 and Fig. 4.5, we can obtain the minimum required SR and GBW w. r. t. a specific OSR. The results are summarized in Table 4.4.
It is clear from Table 4.1 that as OSR decreases, SR have to increase dramatically so that the effect of settling distortion can be contained. This can be explained by（39）, since T increases when OSR decreases.
TABLE 4.1
Minimum SR and GBW required w. r. t. OSR
OSR HD3(dB) SR
) / (V μs
GBW
(MHz)
2 20logα3 -24 ≥180 ≥430
4 20logα3 -42 ≥150 ≥400
8 20logα3 -60 ≥120 ≥370
16 20logα3 -72 ≥100 ≥350
32 20logα3 -78 ≥80 ≥340
64 20logα3 -89 ≥50 ≥320
100 20logα3 -90 ≥30 ≥300
Fig. 5.1 Circuit-level schematic of spice simulation
Fig. 5.2 Quantizer of spice simulation
104 105 106 107 -140
-120 -100 -80 -60 -40 -20
frequency (Hz)
Power Spectrum Density (dB)
Behavior Simulation Spice simulation our model
(a)
103 104 105 106 107
-120 -100 -80 -60 -40
-20 Behavior Simulation Spice Simulation our model
(b)
103 104 105 106 107
-110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10
frequency (Hz)
Power Spectrum Density (dB)
Behavior Simulation Spice Simulation Our model
(c)
5.
Simulation Results and Validation
In order to demonstrate the validity the model presented in previous section, we use the spice simulation shown in Fig. 5.1 and Fig. 5.2 The relevant parameters were:
kHz, OSR = 100, CS = 0.5pf, Ci = 1pf, and a 100 kHz sinusoidal input signal.
Additional parameters used in the simulation of Fig. 5.3 are listed in Table 5.1. Fig.
5.3 shows the settling noise obtained by presented model and simulated output by transistor-level and behavior model. The theoretical noise power by previous model is obtained by adding the previous settling noise power to the theoretical quantization noise power. The output shows a good agreement between the transistor-level modeled and presented modeled modulator.
=100 fB
Notice that increase OSR will increase settling noise and reduce SNR. Then we do the same simulation with different OSR. Fig. 5.4 indicates the noise power at modulator output, which is a combination of quantization noise and settling noise.
Notice that increasing SR and GBW will reduce settling noise and increase SNR, but will also increase analog power consumption and the design challenges. On the other hand, multi-bit quantizers can reduce the slew rate requirement, since a multi-bit structure makes the output feedback signal closer to the input signal.
ΣΔ
20 40 60 80 100 120 140 160 180 -75
-70 -65 -60 -55 -50 -45 -40
In Band Noise Power(dB)
OSR spice simulation presented model
Fig. 5.4 P.S.D of settling noise obtained from transistor-level simulation and previous established model
The previous study reveals that as non-idealities or OSR increases, the settling noise will rise dramatically and degrade the performance of ΣΔ modulator. Because high non-idealities reflect high-frequency noises into base band, first order modulator maybe is a more efficient architecture than second order. In order to make an efficient choice between first and second order, we calculate the minimum required SR and GBW w. r. t. a specific OSR. The results are summarized in Table 5.2. Table 5.1
indicates that as OSR increase, the bigger SR and GBW are needed to cope with the settling noise.
ΣΔ
TABLE 5.1
SIMULATION PARAMETERS IN FIG.5.3
Parameter Fig. 5.3(a) Fig. 5.3(b) Fig. 5.3(c)
SR(V /μ s) 160 80 60
GBW(MHz) 160 127 95 P (dB) ε -85.4 -68.48 -49.2
TABLE 5.2
MINIMUM SR AND GBW REQUIRED W. R. T.OSR
OSR PQ of fist order modulator ΣΔ
SR ) / (V μ s
GBW
(MHz)
16 6.69×10−5 ≥6 ≥20
32 8.37×10−6 ≥20 ≥40
64 1.05×10−6 ≥50 ≥75
80 5.35×10−7 ≥60 ≥120
100 2.74×10−7 ≥100 ≥140
120 1.59×10−7 ≥140 ≥160
140 1×10−7 ≥200 ≥220
6.
Conclusions and Future Works
The analytical model of settling noise of ΣΔ ADCs is never derived in the literature to date and can only be performed through time-domain behavior simulations due to the complex dynamic behavior. In this paper, we have established an analytical model with nonlinear slewing behavior to adequately estimate the ADCs in-band noise power as a function of
ΣΔ ΣΔ modulator system parameters. Once the system parameters such as OSR, GBW, and SR are known, the model gives a expect value of PSD. Both behavior simulations and HSPICE circuits are employed to verify these analytical models, and the results show that our analytical models are sufficiently accurate. Measurement results suggest that for high order ADCs with high OSR and low Bit-number the settling noise will be bigger than other noises and becomes dominate noise source.
ΣΔ
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