Simulation Results

The simulation platform is build by Matlab and C language with infinite word length. The DVB-T baseband receiver can compensate the CFO to 50 subcarrier spacing (about 200kHz at 2k mode) and the SCO to 100ppm. In simulation environment, the fallowing variables are used:

CFO = 23.15 subcarrier spacing, SCO = 100 ppm, AWGN = 16.5 db and Rayleigh channel. Fig.

3 is the maximum correlation output, and the peak means the location of OFDM. Fig. 4 and Fig.

5 is the convergence curve of CFO and SCO. The convergence time is about 40 OFDM symbol.

Fig. 6 is the interpolation control. The saw means that input signal needs to copy a sample.

0 2000 4000 6000 8000 10000 12000 14000 16000 18000

0 0.05 0.1 0.15 0.2 0.25

sample index

maximun correlation amplitude

Fig. 3 symbol boundary detection

20 40 60 80 100 120 140 160 180 200

Fig. 4 CFO convergence curve

20 40 60 80 100 120 140 160 180

Fig. 5 SCO convergence curve

1 2 3 4 5 6 7 8 9 10 11 x 10⁴ 0.1

0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

sample index

fractional delay (1/ sampling time)

Fig. 6 Interpolation control

3 Memory-less Algorithm for ICFO Estimation

An ICFO estimation algorithms [2] [3] requires a copy of previous symbol shown in Fig. 7.

However, the maximum FFT length of DVB-T is 8192. If data word length of FFT output is N bits. It needs to store 8192 × 2 × N bits, which occupy large size. Besides, the correlation operations accesses data of a symbol saw-toothedly shown in Fig. 8. Thus data accessed many times (more than 5 times), and this will increases the power consumption. The sawed–toothed access is caused by the overlapping between estimating ranges of ICFO. By reducing the usage of the continual pilots, the situation of overlapping is avoided. We choose a set that the interval of continual pilot exceeds 100 sub-carriers spacing. The set is {54, 156, 279, 432, 618, 759, 873, 984, 1101, 1206, 1323, 1491}. The number of used continual pilot is 12.

Fig. 7 Block diagram of integer CFO estimation

Fig. 8 Data are accessed saw-toothedly

After solving saw-toothed access, we reduce the usage of storage unit for one symbol delay.

Only sign bit of previous OFDM symbol is stored. The advantage of this simplification is not only to decrease the number of storage unit, but also to substitute the multiplication in the correlation with addition and subtraction. The memory-less algorithm is as follows:

( ) ( )

where z is FFT output signal, l is symbol index, k is subcarrier index, φ is the estimated CFO and cpilot is the set of continual pilot. φ

Because only the sign bit of the symbol is stored, it is not necessary to store at every sample that come form FFT output. By using N shift register to store N sign bits of symbol, memory is accessed in every N clock cycles, where N is ward length of memory.

Fig. 9 is performance comparison between the original algorithm and the memory-less one.

The test environment is at Rayleigh Channel, CFO = 30.12 subcarrier spacing. The number of test times is 2000. At SNR = 16 dB, the error ratio of the memory-less algorithm is about 8x10^-2

hardware complexity comparison between the original algorithm and the memory-less one.

When memory word length N is 12 bits and the estimation n is 50 subcarrier spacing. The usage of memory reduces 90 %, the access number reduces 94%, and the estimation time reduces 37%.

12 continual pilot used,signed data fully continual pilot used,fully data bits

SNR

Fig. 9 The error ratio of ICFO estimation Table 1 Hardware complexity of ICFO estimation

Conventional New proposed

Storage unit 2048×2×N ⎡^2048/N⎤×2×N

Fig. 10 is the state diagram of jointed ICFO, RCFO and SCO estimation. The first state is to write the sign bit of current OFDM symbol. When next symbol comes from the FFT, it jumps to the second state. In this state, the coming OFDM symbols also are also stored and one correlate with previous stored symbol to generate the integer CFO estimation. In order to

decrease the error ratio of estimation, a voting mechanism is added. This voting mechanism will watch 2~3 OFDM symbol. If 2 among 3 estimations are the same, the value will be considered cowed. With this mechanism, we can reduce the error rate form 10^-2 to 10^-4~10^-6. After estimating the ICFO, a mechanism is used to release hardware resource for RCFO and SCO estimation. In the third state, fully information bits of continual pilots in an OFDM symbol are written into memory. In the fourth state, the continual pilots of two OFDM symbol are correlated and the RCFO and SCO are estimated.

Fig. 10 State diagram of the jointed estimation

The overall architecture for jointed estimation is shown in Fig. 11. ICFO estimation, RCFO and SCO estimation share a memory. The Arctan block and Abs block share the same CORDIC unit for hardware reuse. The operation of this architecture is following the state diagram shown in Fig. 10. In ICFO estimation, the sign bit of samples coming from the FFT output are streamed in the shift registers. After shift registers is full, the temporarily stored data are written into memory. This decease number of access. Another memory is used to store the correlation results. After correlation is complete, the Abs block is used to compute magnitude of the correlation result. The Argmax block finds the index of maximum correlation results which means the ICFO. In RCFO and SCO estimation, the continual pilots are stored into the memory and correlation with the next symbol. The correlation results are divided into two set which describe in Eqn. (3). The summation can compute the CFO, and the subtraction can compute the SCO. The hardware complexity is listed in Table 2.

Fig. 11 Architecture of jointed estimation Table 2 Hardware required for jointed estimation

Memory 171 x 24 (ICFO RCFO & SCO) 101 x 26 (ICFO)

CORDIC 1 (11 iterations )

Multiplier 0 (ICFO)

4 (RCFO & SCO)

Adder 4 (ICFO)

4 (RCFO & SCO)

4 Conclusion and Discussion

In this year, we carry out a simulation platform for DVB-T, which contains digital down converter, carrier recovery loop, sampling timing recovery loop and frequency domain equalizer. At the same time, several simulation results are showed. The convergence time is about 40 OFDM symbol. Besides, a memory-less algorithm reduces the usage of memory reduces 90 %, the access number reduces 94%, and the estimation time reduce 37%., but does not decrease performance a lot. Finally, the architecture of jointed ICFO, RCFO, and SCO is proposed.

5 Reference

[1] ETSI, “Digital Video Broadcasting: Framing Structure, Channel Coding and Modulation for Digital Terrestrial Television, European Telecommunication Standard EN 300 744 V1.5, .November, 2004.

[2] M. Speth, S. Fechtel, G. Fock, H. Meyr, “Optimum receiver design for wireless broad-band systems using OFDM. part I,” IEEE Transactions on Communications, vol. 47, No.11, Nov. 1999, pp. 668 - 1677

[3] M. Speth, S. Fechtel, G. Fock, H. Meyr, “Optimum receiver design for OFDM-Based Broadband Transmission part II: A case study,” IEEE Transactions on Communications, vol. 49, No 4, Apr. 2001, pp. 571 - 578 [4] Dong-Seog Han, Jae-Hyun Seo, Jung-Jin Kim “Fast carrier frequency offset compensation in OFDM

systems,” IEEE Transactions on Consumer Electronics, vol. 47, No. 3, Aug. 2001, pp. 364 - 369

[5] Youngho ahn, Seunghyeon Nahm, Wonyong Sung, “VLSI design of a CORDIC-based derotator,” in Proc.

ISCAS '98, pp. 449 - 452

[6] F.M. Gardner, “Interpolation in digital modems. I. Fundamentals,” IEEE Transactions on Communications, vol. 41, No. 2, March 1993, pp. 501 - 507

[7] Ludwig Schwoerer, “Fast pilot synchronization schemes for DVB-H,” proceedings of 4th IASTED, 2004, Banff, Canada.

可供推廣之研發成果資料表

□ 可申請專利 ;可技術移轉 日期：94 年 5 月 31 日

國科會補助計畫

計畫名稱：子計劃四：數位電視廣播接收器之數位解調與同步設 計及其平台與晶片製作

Digital Demodulation and Synchronization Platform Design and Chip

技術說明 英文： We design the digital back-end subsystems of DVB-T. These subsystems include digital frequency down converter, channel

estimation/equalization and synchronization. The goals are not only to design and implement these subsystems but also integrate (cooperated with other subprojects) all the demodulation and decoding systems into an System on Chip (SoC).