From the chapter above, we have described a method to determine operation frequency from delay time, and it is also demonstrated that the Vth variation of device mainly affects circuit performance in whole parameters. In this chapter, we wil propose a simulation skill to predict operation frequency of an n-stage shift register through simplifying propagation delay from an n-stage one to an 1-stage one. The power dissipation of an n-stage shift register is also estimated in the same way.
4-1. Estimation of Operation Frequency 4-1-1. Worst Case V.S. Monte Carlo
In the chapter 2, we have mentioned that the most frequently used Worst-Case parameters in a practical design are ones that represent “maximum” and “minimum”
current of PTFT and NTFT transistors. Because the delay time of cells depend on transistor current, “maximum” and “minimum” parameters correspond to the “fast ” and ”slow” case, respectively. Although Worst-Case is widely used in a practical design, it does not have enough accuracy while comparing with that of a Monte Carlo analysis. Fig. 4-1-1 shows a distribution of gate delay calculated by the Monte Carlo analysis with 1000 SPICE simulations. Two worst-case values calculated by Worst-Case and Monte Carlo analysis are indicated as “corner” and “MC”, respectively. From Fig. 4-1-1, the worst-case rang of the Worst-Case simulation is 19% wider than the range of the Monte Carlo analysis. In order to obtain the high accuracy of Monte Carlo analysis, one has to develop simulation skills to save
simulation time.
4-1-2. One-Stage Shift Register
Over the past few years, several studies [2,3] have been conducted on future application potential of LTPS TFT LCD display. Some of the most compelling studies have focused on typical simulation of an one-stage shift register. For example, Fig.
4-1-2 shows the operating frequency of a shift register simulated as a function of variations in the field effective electron mobility and channel length. The results show the interesting trends while designing LTPS TFTs digital circuits, e.g. , when a timing controller with a 3V voltage source is integrated into LCD panel whose resolution is VGA (25 MHz dot clock), the electron mobility of an N-type TFT higher than 200 cm2/Vs and channel length shorter than 2um for the TFT characteristics are needed.
However, little attention has been given to the estimation of delay with device variations. Let us begin with the observation of one-stage simulations for Monte Carlo method compared with typical method. The trend of operation frequencies of one-stage shift register with different supply voltages were investigated by means of Monte Carlo and Worst Case simulations using Vth ± 3σVth, as shown in Fig. 4-1-3.
From Fig. 4-1-3, the typical result obviously over-estimating than Monte Carlo results.
It is said that one-stage simulations have an advantage in predicting operating frequency in LTPS TFTs digital circuits. However, there seems to be no established theory to explain this trend. In digital circuits a path delay is one of the most important performances, so that it is necessary to analyze the variability of the path delay. In next section, we will now discuss the derivation of path delay from one-stage to n-stage shift register more closely.
4-1-3. N-Stage Shift Register
First of all, we will focus our attention on deviation of path delay [1]. The probability distribution function pdf of gate delay can be modeled by an normal distribution function N(m,σ2)fully characterized by its mean value and its variance
2
whereσdelay is defined as the deviation of half-stage delay
The average delay of a path comprising n stages corresponds to the linear combination of the n pdfs of the gate delays. The average path delay is given by
∑
−
=
ni delayi
path
d
d
(4-2)With the symmetrical covariance matrix C ~
ρij: correlation between two different half-stages the variance of the path can be expressed as
∑∑
⋅ ⋅=
∑∑
n = ⋅ ⋅Equation (4-5) can be simplified to
Forρij =ρ, i.e., the integrate correlation is the same for all half-stages
∑
The distance dependent correlation of the gate delay on the chip is given by the autocorrelation coefficient ρ [5]. As the device variations of each shift register have no relevance to distance, i.e., the device variation is independent to distance. The autocorrelation coefficient ρ can be set toρ =0. Here, with the variance of a half-stage shift registerσdelayi2, the variance of a path comprising n gates is given as
∑
=It will be clear from Eq. (4-7) that the variance of a path comprising n half-stages is the linear combination of each half-stage delay. Fig. 4-1-4 shows the average and deviation delays of different nth half-stage on delay time with 30 Monte Carlo simulations. From Fig. 4-1-4, it is seen that the device variations correspond to different deviation of delays
σ
delayi are similar to each other. Thus, Eq. (4-7) can be approximated toFinally, as mentioned that the determination of operation frequency determined in chapter 2, operation frequency finally can be written as
)
where m is described as mean value with Monte Carlo results of an half-stage shift register.
The trend of operation frequencies composed of various n half-stage shift registers with different supply voltages were calculated by Eq. (4-9). The results are shown in Fig. 4-1-5. It was found from the results that operating frequencies showed a reduced ration
n
1 while gradually increasing half-stage numbers.
4-2. Estimation of Power Dissipation
The histogram of the power dissipation for the good cases is shown in Fig. 4-1-6, which exhibits normal distribution. This Monte Carlo approach is believed to give better approximation to the actual circuit performance for LTPS TFTs because that it makes no restrictive assumptions on the nature of the relationship between the circuit parameters and the circuit performance.
As for the power consumption, after excluding the failed cases, the linearly product method can be applied, as shown in Table Ⅱ. That is, the power distribution of an n-stage shift register circuit (PEn) can be estimated by the results of Monte Carlo simulation for 3-stage shift register (PMC3)
Average (PEn) = Average (PMC3) ×
n / 3
(4-10) andDeviation (PEn) = Deviation (PMC3) ×
n / 3
(4-11) respectively.The comparison between PE20 and PMC20 at 10, 11, and 12MHz is listed in Table II. For the frequencies with enough good cases, the errors for the average and deviation are as low as 3% and 8%, respectively.