As mention before, the multiphase generator is used to generate 32 phases between one clock cycles. In other word, the phase error 32 means that signal is delay one cycle, and the phase error 0 means that sign is at ideal phase. With different initial phase error and SNR=14, after timing synchronizer, the final phase errors are convergence into 4 phases, as shown in Figure 21. In TABLE V, the value of root mean square error is more and more larger with SCO increasing, but the probability density function still is Gauss distribution and mean is near to zero .
TABLE IV SIMULATION PARAMETERS
Parameter Value
MCS Set 86
Antenna No. 8*8
Modulation 64 QAM
Coding Rate 2/3
PSDU Length 4096 Bytes
Carrier Frequency 2.4 GHz
Bandwidth 80 MHz
IFFT / FFT Period 25.6 s (2048-FFT)
TABLE V
RMS OF SAMPLING PHASE ERROR
SCO(ppm) 10000 20000 30000 40000
RMS 1.9882 1.8237 2.2410 3.8890
Variance 3.8919 3.3043 4.1429 7.1407 Figure 21: PDF of sampling phase error
To compare with perfect synchronization at 8% PER, SNR losses are about 0.29 dB of SCO=0ppm and 0.51dB of SCO=40000ppm, as shown in Figure 22.
Figure 22: The system performance with 64-QAM SNR=14-dB, 100-ns RMS delay spreading
Figure23 shows the root mean square of sampling errors. No synchronization sample means without an algorithm to fix the error of an unknown initial phase. Those initial phase is random to generate and its RMS is about 9.1~9.5 (phase). The value of RMS is decreasing with the increas-ing of SNR and converges to 2 phases.
The required packet-error rate (PER) is 8% under a packet length of 4096 byte, 64 QAM, IEEE frequency-selective fading with an RMS delay spread of 100 ns. Figure 24 displays the offset tolerance with various SNR and modulations which can be as high as 40000~-30000-ppm, much larger than the 25 ppm in most wireless standards.
Figure 23: The root means square error of sampling phase with 64-QAM SNR=14-dB, 100-ns RMS delay spreading
Figure 24: Offset tolerance with SNR=14-dB, 100-ns RMS delay spreading
CHAPTER 5
HARDWARE IMPLEMENTATION
A synchronization scheme for 64-FFT 4*4 MIMO-OFDM systems is implemented. Figure 25 shows the architecture of hardware implementations, and the input are the received data after 16-FFT. In the architecture of timing synchronizer, there are two algorithm which are described in chapter3. There are four sets calculators for each antenna to calculate SCO and sampling
Figure 25: Architecture of hardware implementation
TABLE VI
HARDWARE SPECIFICATIONS
Hardware specifications
Application IEEE 802.11n MIMO-OFDM
Space-Time Coding STBC
Support Antenna Configuration 4 Tx, 4 Rx
Support Modulation Type BPSK, QPSK, 16-QAM, 64-QAM
Technology 0.18 m 1P6M CMOS
System Clock 20 MHz
TABLE VII AREA REPORT
Area Report
Combinational area 4785241.500000 Noncombinational area 209007.562500
Total cell area 4995827.000000
The hardware specifications and area reports are listed in TABLE VI, TABLE VIII respec-tively.
CHAPTER 6
CONCLUSIONS AND FUTURE WORKS
For OFDM timing synchronization, a frequency-domain synchronizer to is in-vestigated to offer fast recovery and wide tolerance. The A/D phase adjustment is thesis, we only consider the multipath and AWGN, but man-made noise and jam-ming are also a source to affect the accu-racy of timing synchronization. Since
timing synchronization is in the first stage of receiver, there will be many non-ideal front-end ef-fects which are not improved yet. Hence, we have to improve the proposed algorithm again these effect in the future. The measured EVM are listed in TABLE VII. They hint that the proposed frequency-domain timing synchronizer in certain wireless situations.
TABLE VII summarizes the features with related works [15-16, 20-21, 23-25].
TABLEVIII
VLSI Type Mixed-Mode Mixed-Mode All-Digital All-Digital All-Digital All-Digital All-Digital All-Digital Architecture DAC + VCXO DAC + VCXO ADPLL
(PTCG)
Non-PLL/DLL
(ADCM) Interpolator Interpolator Interpolator Non-PLL/DLL (ADCM) Sampling Mode Synchronous Synchronous Synchronous Synchronous Asynchronous Asynchronous Asynchronous Synchronous
Control Factor Frequency Frequency 8 Phases 32 Phases Fixed Clock Fixed Clock Fixed Clock 32 Phases
Sampling Rate N/A 4x 1x 1x 4x 2x 4x 1x
Cycle Count 40 symbols 380 symbols N/A 4 symbols N/A 32~64 symbols 100 symbols 6 symbols
Tolerant Range N/A N/A N/A 400 ppm 200 ppm N/A 100 ppm 30000 ppm
References
[1] Wang Dan, Hu Ai qun, “A Combined Residual Frequency and Sampling Clock Offset Esti-mation for OFDM Systems,” IEEE Trans. Circuits and Systems pp. 1184-1187, 2006.
[2] Dong Kyu Kim, Sang Hyun Do, Hong Bae Cho, Hyung Jin Chol, Ki Bum Kim, ”A new joint algorithm of symbol timing recovery and sampling clock adjustment for systems,” IEEE Trans. Consumer Electronics, vol. 44, pp. 1142-1149, 1998.
[3] M. Sliskovic, “Sampling frequency offset estimation and correction in OFDM systems,”
IEEE International Conference in Electronic Circuits and Systems, vol. 1, pp. 437-440, 2001.
[4] M. Sliskovic, “Carrier and sampling frequency offset estimation and correction in multicarrier systems,” IEEE Global telecommunications Conference, vol. 1, pp. 285-289, 2001.
[5] Yuanxin Xu, Ling Dong and Cheng Zhang, ”Sampling Clock Offset Estimation Algorithm Based on IEEE 802.11n,” IEEE International Conference in Networking Sensing and control, vol. 1, pp. 523-527, 2008.
[6] D. Fu and A. N. Willson Jr., "Trigonometric polynomial interpolation for timing recovery,"
IEEE Trans. Circuits and Systems I: Fundamental Theory and Applications, vol. 52, pp.
338-349, 2005.
[7] B. Yang, K.B. Letaief, R.S. Cheng, and Z. Cao, “Timing Recovery for OFDM Transmission,”
IEEE J. Select Area in Commun, vol. 18, pp. 2278-2291, Nov. 2000.
[8] M. Kiviranta, "Novel interpolator structure for digital symbol synchronization," IEEE/ACES International Conference in Wireless Communications and Applied Computational Electro-magnetics, pp. 1014-1017, 2005.
[9] J. Selva, "Interpolation of Bounded Bandlimited Signals and Applications," IEEE Trans. Sig-nal Processing, vol. 54, pp. 4244-4260, 2006.
[10] A. Enteshari, R. Pasand and J. Nielsen, "A novel technique for fast clock phase and fre-quency offset simulation in digital communication systems," Canadian Conference in Elec-trical and Computer Engineering, pp. 2460-2463, 2006.
[11] Ser Wah Oh, "Accuracy enhancement for initial timing acquisition through lagrange inter-polation," IEEE Wireless Communications and Networking Conference, pp. 2436-2440, 2007.
[12] H. Meyr, M. Moeneclaey, and S. A. Fechtel, “Digital Communication Receivers – Synchro-nization, Channel Estimation and Signal Processing,” Wiley, 1998.
[13] A. F. Molisch, “Wideband Wireless Digital Communications,” Englewood Cliffs, NJ: Pren-tice-Hall, 2001.
[14] John Terry and J. Heiskala, “OFDM Wireless LANs: A Theoretical and Practical Guide,”
Indianapolis, Indiana, Sams, 2002.
[15] A. I. Bo, G. E. Jian-hua and W. Yong, "Symbol synchronization technique in COFDM sys-tems," IEEE Trans. Broadcasting, vol. 50, pp. 56-62, 2004.
[16] Y. Song and B. Kim, "Low-jitter digital timing recovery techniques for CAP-based VDSL applications," IEEE J. Solid-State Circuits, vol. 38, pp. 1649-1656, 2003.
[17] A. Jennings, and B.R. Clarke, “Data-Sequence Selective Timing Recovery for PAM sys-tems,” IEEE Trans. Commun, vol. 33, pp. 360-374, July 1985.
[18] W.G. Cowley, and L.P. Sabel, “The performance of Two Symbol Timing Recovery algorithm for PSK demodulators,” IEEE Trans. Commun, vol. 42, pp. 2345-2355, June 1994.
[19] A.N. D`Andrea, and M Luise, “Optimization of Symbol Timing Recovery for QAM Data Demodulators,” IEEE Trans. Commun, vol. 44, pp. 339-406, March 1996.
[20] J.-Y. Yu, C.-C. Chung, H.-Y. Liu, Y.-W. Lin, W.-C. Liao, T.-Y. Hsu and C.-Y. Lee, "A 31.2mW UWB baseband transceiver with all-digital I/Q-mismatch calibration and dynamic sampling," IEEE symposium on VLSI Circuits, pp. 236-237, 2006.
[21] Terng-Yin Hsu, You-Hsien Lin and Ming-Feng Shen,”Synchronous Sampling Recovery with All-Digital Clock Management in OFDM Systems”,2007
[22] 802.11n standard, “TGn Sync Proposal Technical Specification”, IEEE 802.11-04/0889r7, July 2005.
[23] E. Oswald, "NDA based feedforward sampling frequency synchronization for OFDM sys-tems," in IEEE Vehicular Technology Conference, pp. 1068-1072, 2004.
[24] Wei-Ping Zhu, Y. Yan, M. O. Ahmad and M. N. S. Swamy, "Feedforward symbol timing re-covery technique using two samples per symbol," IEEE Trans. Circuits and Systems I:
Fundamental Theory and Applications, vol. 52, pp. 2490-2500, 2005.
[25] M. Zhao, A. Huang, Z. Zhang and P. Qiu, "All digital tracking loop for OFDM symbol tim-ing," in IEEE Vehicular Technology Conference, pp. 2435-2439, 2003.