In adaptive feedforward (two-sensor configuration) and feedback (one-sensor configuration) noise and vibration control system, the controller software can be in real time (at each sample period) or at a rate slower than real time. Typically, the adaptive filter output must be calculated in real time and the other operations such as user’s input/output can be done off-line. Real time code is usually interrupt driven;
i.e., when a data sample is ready, a signal is sent to the microprocessor to stop what it is doing and then to execute a specified operation such as calculation of the filter output in this instance. Dividing the controller code into an interrupt-driven real time part and an off-line background part often leads to more efficient use of the processor, especially in large scale implementation.
The code in microprocessor can be generated in a number of programming languages: a low-level assembly language and a variety of high-level languages such as C. Programming in higher level language is generally far simpler than in assembly language. However, the complied code written in assembly language executes, usually significantly, faster. A better strategy is to write the real time part of the code in assembly language, and the off-line code may be written in a higher level language. DSP can support either fixed point (integer number) or floating point (real number) calculation. In general, a fixed point processor is less expensive because of its simple hardware structure, however, the calculation is prone to numerical problems such as truncation error. As most fixed point processors have floating point libraries and functions, it is not uncommon to implement controller on a fixed point chip with fixed point real time filtering code and floating point weight adaptation. More complex programming is thus required.
The advent of digital signal processor provides more computational speed to facilitate active noise and vibration control. The controllers described in previous
chapters are implemented by a TMS320C32 DSP. There are two important features of the assembly code of TMS320C3x family DSPs in high-speed computation. One is the circular addressing mode where the circular buffer is used to implement a sliding window that contains the most recent data to be processed. As new data is brought in, it overwrites the oldest data to save the executive time of moving data in C language. Another is the parallel-operation instruction that makes a higher degree of parallelism possible. These two features are the main difference in computational speed between C-code and assembly code.
Figure 4.1 shows the TMS320C3x DSP Start Kit (DSK) with the external boot, erasable, programmable, read only memory (EPROM) module. The TMS320C3x DSK includes: (1) an industry-standard TMS320C31 floating point DSP of 32-bit, 40-ns instruction cycle time, 50 MFLOPS, and 25MIPS, (2) a standard or enhanced parallel printer port interface for communication with PC programs, (3) a TLC32040 analog interface circuit for analog data acquisition, which includes variable rate analog-to-digital converter (ADC) in 14-bit dynamic range at 20 K sampling rate, output reconstruction filter and bypassable, switched-capacitor anti-alias input filter, (4) the standard RCA plug connectors for analog input and output. The TMS320C31 DSK with the external boot EPROM will execute a bootload operation from an address. The number of software wait-states defined in the bus control register must be sufficient for the EPROM operation plus the time delay for the boot signal to be decoded. In this design, the TMS27C040-10 EPROM has a clock speed of 100 ns.
The decoder of 25 ns, and the DSP signal delay of 13 ns, so that the bus cycle time will need 138 ns. With three wait-states the bus read time is (3+1)×40 ns =160 ns (TMS320C31 of 40ns cycle time) to ensure proper operation.
The TMS320C31 DSP is a 32-bit processor while the TMS27C040 is an 8-bit EPROM. Although, the target word of the firmware must be 32-bit, one could split a
32-bit word into (four) multiple 8-bit consecutive memory words. After all four 8-bit words are loaded from the 8-bit EPROM to the DSP, the 32-bit word is reconstructed by combining them. In this way, the boot firmware can be stored only in an 8-bit EPROM.
Figure 4.2 shows the applications of the active noise and vibration control with the standalone DSP controller. The analog signal of the error sensor can be directly sent into the input port, and the analog signal of control output can be read from the output port. In the noise control headset, a sound detection circuit with a condenser microphone, a pre-amplifier, and a low-pass filter (optional) is also developed as shown in Fig. 4.3. The condenser microphone requires an external power source of direct current voltage bias to operate. In order to achieve the desired performance of noise cancellation, the sensor and speaker have to have desired characteristics in low frequency range. This standalone DSP controller design makes the adaptive noise and vibration control in one-sensor configuration feasible in engineering implementation.
Alternatively, a C31 DSP system board is developed as shown in Fig. 4.4.
This board includes: (1) a TMS320C31 floating point DSP of 32-bit, 50-ns instruction cycle time, (2) a 32K words (32-bit wide) of external static random access memory (SRAM), (3) 512K bytes of EPROM, (4) a stereo audio codec CS4218, and (5) a general purpose low-pass amplifier. This design is compatible with TMS320C3x DSK. A specific program can be debugged on the TMS320C3x DSK board and then execute from the EPROM without any connection through the PC. The stereo audio codec CS4218 provides 16-bit input and output (I/O) with a maximum sampling rate of 50 KHz per channel and includes two sets of analog-to-digital converters (ADCs) and digital-to-analog converters (DACs). Both ADCs and DACs use delta-sigma modulation with 64x oversampling. The anti-aliasing input and smoothing output
digital filters are also contained in the codec chip. The processor’s TCLK0 signal is used as the master clock of the CS4218 codec, which controls the A/D and D/A conversion rates. By setting the appropriate period register of the timer, different sampling rates can be achieved. The codec’s REFBUF signal is used for biasing the amplifiers and allowing the input signals without DC offset such that only one power source of +5V is need. Figure 4.5 shows the component- (top-) side layout, the solder- (bottom-) side layout, the silkscreen, and the hardware of the C31 DSP system board. The C31 DSP system provides an example of developing a low cost and efficient standalone DSP controller for active noise and vibration control that facilitates the transition from laboratory experiments to engineering applications.