Source of Power Consumption

It has shown that 50% to 80% of power cost is due to memory traffic in Chapter 1. Our target system is a typical memory-intensive embedded system. According to the Amdahl’s law, we tend to reduce the power consumption on buses.

Power dissipation in CMOS circuits can be considered as composed of a static and a dynamic component. Static power is due to the leakage current. However, in

“well-designed” CMOS devices, static power dissipation can be considered

insignificant in most designs [5]. Dynamic power is the main source dissipation for most CMOS designs. Leakage power will become a significant problem as process feature sizes decrease, but one that we will not discuss [6]. The dominant part of the power dissipation in CMOS circuits is thus the dynamic component, which is in turn composed of two terms. The first term, indicated as the switching power, is due to the charge and discharge of the circuit node capacitances at the output of each logic gate.

The second term, indicated as short-circuit power, represents the short-circuit current from the supply to the ground voltage during output transitions.

There are three most contributions of average power consumption in digital CMOS circuits which are summarized in the following equation: [4]

leakage circuit

short switching

avg

P P P

P = +

+

= α

C

⋅ V

⋅ f

+ I

⋅ V

+ I

⋅ V

The first represents the switching power, where CL is the load capacitance, Vdd is the

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supply voltage, fclk is the clock frequency and α0→1 is the node switching activity factor (the average number of times the node makes a power consuming transition in one clock period).

Let us analyze each contribution in detail, considering a simple static CMOS gate, an inverter, as a motivating example. Other combinational and sequential gates show a similar behavior. Figure 2-1 shows the structure of the generic static CMOS inverter.

The pull-up network is built with PMOS transistors (T1 for the selected inverter) and it connects the output node Vout to the power supply Vdd. Conversely, the pull-down network is composed of NMOS transistors (T2 for the selected inverter) and it connects the output node to the ground node Vss. In CMOS gates, the structure of the pull-up and pull-down network is such that when the circuit is stable (i.e. after the output rise or fall transients are exhausted) the output node is never connected to both Vdd and Vss at the same time.

Figure 2-1: The structure of a CMOS inverter

When an input transition causes a change in the conductive state of the pull-up and the pull-down network, the electric charge is transferred from the power supply to the output capacitance CL or from the output capacitance to ground. The transition causes power dissipation on the resistive pull-up and pull-down networks. Let us

consider a rising output transition (see Figure 6-a). Power is by definition Psw (t) = d E(t) / dt = id (t) v (t), where id (t) is the current drawn from the supply and v (t) is the supply voltage Vdd. The total energy provided by the supply is [13]:

∫

∫

= ^{r dd}

T V

dd out out L dd d

r i t v t dt V C dV C V

E

0 0

) 2

( ) (

where Tr is the time interval long enough for the transient exhaustion. Notice that we implicitly assume that all current provided by Vdd is used to charge the output capacitance. We also assume the output capacitance to be a constant.

At the end of the transition, the output capacitance is charged to Vdd, and the energy stored in it is given by: . Hence, the total energy dissipated by T1

during the 0→1 output transition is: .

2 2

/

1 _{L dd}

s C V

E =

2 2

2 1/2 _{L dd} 1/2 _{L dd}

dd L

d C V C V C V

E = − =

(a) (b) Figure 2-2: (a) The 0→1 and (b) 1→0

If we consider the falling output transition (see Figure 6-b), no energy is stored in the output capacitance. For the conservation of the energy, the total energy dissipated

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by T2 during a falling output transition is given by . This derivation leads us to the fundamental expression of the switching power consumption [13]:

2 2

/

1 _{L dd}

s C V

E =

f V C P_sw =α _{L dd}²

where CL is the load capacitance, Vdd is the supply voltage, f is the clock frequency and αis the node switching activity factor.

Factor CL is decided once the manufacture process has been chosen. Decreasing the Vdd factor has a quadratic effect and can be an effective way. However, the supply voltage is usually determined by the system and technology consideration, and decreasing Vdd will accordingly increase the propagation delay. The computing time will be definitely extended by reducing the factor f, clock speed. It is an unacceptable defect to trade performance of embedded system that usually has real-time demands.

Moreover, the power of other idle modules cannot be omitted since execution time increases. Therefore, the most important factor that distinguishes power is its dependence on the switching activity.

There are two ways to cut-down the switching activity on buses in execution time,

1. Reducing transaction counts:

Reducing requests of memory access is a direct approach to reduce bit transitions on buses. Buses can keep idle and eliminate power consumption since requests are saved. To increase the reusability of transmitted values is a common example of this idea.

2. Reducing numbers of switch activities per transaction:

Reducing numbers of switch activities per transaction that make the current transmitted bits near previous ones can reduce number of capacitances needed to be driven. Bus masking is a general technique

to eliminate variability between two sequential accesses.