Summary and Conclusion
In summary, we have proposed strain proximity free technique (SPFT) in nMOSETs, it could be solve etch processes problems with dense structure in logic CMOS circuit. We found that the transconductance (GM) exhibits an 16% increase and drain current improve 10% at channel length 0.4μm of nMOFETs with SPFT and the hot carrier stress would not serious damage. A multiple strain-gate engineering that utilizes the SPFT and a stacked a-Si/poly-Si gate structure. The GM and current drivability could be improved by controlling the SPFT process and the thickness of stacked gate structure. Without the limitation of stressor volume in high density CMOS circuits, we believe this scheme, by using both SPFT and stacked a-Si/poly-Si gate structure will provide us a guide line to keep continuous improvement in future CMOS technology.
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